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PCI: Return more meaningful error codes from ReadConfig/WriteConfig.

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This commit is contained in:
Augustin Cavalier
2024-07-09 11:36:50 -04:00
parent 342a1b221b
commit 599a303e23
3 changed files with 16 additions and 16 deletions
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src/add-ons/kernel/busses/pci/designware/DWPCIController.cpp
+4 -4
View File
@@ -331,14 +331,14 @@ DWPCIController::ReadConfig(uint8 bus, uint8 device, uint8 function,
addr_t address = ConfigAddress(bus, device, function, offset); addr_t address = ConfigAddress(bus, device, function, offset);
if (address == 0) if (address == 0)
return B_ERROR; return ERANGE;
switch (size) { switch (size) {
case 1: value = ReadReg8(address); break; case 1: value = ReadReg8(address); break;
case 2: value = ReadReg16(address); break; case 2: value = ReadReg16(address); break;
case 4: value = *(vuint32*)address; break; case 4: value = *(vuint32*)address; break;
default: default:
return B_ERROR; return B_BAD_VALUE;
} }
return B_OK; return B_OK;
@@ -353,14 +353,14 @@ DWPCIController::WriteConfig(uint8 bus, uint8 device, uint8 function,
addr_t address = ConfigAddress(bus, device, function, offset); addr_t address = ConfigAddress(bus, device, function, offset);
if (address == 0) if (address == 0)
return B_ERROR; return ERANGE;
switch (size) { switch (size) {
case 1: WriteReg8(address, value); break; case 1: WriteReg8(address, value); break;
case 2: WriteReg16(address, value); break; case 2: WriteReg16(address, value); break;
case 4: *(vuint32*)address = value; break; case 4: *(vuint32*)address = value; break;
default: default:
return B_ERROR; return B_BAD_VALUE;
} }
return B_OK; return B_OK;
src/add-ons/kernel/busses/pci/ecam/ECAMPCIController.cpp
+4 -4
View File
@@ -184,14 +184,14 @@ ECAMPCIController::ReadConfig(uint8 bus, uint8 device, uint8 function,
{ {
addr_t address = ConfigAddress(bus, device, function, offset); addr_t address = ConfigAddress(bus, device, function, offset);
if (address == 0) if (address == 0)
return B_ERROR; return ERANGE;
switch (size) { switch (size) {
case 1: value = ReadReg8(address); break; case 1: value = ReadReg8(address); break;
case 2: value = ReadReg16(address); break; case 2: value = ReadReg16(address); break;
case 4: value = *(vuint32*)address; break; case 4: value = *(vuint32*)address; break;
default: default:
return B_ERROR; return B_BAD_VALUE;
} }
return B_OK; return B_OK;
@@ -204,14 +204,14 @@ ECAMPCIController::WriteConfig(uint8 bus, uint8 device, uint8 function,
{ {
addr_t address = ConfigAddress(bus, device, function, offset); addr_t address = ConfigAddress(bus, device, function, offset);
if (address == 0) if (address == 0)
return B_ERROR; return ERANGE;
switch (size) { switch (size) {
case 1: WriteReg8(address, value); break; case 1: WriteReg8(address, value); break;
case 2: WriteReg16(address, value); break; case 2: WriteReg16(address, value); break;
case 4: *(vuint32*)address = value; break; case 4: *(vuint32*)address = value; break;
default: default:
return B_ERROR; return B_BAD_VALUE;
} }
return B_OK; return B_OK;
src/add-ons/kernel/busses/pci/x86/X86PCIController.cpp
+8 -8
View File
@@ -190,7 +190,7 @@ X86PCIControllerMeth1::ReadConfig(
uint16 offset, uint8 size, uint32 &value) uint16 offset, uint8 size, uint32 &value)
{ {
if (offset > 0xff) if (offset > 0xff)
return B_BAD_VALUE; return ERANGE;
InterruptsSpinLocker lock(fLock); InterruptsSpinLocker lock(fLock);
out32(PCI_MECH1_REQ_DATA(bus, device, function, offset), PCI_MECH1_REQ_PORT); out32(PCI_MECH1_REQ_DATA(bus, device, function, offset), PCI_MECH1_REQ_PORT);
@@ -205,7 +205,7 @@ X86PCIControllerMeth1::ReadConfig(
value = in32(PCI_MECH1_DATA_PORT); value = in32(PCI_MECH1_DATA_PORT);
break; break;
default: default:
return B_ERROR; return B_BAD_VALUE;
} }
return B_OK; return B_OK;
@@ -218,7 +218,7 @@ X86PCIControllerMeth1::WriteConfig(
uint16 offset, uint8 size, uint32 value) uint16 offset, uint8 size, uint32 value)
{ {
if (offset > 0xff) if (offset > 0xff)
return B_BAD_VALUE; return ERANGE;
InterruptsSpinLocker lock(fLock); InterruptsSpinLocker lock(fLock);
out32(PCI_MECH1_REQ_DATA(bus, device, function, offset), PCI_MECH1_REQ_PORT); out32(PCI_MECH1_REQ_DATA(bus, device, function, offset), PCI_MECH1_REQ_PORT);
@@ -233,7 +233,7 @@ X86PCIControllerMeth1::WriteConfig(
out32(value, PCI_MECH1_DATA_PORT); out32(value, PCI_MECH1_DATA_PORT);
break; break;
default: default:
return B_ERROR; return B_BAD_VALUE;
} }
return B_OK; return B_OK;
@@ -273,7 +273,7 @@ X86PCIControllerMeth2::ReadConfig(
uint16 offset, uint8 size, uint32 &value) uint16 offset, uint8 size, uint32 &value)
{ {
if (offset > 0xff) if (offset > 0xff)
return B_BAD_VALUE; return ERANGE;
InterruptsSpinLocker lock(fLock); InterruptsSpinLocker lock(fLock);
out8((uint8)(0xf0 | (function << 1)), PCI_MECH2_ENABLE_PORT); out8((uint8)(0xf0 | (function << 1)), PCI_MECH2_ENABLE_PORT);
@@ -289,7 +289,7 @@ X86PCIControllerMeth2::ReadConfig(
value = in32(PCI_MECH2_CONFIG_PORT(device, offset)); value = in32(PCI_MECH2_CONFIG_PORT(device, offset));
break; break;
default: default:
return B_ERROR; return B_BAD_VALUE;
} }
out8(0, PCI_MECH2_ENABLE_PORT); out8(0, PCI_MECH2_ENABLE_PORT);
@@ -303,7 +303,7 @@ X86PCIControllerMeth2::WriteConfig(
uint16 offset, uint8 size, uint32 value) uint16 offset, uint8 size, uint32 value)
{ {
if (offset > 0xff) if (offset > 0xff)
return B_BAD_VALUE; return ERANGE;
InterruptsSpinLocker lock(fLock); InterruptsSpinLocker lock(fLock);
out8((uint8)(0xf0 | (function << 1)), PCI_MECH2_ENABLE_PORT); out8((uint8)(0xf0 | (function << 1)), PCI_MECH2_ENABLE_PORT);
@@ -319,7 +319,7 @@ X86PCIControllerMeth2::WriteConfig(
out32(value, PCI_MECH2_CONFIG_PORT(device, offset)); out32(value, PCI_MECH2_CONFIG_PORT(device, offset));
break; break;
default: default:
return B_ERROR; return B_BAD_VALUE;
} }
out8(0, PCI_MECH2_ENABLE_PORT); out8(0, PCI_MECH2_ENABLE_PORT);