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setup hardware cursor. bitmap not yet correct, colors neither.

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@13633 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2005-07-11 15:29:50 +00:00
parent 9784ce8df4
commit 5de64e32fd
8 changed files with 131 additions and 168 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/add-ons/accelerants/via/GetAccelerantHook.c
+1 -1
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@@ -4,7 +4,7 @@
Other authors: Other authors:
Mark Watson, Mark Watson,
Rudolf Cornelissen 10/2002-4/2004 Rudolf Cornelissen 10/2002-7/2005
*/ */
#define MODULE_BIT 0x08000000 #define MODULE_BIT 0x08000000
src/add-ons/accelerants/via/InitAccelerant.c
+4 -3
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@@ -4,7 +4,7 @@
Other authors: Other authors:
Mark Watson, Mark Watson,
Rudolf Cornelissen 10/2002-7/2004. Rudolf Cornelissen 10/2002-7/2005.
*/ */
#define MODULE_BIT 0x00800000 #define MODULE_BIT 0x00800000
@@ -153,8 +153,9 @@ status_t INIT_ACCELERANT(int the_fd) {
to the app_server later. to the app_server later.
*/ */
pointer_reservation = 0; pointer_reservation = 0;
/* Nvidia hardcursor needs 2kB space */ /* VIA hardcursor needs 4kB space */
if (si->settings.hardcursor) pointer_reservation = 2048; //rud: shutoff until adress of FB is programmed! <<<<<<<<<<
// if (si->settings.hardcursor) pointer_reservation = 4096;
si->fbc.frame_buffer = (void *)((char *)si->framebuffer+pointer_reservation); si->fbc.frame_buffer = (void *)((char *)si->framebuffer+pointer_reservation);
si->fbc.frame_buffer_dma = (void *)((char *)si->framebuffer_pci+pointer_reservation); si->fbc.frame_buffer_dma = (void *)((char *)si->framebuffer_pci+pointer_reservation);
src/add-ons/accelerants/via/engine/agp.c
+4 -4
View File
@@ -25,15 +25,15 @@ status_t eng_agp_setup(void)
// { // {
// uint32 reg; // uint32 reg;
// LOG(4, ("AGP: STRAPINFO2 contains $%08x\n", ENG_RG32(RG32_NVSTRAPINFO2))); // LOG(4, ("AGP: STRAPINFO2 contains $%08x\n", ENG_REG32(RG32_NVSTRAPINFO2)));
// LOG(4, ("AGP: attempting to enable fastwrite support..\n")); // LOG(4, ("AGP: attempting to enable fastwrite support..\n"));
/* 'force' FW support */ /* 'force' FW support */
// reg = (ENG_RG32(RG32_NVSTRAPINFO2) & ~0x00000800); // reg = (ENG_REG32(RG32_NVSTRAPINFO2) & ~0x00000800);
/* enable strapinfo overwrite */ /* enable strapinfo overwrite */
// ENG_RG32(RG32_NVSTRAPINFO2) = (reg | 0x80000000); // ENG_REG32(RG32_NVSTRAPINFO2) = (reg | 0x80000000);
// LOG(4, ("AGP: STRAPINFO2 now contains $%08x\n", ENG_RG32(RG32_NVSTRAPINFO2))); // LOG(4, ("AGP: STRAPINFO2 now contains $%08x\n", ENG_REG32(RG32_NVSTRAPINFO2)));
// } // }
/* set the magic number so the skeleton kerneldriver knows we're for real */ /* set the magic number so the skeleton kerneldriver knows we're for real */
src/add-ons/accelerants/via/engine/bes.c
+4 -4
View File
@@ -357,16 +357,16 @@ status_t eng_bes_to_crtc(bool crtc)
{ {
LOG(4,("Overlay: switching overlay to CRTC2\n")); LOG(4,("Overlay: switching overlay to CRTC2\n"));
/* switch overlay engine to CRTC2 */ /* switch overlay engine to CRTC2 */
ENG_RG32(RG32_FUNCSEL) &= ~0x00001000; ENG_REG32(RG32_FUNCSEL) &= ~0x00001000;
ENG_RG32(RG32_2FUNCSEL) |= 0x00001000; ENG_REG32(RG32_2FUNCSEL) |= 0x00001000;
si->overlay.crtc = !si->crtc_switch_mode; si->overlay.crtc = !si->crtc_switch_mode;
} }
else else
{ {
LOG(4,("Overlay: switching overlay to CRTC1\n")); LOG(4,("Overlay: switching overlay to CRTC1\n"));
/* switch overlay engine to CRTC1 */ /* switch overlay engine to CRTC1 */
ENG_RG32(RG32_2FUNCSEL) &= ~0x00001000; ENG_REG32(RG32_2FUNCSEL) &= ~0x00001000;
ENG_RG32(RG32_FUNCSEL) |= 0x00001000; ENG_REG32(RG32_FUNCSEL) |= 0x00001000;
si->overlay.crtc = si->crtc_switch_mode; si->overlay.crtc = si->crtc_switch_mode;
} }
return B_OK; return B_OK;
src/add-ons/accelerants/via/engine/crtc.c
+44 -82
View File
@@ -1,6 +1,6 @@
/* CTRC functionality */ /* CTRC functionality */
/* Author: /* Author:
Rudolf Cornelissen 11/2002-9/2004 Rudolf Cornelissen 11/2002-7/2005
*/ */
#define MODULE_BIT 0x00040000 #define MODULE_BIT 0x00040000
@@ -610,7 +610,7 @@ status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp)
/* we might have no retraces during setmode! */ /* we might have no retraces during setmode! */
/* wait 25mS max. for retrace to occur (refresh > 40Hz) */ /* wait 25mS max. for retrace to occur (refresh > 40Hz) */
while (((ENG_RG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display) && while (((ENG_REG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display) &&
(timeout < (25000/10))) (timeout < (25000/10)))
{ {
/* don't snooze much longer or retrace might get missed! */ /* don't snooze much longer or retrace might get missed! */
@@ -646,7 +646,7 @@ status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp)
* wrap-around at 16Mb boundaries!! */ * wrap-around at 16Mb boundaries!! */
/* 30bit adress in 32bit words */ /* 30bit adress in 32bit words */
ENG_RG32(RG32_NV10FBSTADD32) = (startadd & 0xfffffffc); ENG_REG32(RG32_NV10FBSTADD32) = (startadd & 0xfffffffc);
} }
/* set NV4/NV10 byte adress: (b0 - 1) */ /* set NV4/NV10 byte adress: (b0 - 1) */
@@ -662,11 +662,8 @@ status_t eng_crtc_cursor_init()
/* cursor bitmap will be stored at the start of the framebuffer */ /* cursor bitmap will be stored at the start of the framebuffer */
const uint32 curadd = 0; const uint32 curadd = 0;
/* enable access to primary head */
set_crtc_owner(0);
/* set cursor bitmap adress ... */ /* set cursor bitmap adress ... */
if ((si->ps.card_arch == NV04A) || (si->ps.laptop)) if (0)//(si->ps.card_arch == NV04A) || (si->ps.laptop))
{ {
/* must be used this way on pre-NV10 and on all 'Go' cards! */ /* must be used this way on pre-NV10 and on all 'Go' cards! */
@@ -686,20 +683,24 @@ status_t eng_crtc_cursor_init()
* This register does not exist on pre-NV10 and 'Go' cards. */ * This register does not exist on pre-NV10 and 'Go' cards. */
/* cursorbitmap must still start on 2Kbyte boundary: */ /* cursorbitmap must still start on 2Kbyte boundary: */
ENG_RG32(RG32_NV10CURADD32) = (curadd & 0xfffff800); //via
/* background is black */
CRTCDW(CURSOR_BG, 0x00000000);
/* foreground is white */
CRTCDW(CURSOR_FG, 0x00ffffff);
/* set cursor bitmap adress */
CRTCDW(CURSOR_MODE, (curadd & 0xfffffffc));
} }
/* set cursor colour: not needed because of direct nature of cursor bitmap. */ /* clear cursor (via cursor uses 4kb) */
/*clear cursor*/
fb = (uint32 *) si->framebuffer + curadd; fb = (uint32 *) si->framebuffer + curadd;
for (i=0;i<(2048/4);i++) for (i=0;i<(4096/4);i++)
{ {
fb[i]=0; fb[i]=0;
} }
/* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */
ENG_RG32(RG32_CURCONF) = 0x02000100; // ENG_REG32(RG32_CURCONF) = 0x02000100;
/* activate hardware cursor */ /* activate hardware cursor */
eng_crtc_cursor_show(); eng_crtc_cursor_show();
@@ -710,12 +711,7 @@ status_t eng_crtc_cursor_init()
status_t eng_crtc_cursor_show() status_t eng_crtc_cursor_show()
{ {
LOG(4,("CRTC: enabling cursor\n")); LOG(4,("CRTC: enabling cursor\n"));
CRTCDW(CURSOR_MODE, (CRTCDR(CURSOR_MODE) | 0x00000003));
/* enable access to CRTC1 on dualhead cards */
set_crtc_owner(0);
/* b0 = 1 enables cursor */
CRTCW(CURCTL0, (CRTCR(CURCTL0) | 0x01));
return B_OK; return B_OK;
} }
@@ -723,12 +719,7 @@ status_t eng_crtc_cursor_show()
status_t eng_crtc_cursor_hide() status_t eng_crtc_cursor_hide()
{ {
LOG(4,("CRTC: disabling cursor\n")); LOG(4,("CRTC: disabling cursor\n"));
CRTCDW(CURSOR_MODE, (CRTCDR(CURSOR_MODE) & 0xfffffffc));
/* enable access to primary head */
set_crtc_owner(0);
/* b0 = 0 disables cursor */
CRTCW(CURCTL0, (CRTCR(CURCTL0) & 0xfe));
return B_OK; return B_OK;
} }
@@ -736,50 +727,50 @@ status_t eng_crtc_cursor_hide()
/*set up cursor shape*/ /*set up cursor shape*/
status_t eng_crtc_cursor_define(uint8* andMask,uint8* xorMask) status_t eng_crtc_cursor_define(uint8* andMask,uint8* xorMask)
{ {
int x, y; int y;
uint8 b; uint8 b,s;
uint16 *cursor; uint16 *cursor;
uint16 pixel; uint16 data;
/* get a pointer to the cursor */ /* get a pointer to the cursor */
cursor = (uint16*) si->framebuffer; cursor = (uint16*) si->framebuffer;
/* draw the cursor */ /* draw the cursor */
/* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */
for (y = 0; y < 16; y++) for (y = 0; y < 16; y++)
{ {
b = 0x80; b = 0x01;
for (x = 0; x < 8; x++)
{
/* preset transparant */ /* preset transparant */
pixel = 0x0000; data = 0x0000;
for (s = 0; s < 15; s += 2)
{
/* set white if requested */ /* set white if requested */
if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; if ((!(*andMask & b)) && (!(*xorMask & b))) data |= (0x0003 << s);
/* set black if requested */ /* set black if requested */
if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; if ((!(*andMask & b)) && (*xorMask & b)) data |= (0x0002 << s);
/* set invert if requested */ /* set invert if requested */
if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; if ( (*andMask & b) && (*xorMask & b)) data |= (0x0001 << s);
/* place the pixel in the bitmap */ b <<= 1;
cursor[x + (y * 32)] = pixel;
b >>= 1;
} }
/* place the 8 pixels in the bitmap */
cursor[0 + (y * 4)] = data;
xorMask++; xorMask++;
andMask++; andMask++;
b = 0x80;
for (; x < 16; x++) b = 0x01;
{
/* preset transparant */ /* preset transparant */
pixel = 0x0000; data = 0x0000;
for (s = 0; s < 15; s += 2)
{
/* set white if requested */ /* set white if requested */
if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; if ((!(*andMask & b)) && (!(*xorMask & b))) data |= (0x0003 << s);
/* set black if requested */ /* set black if requested */
if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; if ((!(*andMask & b)) && (*xorMask & b)) data |= (0x0002 << s);
/* set invert if requested */ /* set invert if requested */
if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; if ( (*andMask & b) && (*xorMask & b)) data |= (0x0001 << s);
/* place the pixel in the bitmap */ b <<= 1;
cursor[x + (y * 32)] = pixel;
b >>= 1;
} }
/* place the 8 pixels in the bitmap */
cursor[1 + (y * 4)] = data;
xorMask++; xorMask++;
andMask++; andMask++;
} }
@@ -790,40 +781,11 @@ status_t eng_crtc_cursor_define(uint8* andMask,uint8* xorMask)
/* position the cursor */ /* position the cursor */
status_t eng_crtc_cursor_position(uint16 x, uint16 y) status_t eng_crtc_cursor_position(uint16 x, uint16 y)
{ {
uint16 yhigh; /* set cursor origin, b1-7 = Y offset; b17-23 = X offset
* (? linux seems non-consistent) */
/* make sure we are beyond the first line of the cursorbitmap being drawn during CRTCDW(CURSOR_ORG, 0x00000000);
* updating the position to prevent distortions: no double buffering feature */
/* Note:
* we need to return as quick as possible or some apps will exhibit lagging.. */
/* read the old cursor Y position */
yhigh = ((DACR(CURPOS) & 0x0fff0000) >> 16);
/* make sure we will wait until we are below both the old and new Y position:
* visible cursorbitmap drawing needs to be done at least... */
if (y > yhigh) yhigh = y;
if (yhigh < (si->dm.timing.v_display - 16))
{
/* we have vertical lines below old and new cursorposition to spare. So we
* update the cursor postion 'mid-screen', but below that area. */
while (((uint16)(ENG_RG32(RG32_RASTER) & 0x000007ff)) < (yhigh + 16))
{
snooze(10);
}
}
else
{
/* no room to spare, just wait for retrace (is relatively slow) */
while ((ENG_RG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display)
{
/* don't snooze much longer or retrace might get missed! */
snooze(10);
}
}
/* update cursorposition */ /* update cursorposition */
DACW(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16))); CRTCDW(CURSOR_POS, (((x & 0x07ff) << 16) | (y & 0x07ff)));
return B_OK; return B_OK;
} }
src/add-ons/accelerants/via/engine/crtc2.c
+6 -6
View File
@@ -592,7 +592,7 @@ status_t eng_crtc2_set_display_start(uint32 startadd,uint8 bpp)
/* we might have no retraces during setmode! */ /* we might have no retraces during setmode! */
/* wait 25mS max. for retrace to occur (refresh > 40Hz) */ /* wait 25mS max. for retrace to occur (refresh > 40Hz) */
while (((ENG_RG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && while (((ENG_REG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) &&
(timeout < (25000/10))) (timeout < (25000/10)))
{ {
/* don't snooze much longer or retrace might get missed! */ /* don't snooze much longer or retrace might get missed! */
@@ -609,7 +609,7 @@ status_t eng_crtc2_set_display_start(uint32 startadd,uint8 bpp)
* wrap-around at 16Mb boundaries!! */ * wrap-around at 16Mb boundaries!! */
/* 30bit adress in 32bit words */ /* 30bit adress in 32bit words */
ENG_RG32(RG32_NV10FB2STADD32) = (startadd & 0xfffffffc); ENG_REG32(RG32_NV10FB2STADD32) = (startadd & 0xfffffffc);
/* set byte adress: (b0 - 1) */ /* set byte adress: (b0 - 1) */
ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1)); ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1));
@@ -648,7 +648,7 @@ status_t eng_crtc2_cursor_init()
* This register does not exist on pre-NV10 and 'Go' cards. */ * This register does not exist on pre-NV10 and 'Go' cards. */
/* cursorbitmap must still start on 2Kbyte boundary: */ /* cursorbitmap must still start on 2Kbyte boundary: */
ENG_RG32(RG32_NV10CUR2ADD32) = (curadd & 0xfffff800); ENG_REG32(RG32_NV10CUR2ADD32) = (curadd & 0xfffff800);
} }
/* set cursor colour: not needed because of direct nature of cursor bitmap. */ /* set cursor colour: not needed because of direct nature of cursor bitmap. */
@@ -661,7 +661,7 @@ status_t eng_crtc2_cursor_init()
} }
/* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */
ENG_RG32(RG32_2CURCONF) = 0x02000100; ENG_REG32(RG32_2CURCONF) = 0x02000100;
/* activate hardware cursor */ /* activate hardware cursor */
eng_crtc2_cursor_show(); eng_crtc2_cursor_show();
@@ -769,7 +769,7 @@ status_t eng_crtc2_cursor_position(uint16 x, uint16 y)
{ {
/* we have vertical lines below old and new cursorposition to spare. So we /* we have vertical lines below old and new cursorposition to spare. So we
* update the cursor postion 'mid-screen', but below that area. */ * update the cursor postion 'mid-screen', but below that area. */
while (((uint16)(ENG_RG32(RG32_RASTER2) & 0x000007ff)) < (yhigh + 16)) while (((uint16)(ENG_REG32(RG32_RASTER2) & 0x000007ff)) < (yhigh + 16))
{ {
snooze(10); snooze(10);
} }
@@ -777,7 +777,7 @@ status_t eng_crtc2_cursor_position(uint16 x, uint16 y)
else else
{ {
/* no room to spare, just wait for retrace (is relatively slow) */ /* no room to spare, just wait for retrace (is relatively slow) */
while ((ENG_RG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) while ((ENG_REG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display)
{ {
/* don't snooze much longer or retrace might get missed! */ /* don't snooze much longer or retrace might get missed! */
snooze(10); snooze(10);
src/add-ons/accelerants/via/engine/general.c
+6 -6
View File
@@ -90,7 +90,7 @@ status_t eng_general_powerup()
{ {
status_t status; status_t status;
LOG(1,("POWERUP: Haiku skeleton Accelerant 0.01 running.\n")); LOG(1,("POWERUP: Haiku VIA Accelerant 0.01 running.\n"));
/* preset no laptop */ /* preset no laptop */
si->ps.laptop = false; si->ps.laptop = false;
@@ -102,7 +102,7 @@ status_t eng_general_powerup()
case 0x31221106: /* */ case 0x31221106: /* */
si->ps.card_type = NV04; si->ps.card_type = NV04;
si->ps.card_arch = NV04A; si->ps.card_arch = NV04A;
LOG(4,("POWERUP: Detected Nvidia TNT1 (NV04)\n")); LOG(4,("POWERUP: Detected VIA CLE266 Unichrome\n"));
status = engxx_general_powerup(); status = engxx_general_powerup();
break; break;
default: default:
@@ -416,7 +416,7 @@ status_t eng_general_head_select(bool cross)
static status_t eng_general_bios_to_powergraphics() static status_t eng_general_bios_to_powergraphics()
{ {
/* let acc engine make power off/power on cycle to start 'fresh' */ /* let acc engine make power off/power on cycle to start 'fresh' */
// ENG_RG32(RG32_PWRUPCTRL) = 0x13110011; // ENG_REG32(RG32_PWRUPCTRL) = 0x13110011;
snooze(1000); snooze(1000);
/* power-up all hardware function blocks */ /* power-up all hardware function blocks */
@@ -429,7 +429,7 @@ static status_t eng_general_bios_to_powergraphics()
* bit 8: PFIFO, * bit 8: PFIFO,
* bit 4: PMEDIA, * bit 4: PMEDIA,
* bit 0: TVOUT. (> NV04A) */ * bit 0: TVOUT. (> NV04A) */
// ENG_RG32(RG32_PWRUPCTRL) = 0x13111111; // ENG_REG32(RG32_PWRUPCTRL) = 0x13111111;
/* select colormode CRTC registers base adresses */ /* select colormode CRTC registers base adresses */
// ENG_REG8(RG8_MISCW) = 0xcb; // ENG_REG8(RG8_MISCW) = 0xcb;
@@ -469,8 +469,8 @@ static status_t eng_general_bios_to_powergraphics()
* bit 9: TVout chip #2 (confirmed on NV18, NV25, NV28), * bit 9: TVout chip #2 (confirmed on NV18, NV25, NV28),
* bit 8: TVout chip #1 (all cards), * bit 8: TVout chip #1 (all cards),
* bit 4: both I2C busses (all cards) */ * bit 4: both I2C busses (all cards) */
ENG_RG32(RG32_2FUNCSEL) &= ~0x00001000; ENG_REG32(RG32_2FUNCSEL) &= ~0x00001000;
ENG_RG32(RG32_FUNCSEL) |= 0x00001000; ENG_REG32(RG32_FUNCSEL) |= 0x00001000;
} }
si->overlay.crtc = false; si->overlay.crtc = false;
src/add-ons/accelerants/via/engine/info.c
+62 -62
View File
@@ -311,8 +311,8 @@ static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_ta
//fixme?: works on at least one NV28... how about other cards? //fixme?: works on at least one NV28... how about other cards?
if (si->ps.card_type == NV28) if (si->ps.card_type == NV28)
{ {
fb_mrs2 = ENG_RG32(RG32_FB_MRS2); fb_mrs2 = ENG_REG32(RG32_FB_MRS2);
fb_mrs1 = ENG_RG32(RG32_FB_MRS1); fb_mrs1 = ENG_REG32(RG32_FB_MRS1);
} }
/* select colormode CRTC registers base adresses */ /* select colormode CRTC registers base adresses */
@@ -381,8 +381,8 @@ static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_ta
/* get NV28 RAM access up and running */ /* get NV28 RAM access up and running */
//fixme?: works on at least one NV28... how about other cards? //fixme?: works on at least one NV28... how about other cards?
ENG_RG32(RG32_FB_MRS2) = fb_mrs2; ENG_REG32(RG32_FB_MRS2) = fb_mrs2;
ENG_RG32(RG32_FB_MRS1) = fb_mrs1; ENG_REG32(RG32_FB_MRS1) = fb_mrs1;
} }
/* now enable ROM shadow or the card will remain shut-off! */ /* now enable ROM shadow or the card will remain shut-off! */
@@ -448,7 +448,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
float calced_clk; float calced_clk;
uint8 m, n, p; uint8 m, n, p;
eng_dac_sys_pll_find(((float)data2), &calced_clk, &m, &n, &p, 0); eng_dac_sys_pll_find(((float)data2), &calced_clk, &m, &n, &p, 0);
ENG_RG32(reg) = ((p << 16) | (n << 8) | m); ENG_REG32(reg) = ((p << 16) | (n << 8) | m);
} }
log_pll(reg, data2); log_pll(reg, data2);
break; break;
@@ -470,7 +470,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
adress += 2; adress += 2;
data2 = *((uint32*)(&(rom[data]))); data2 = *((uint32*)(&(rom[data])));
LOG(8,("cmd 'WR indirect 32bit reg' $%08x = $%08x\n", reg, data2)); LOG(8,("cmd 'WR indirect 32bit reg' $%08x = $%08x\n", reg, data2));
if (exec) ENG_RG32(reg) = data2; if (exec) ENG_REG32(reg) = data2;
break; break;
case 0x63: case 0x63:
*size -= 1; *size -= 1;
@@ -509,8 +509,8 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n", LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n",
reg, data, data2)); reg, data, data2));
/* always done */ /* always done */
ENG_RG32(reg) = data; ENG_REG32(reg) = data;
ENG_RG32(reg) = data2; ENG_REG32(reg) = data2;
CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe)); CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe));
break; break;
case 0x69: case 0x69:
@@ -554,7 +554,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
/* execute */ /* execute */
adress += 1; adress += 1;
data = ENG_RG32(RG32_NV4STRAPINFO); data = ENG_REG32(RG32_NV4STRAPINFO);
and_out = *((uint8*)(&(rom[adress]))); and_out = *((uint8*)(&(rom[adress])));
adress += 1; adress += 1;
byte = *((uint8*)(&(rom[adress]))); byte = *((uint8*)(&(rom[adress])));
@@ -594,10 +594,10 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
reg, and_out, or_in)); reg, and_out, or_in));
if (exec) if (exec)
{ {
data = ENG_RG32(reg); data = ENG_REG32(reg);
data &= and_out; data &= and_out;
data |= or_in; data |= or_in;
ENG_RG32(reg) = data; ENG_REG32(reg) = data;
} }
break; break;
case 0x71: case 0x71:
@@ -637,7 +637,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
/* execute */ /* execute */
adress += 1; adress += 1;
data = ENG_RG32(RG32_NVSTRAPINFO2); data = ENG_REG32(RG32_NVSTRAPINFO2);
and_out = *((uint32*)(&(rom[adress]))); and_out = *((uint32*)(&(rom[adress])));
adress += 4; adress += 4;
data2 = *((uint32*)(&(rom[adress]))); data2 = *((uint32*)(&(rom[adress])));
@@ -691,7 +691,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
adress += 2; adress += 2;
LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x (b31-16 = '0', b15-0 = data)\n", LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x (b31-16 = '0', b15-0 = data)\n",
reg, data)); reg, data));
if (exec) ENG_RG32(reg) = data; if (exec) ENG_REG32(reg) = data;
break; break;
case 0x78: case 0x78:
*size -= 6; *size -= 6;
@@ -747,7 +747,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
float calced_clk; float calced_clk;
uint8 m, n, p; uint8 m, n, p;
eng_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0); eng_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0);
ENG_RG32(reg) = ((p << 16) | (n << 8) | m); ENG_REG32(reg) = ((p << 16) | (n << 8) | m);
} }
log_pll(reg, (data / 100)); log_pll(reg, (data / 100));
break; break;
@@ -768,7 +768,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
data = *((uint32*)(&(rom[adress]))); data = *((uint32*)(&(rom[adress])));
adress += 4; adress += 4;
LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data)); LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data));
if (exec) ENG_RG32(reg) = data; if (exec) ENG_REG32(reg) = data;
break; break;
default: default:
LOG(8,("unknown cmd, aborting!\n\n")); LOG(8,("unknown cmd, aborting!\n\n"));
@@ -828,9 +828,9 @@ static void setup_ram_config(uint8* rom, uint16 ram_tab)
uint8 cnt; uint8 cnt;
/* set MRS = 256 */ /* set MRS = 256 */
ENG_RG32(RG32_PFB_DEBUG_0) &= 0xffffffef; ENG_REG32(RG32_PFB_DEBUG_0) &= 0xffffffef;
/* read RAM config hardware(?) strap */ /* read RAM config hardware(?) strap */
ram_cfg = ((ENG_RG32(RG32_NVSTRAPINFO2) >> 2) & 0x0000000f); ram_cfg = ((ENG_REG32(RG32_NVSTRAPINFO2) >> 2) & 0x0000000f);
LOG(8,("INFO: ---RAM config strap is $%01x\n", ram_cfg)); LOG(8,("INFO: ---RAM config strap is $%01x\n", ram_cfg));
/* use it as a pointer in a BIOS table for prerecorded RAM configurations */ /* use it as a pointer in a BIOS table for prerecorded RAM configurations */
ram_cfg = *((uint16*)(&(rom[(ram_tab + (ram_cfg * 2))]))); ram_cfg = *((uint16*)(&(rom[(ram_tab + (ram_cfg * 2))])));
@@ -876,15 +876,15 @@ static void setup_ram_config(uint8* rom, uint16 ram_tab)
break; break;
} }
/* set RAM amount, width and type */ /* set RAM amount, width and type */
data = (ENG_RG32(RG32_NV4STRAPINFO) & 0xffffffc0); data = (ENG_REG32(RG32_NV4STRAPINFO) & 0xffffffc0);
ENG_RG32(RG32_NV4STRAPINFO) = (data | (ram_cfg & 0x0000003f)); ENG_REG32(RG32_NV4STRAPINFO) = (data | (ram_cfg & 0x0000003f));
/* setup write to read delay (?) */ /* setup write to read delay (?) */
data = (ENG_RG32(RG32_PFB_CONFIG_1) & 0xff8ffffe); data = (ENG_REG32(RG32_PFB_CONFIG_1) & 0xff8ffffe);
data |= ((ram_cfg & 0x00000700) << 12); data |= ((ram_cfg & 0x00000700) << 12);
/* force update via b0 = 0... */ /* force update via b0 = 0... */
ENG_RG32(RG32_PFB_CONFIG_1) = data; ENG_REG32(RG32_PFB_CONFIG_1) = data;
/* ... followed by b0 = 1(?) */ /* ... followed by b0 = 1(?) */
ENG_RG32(RG32_PFB_CONFIG_1) = (data | 0x00000001); ENG_REG32(RG32_PFB_CONFIG_1) = (data | 0x00000001);
/* do RAM width test to confirm RAM width set to be correct */ /* do RAM width test to confirm RAM width set to be correct */
/* write testpattern to first 128 bits of graphics memory... */ /* write testpattern to first 128 bits of graphics memory... */
@@ -896,7 +896,7 @@ static void setup_ram_config(uint8* rom, uint16 ram_tab)
if (((uint32 *)si->framebuffer)[3] != data) if (((uint32 *)si->framebuffer)[3] != data)
{ {
LOG(8,("INFO: ---RAM width tested: width is 64bits, correcting settings.\n")); LOG(8,("INFO: ---RAM width tested: width is 64bits, correcting settings.\n"));
ENG_RG32(RG32_NV4STRAPINFO) &= ~0x00000004; ENG_REG32(RG32_NV4STRAPINFO) &= ~0x00000004;
} }
else else
{ {
@@ -963,11 +963,11 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
LOG(8,("INFO: (cont.) then WR result data to 32bit reg $%08x'\n", reg2)); LOG(8,("INFO: (cont.) then WR result data to 32bit reg $%08x'\n", reg2));
if (*exec && reg2) if (*exec && reg2)
{ {
data = ENG_RG32(reg); data = ENG_REG32(reg);
data &= and_out; data &= and_out;
data >>= shift; data >>= shift;
data2 = *((uint32*)(&(rom[(*adress + (data << 2))]))); data2 = *((uint32*)(&(rom[(*adress + (data << 2))])));
ENG_RG32(reg2) = data2; ENG_REG32(reg2) = data2;
} }
*adress += size32; *adress += size32;
break; break;
@@ -1009,7 +1009,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
byte >>= byte2; byte >>= byte2;
offset32 = (byte << 2); offset32 = (byte << 2);
data = *((uint32*)(&(rom[(*adress + offset32)]))); data = *((uint32*)(&(rom[(*adress + offset32)])));
ENG_RG32(reg2) = data; ENG_REG32(reg2) = data;
} }
*adress += size32; *adress += size32;
break; break;
@@ -1102,10 +1102,10 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
uint8 m, n, p; uint8 m, n, p;
eng_dac_sys_pll_find((data2 / 100.0), &calced_clk, &m, &n, &p, 0); eng_dac_sys_pll_find((data2 / 100.0), &calced_clk, &m, &n, &p, 0);
/* programming the PLL needs to be done in steps! (confirmed NV28) */ /* programming the PLL needs to be done in steps! (confirmed NV28) */
data = ENG_RG32(reg2); data = ENG_REG32(reg2);
ENG_RG32(reg2) = ((data & 0xffff0000) | (n << 8) | m); ENG_REG32(reg2) = ((data & 0xffff0000) | (n << 8) | m);
data = ENG_RG32(reg2); data = ENG_REG32(reg2);
ENG_RG32(reg2) = ((p << 16) | (n << 8) | m); ENG_REG32(reg2) = ((p << 16) | (n << 8) | m);
//fixme? //fixme?
/* program 2nd set N and M scalers if they exist (b31=1 enables them) */ /* program 2nd set N and M scalers if they exist (b31=1 enables them) */
// if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) // if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36))
@@ -1178,7 +1178,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
index, reg2, and_out2)); index, reg2, and_out2));
if (*exec) if (*exec)
{ {
data = ENG_RG32(reg); data = ENG_REG32(reg);
if (byte2 < 0x80) if (byte2 < 0x80)
{ {
data >>= byte2; data >>= byte2;
@@ -1274,12 +1274,12 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
*adress += 1; *adress += 1;
data2 = *((uint8*)(&(rom[*adress]))); data2 = *((uint8*)(&(rom[*adress])));
*adress += 1; *adress += 1;
ENG_RG32(reg2) = data2; ENG_REG32(reg2) = data2;
data = ENG_RG32(reg); data = ENG_REG32(reg);
data &= and_out; data &= and_out;
data |= or_in; data |= or_in;
data |= or_in2; data |= or_in2;
ENG_RG32(reg) = data; ENG_REG32(reg) = data;
} }
} }
else else
@@ -1380,8 +1380,8 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n", LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n",
reg, data, data2)); reg, data, data2));
/* always done */ /* always done */
ENG_RG32(reg) = data; ENG_REG32(reg) = data;
ENG_RG32(reg) = data2; ENG_REG32(reg) = data2;
CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe)); CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe));
break; break;
case 0x69: /* identical to type1 */ case 0x69: /* identical to type1 */
@@ -1479,10 +1479,10 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
reg, and_out, or_in)); reg, and_out, or_in));
if (*exec) if (*exec)
{ {
data = ENG_RG32(reg); data = ENG_REG32(reg);
data &= and_out; data &= and_out;
data |= or_in; data |= or_in;
ENG_RG32(reg) = data; ENG_REG32(reg) = data;
} }
break; break;
case 0x6f: /* new */ case 0x6f: /* new */
@@ -1522,7 +1522,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
{ {
reg2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3))]))); reg2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3))])));
data2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3) + 4)]))); data2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3) + 4)])));
ENG_RG32(reg2) = data2; ENG_REG32(reg2) = data2;
safe32++; safe32++;
} }
} }
@@ -1598,7 +1598,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
reg = *((uint32*)(&(rom[data]))); reg = *((uint32*)(&(rom[data])));
and_out = *((uint32*)(&(rom[(data + 4)]))); and_out = *((uint32*)(&(rom[(data + 4)])));
data2 = *((uint32*)(&(rom[(data + 8)]))); data2 = *((uint32*)(&(rom[(data + 8)])));
data = ENG_RG32(reg); data = ENG_REG32(reg);
data &= and_out; data &= and_out;
LOG(8,("cmd 'CHK bits AND-out $%08x reg $%08x for $%08x'\n", LOG(8,("cmd 'CHK bits AND-out $%08x reg $%08x for $%08x'\n",
and_out, reg, data2)); and_out, reg, data2));
@@ -1701,10 +1701,10 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
uint8 m, n, p; uint8 m, n, p;
eng_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0); eng_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0);
/* programming the PLL needs to be done in steps! (confirmed NV28) */ /* programming the PLL needs to be done in steps! (confirmed NV28) */
data2 = ENG_RG32(reg); data2 = ENG_REG32(reg);
ENG_RG32(reg) = ((data2 & 0xffff0000) | (n << 8) | m); ENG_REG32(reg) = ((data2 & 0xffff0000) | (n << 8) | m);
data2 = ENG_RG32(reg); data2 = ENG_REG32(reg);
ENG_RG32(reg) = ((p << 16) | (n << 8) | m); ENG_REG32(reg) = ((p << 16) | (n << 8) | m);
//fixme? //fixme?
/* program 2nd set N and M scalers if they exist (b31=1 enables them) */ /* program 2nd set N and M scalers if they exist (b31=1 enables them) */
// if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) // if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36))
@@ -1729,7 +1729,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
data = *((uint32*)(&(rom[*adress]))); data = *((uint32*)(&(rom[*adress])));
*adress += 4; *adress += 4;
LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data)); LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data));
if (*exec) ENG_RG32(reg) = data; if (*exec) ENG_REG32(reg) = data;
break; break;
default: default:
LOG(8,("unknown cmd, aborting!\n\n")); LOG(8,("unknown cmd, aborting!\n\n"));
@@ -1787,7 +1787,7 @@ static void setup_ram_config_nv10_up(uint8* rom)
status_t stat = B_ERROR; status_t stat = B_ERROR;
/* set 'refctrl is valid' */ /* set 'refctrl is valid' */
ENG_RG32(RG32_PFB_REFCTRL) = 0x80000000; ENG_REG32(RG32_PFB_REFCTRL) = 0x80000000;
/* check RAM for 256bits buswidth(?) */ /* check RAM for 256bits buswidth(?) */
while ((cnt < 4) && (stat != B_OK)) while ((cnt < 4) && (stat != B_OK))
@@ -1810,7 +1810,7 @@ static void setup_ram_config_nv10_up(uint8* rom)
if (stat != B_OK) if (stat != B_OK)
{ {
LOG(8,("INFO: ---RAM test #1 done: access errors, modified setup.\n")); LOG(8,("INFO: ---RAM test #1 done: access errors, modified setup.\n"));
data = ENG_RG32(RG32_PFB_CONFIG_0); data = ENG_REG32(RG32_PFB_CONFIG_0);
if (data & 0x00000010) if (data & 0x00000010)
{ {
data &= 0xffffffcf; data &= 0xffffffcf;
@@ -1820,7 +1820,7 @@ static void setup_ram_config_nv10_up(uint8* rom)
data &= 0xffffffcf; data &= 0xffffffcf;
data |= 0x00000020; data |= 0x00000020;
} }
ENG_RG32(RG32_PFB_CONFIG_0) = data; ENG_REG32(RG32_PFB_CONFIG_0) = data;
} }
else else
{ {
@@ -1833,7 +1833,7 @@ static void setup_ram_config_nv10_up(uint8* rom)
while ((cnt < 4) && (stat != B_OK)) while ((cnt < 4) && (stat != B_OK))
{ {
/* read RAM size */ /* read RAM size */
data = ENG_RG32(RG32_NV10STRAPINFO); data = ENG_REG32(RG32_NV10STRAPINFO);
/* subtract 1MB */ /* subtract 1MB */
data -= 0x00100000; data -= 0x00100000;
/* write testpattern at generated RAM adress */ /* write testpattern at generated RAM adress */
@@ -1854,7 +1854,7 @@ static void setup_ram_config_nv10_up(uint8* rom)
if (stat != B_OK) if (stat != B_OK)
{ {
LOG(8,("INFO: ---RAM test #2 done: access errors, modified setup.\n")); LOG(8,("INFO: ---RAM test #2 done: access errors, modified setup.\n"));
ENG_RG32(RG32_PFB_CONFIG_0) &= 0xffffefff; ENG_REG32(RG32_PFB_CONFIG_0) &= 0xffffefff;
} }
else else
{ {
@@ -1871,13 +1871,13 @@ static void setup_ram_config_nv28(uint8* rom)
status_t stat = B_ERROR; status_t stat = B_ERROR;
/* set 'refctrl is valid' */ /* set 'refctrl is valid' */
ENG_RG32(RG32_PFB_REFCTRL) = 0x80000000; ENG_REG32(RG32_PFB_REFCTRL) = 0x80000000;
/* check RAM */ /* check RAM */
while ((cnt < 4) && (stat != B_OK)) while ((cnt < 4) && (stat != B_OK))
{ {
/* set bit 11: 'pulse' something into a new setting? */ /* set bit 11: 'pulse' something into a new setting? */
ENG_RG32(RG32_PFB_CONFIG_0) |= 0x00000800; ENG_REG32(RG32_PFB_CONFIG_0) |= 0x00000800;
/* write testpattern to RAM adress 127Mb */ /* write testpattern to RAM adress 127Mb */
((uint32 *)si->framebuffer)[0x01fc0000] = 0x4e564441; ((uint32 *)si->framebuffer)[0x01fc0000] = 0x4e564441;
/* reset first RAM adress */ /* reset first RAM adress */
@@ -1897,7 +1897,7 @@ static void setup_ram_config_nv28(uint8* rom)
} }
/* clear bit 11: set normal mode */ /* clear bit 11: set normal mode */
ENG_RG32(RG32_PFB_CONFIG_0) &= ~0x00000800; ENG_REG32(RG32_PFB_CONFIG_0) &= ~0x00000800;
if (stat == B_OK) if (stat == B_OK)
LOG(8,("INFO: ---RAM test done: access was OK within %d iteration(s).\n", cnt)); LOG(8,("INFO: ---RAM test done: access was OK within %d iteration(s).\n", cnt));
@@ -2334,7 +2334,7 @@ static void detect_panels()
/* dump some panel configuration registers... */ /* dump some panel configuration registers... */
LOG(2,("INFO: Dumping flatpanel registers:\n")); LOG(2,("INFO: Dumping flatpanel registers:\n"));
LOG(2,("DUALHEAD_CTRL: $%08x\n", ENG_RG32(RG32_DUALHEAD_CTRL))); LOG(2,("DUALHEAD_CTRL: $%08x\n", ENG_REG32(RG32_DUALHEAD_CTRL)));
LOG(2,("DAC1: FP_HDISPEND: %d\n", DACR(FP_HDISPEND))); LOG(2,("DAC1: FP_HDISPEND: %d\n", DACR(FP_HDISPEND)));
LOG(2,("DAC1: FP_HTOTAL: %d\n", DACR(FP_HTOTAL))); LOG(2,("DAC1: FP_HTOTAL: %d\n", DACR(FP_HTOTAL)));
LOG(2,("DAC1: FP_HCRTC: %d\n", DACR(FP_HCRTC))); LOG(2,("DAC1: FP_HCRTC: %d\n", DACR(FP_HCRTC)));
@@ -2359,8 +2359,8 @@ static void detect_panels()
LOG(2,("DAC1: FP_DEBUG2: $%08x\n", DACR(FP_DEBUG2))); LOG(2,("DAC1: FP_DEBUG2: $%08x\n", DACR(FP_DEBUG2)));
LOG(2,("DAC1: FP_DEBUG3: $%08x\n", DACR(FP_DEBUG3))); LOG(2,("DAC1: FP_DEBUG3: $%08x\n", DACR(FP_DEBUG3)));
LOG(2,("DAC1: FUNCSEL: $%08x\n", ENG_RG32(RG32_FUNCSEL))); LOG(2,("DAC1: FUNCSEL: $%08x\n", ENG_REG32(RG32_FUNCSEL)));
LOG(2,("DAC1: PANEL_PWR: $%08x\n", ENG_RG32(RG32_PANEL_PWR))); LOG(2,("DAC1: PANEL_PWR: $%08x\n", ENG_REG32(RG32_PANEL_PWR)));
if(si->ps.secondary_head) if(si->ps.secondary_head)
{ {
@@ -2388,8 +2388,8 @@ static void detect_panels()
LOG(2,("DAC2: FP_DEBUG2: $%08x\n", DAC2R(FP_DEBUG2))); LOG(2,("DAC2: FP_DEBUG2: $%08x\n", DAC2R(FP_DEBUG2)));
LOG(2,("DAC2: FP_DEBUG3: $%08x\n", DAC2R(FP_DEBUG3))); LOG(2,("DAC2: FP_DEBUG3: $%08x\n", DAC2R(FP_DEBUG3)));
LOG(2,("DAC2: FUNCSEL: $%08x\n", ENG_RG32(RG32_2FUNCSEL))); LOG(2,("DAC2: FUNCSEL: $%08x\n", ENG_REG32(RG32_2FUNCSEL)));
LOG(2,("DAC2: PANEL_PWR: $%08x\n", ENG_RG32(RG32_2PANEL_PWR))); LOG(2,("DAC2: PANEL_PWR: $%08x\n", ENG_REG32(RG32_2PANEL_PWR)));
} }
LOG(2,("INFO: End flatpanel registers dump.\n")); LOG(2,("INFO: End flatpanel registers dump.\n"));
} }
@@ -2850,7 +2850,7 @@ static void pinsnv30_arch_fake(void)
static void getRAMsize_arch_nv4(void) static void getRAMsize_arch_nv4(void)
{ {
uint32 strapinfo = ENG_RG32(RG32_NV4STRAPINFO); uint32 strapinfo = ENG_REG32(RG32_NV4STRAPINFO);
if (strapinfo & 0x00000100) if (strapinfo & 0x00000100)
{ {
@@ -2883,7 +2883,7 @@ static void getRAMsize_arch_nv4(void)
static void getstrap_arch_nv4(void) static void getstrap_arch_nv4(void)
{ {
uint32 strapinfo = ENG_RG32(RG32_NVSTRAPINFO2); uint32 strapinfo = ENG_REG32(RG32_NVSTRAPINFO2);
/* determine PLL reference crystal frequency */ /* determine PLL reference crystal frequency */
if (strapinfo & 0x00000040) if (strapinfo & 0x00000040)
@@ -2898,7 +2898,7 @@ static void getstrap_arch_nv4(void)
static void getRAMsize_arch_nv10_20_30_40(void) static void getRAMsize_arch_nv10_20_30_40(void)
{ {
uint32 dev_manID = CFGR(DEVID); uint32 dev_manID = CFGR(DEVID);
uint32 strapinfo = ENG_RG32(RG32_NV10STRAPINFO); uint32 strapinfo = ENG_REG32(RG32_NV10STRAPINFO);
switch (dev_manID) switch (dev_manID)
{ {
@@ -2950,7 +2950,7 @@ static void getRAMsize_arch_nv10_20_30_40(void)
static void getstrap_arch_nv10_20_30_40(void) static void getstrap_arch_nv10_20_30_40(void)
{ {
uint32 dev_manID = CFGR(DEVID); uint32 dev_manID = CFGR(DEVID);
uint32 strapinfo = ENG_RG32(RG32_NVSTRAPINFO2); uint32 strapinfo = ENG_REG32(RG32_NVSTRAPINFO2);
/* determine PLL reference crystal frequency: three types are used... */ /* determine PLL reference crystal frequency: three types are used... */
if (strapinfo & 0x00000040) if (strapinfo & 0x00000040)