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radeon_hd: Begin to widdle down DP to common code

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This commit is contained in:
Alexander von Gluck IV
2012-04-02 17:00:24 -05:00
parent 37550d80c9
commit 64dcb00f9f
3 changed files with 36 additions and 107 deletions
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headers/private/graphics/common/dp_raw.h
+12 -10
View File
@@ -70,12 +70,12 @@
// DP Port Capability 0
#define DP_PORT0_CAPABILITY0 0x0008 // Reg
#define DP_PORT1_CAPABILITY0 0x000A // Reg
#define DP_PORTX_CAPABILITY0_EN_EDID_MASK 0x0002 // Bool
#define DP_PORTX_CAPABILITY0_EN_SECOND_MASK 0x0004 // Bool
#define DP_PORT_CAPABILITY0_EN_EDID_MASK 0x0002 // Bool
#define DP_PORT_CAPABILITY0_EN_SECOND_MASK 0x0004 // Bool
// DP Port Capability 1
#define DP_PORT0_CAPABILITY1 0x0009 // Reg
#define DP_PORT1_CAPABILITY1 0x000B // Reg
#define DP_PORT0_CAPABILITY1_BUF_SIZE_MASK 0x00FF // Size
#define DP_PORT_CAPABILITY1_BUF_SIZE_MASK 0x00FF // Size
// (value + 1) * 32 bytes per lane
/* *** DPCD Link Configuration Field (0x0100) *** */
@@ -110,14 +110,16 @@
#define DP_LINK_TRAIN_LANE1 0x0104 // Reg
#define DP_LINK_TRAIN_LANE2 0x0105 // Reg
#define DP_LINK_TRAIN_LANE3 0x0106 // Reg
#define DP_LINK_TRAIN_LANEn_VCCSWING_MASK 0x0003 // Mask
#define DP_LINK_TRAIN_LANEn_MAXSWING_MASK 0x0004 // Mask
#define DP_LINK_TRAIN_LANEn_PREE_MASK 0x0018 // Mask
#define DP_LINK_TRAIN_LANEn_MAXPREE_MASK 0x0020 // Mask
#define DP_LINK_TRAIN_LANE_VCCSWING_SHIFT 0x0000 // Shift
#define DP_LINK_TRAIN_LANE_VCCSWING_MASK 0x0003 // Mask
#define DP_LINK_TRAIN_LANE_MAXSWING_MASK 0x0004 // Mask
#define DP_LINK_TRAIN_LANE_PREE_MASK 0x0018 // Mask
#define DP_LINK_TRAIN_LANE_PREE_SHIFT 0x0003 // Shift
#define DP_LINK_TRAIN_LANE_MAXPREE_MASK 0x0020 // Mask
// DP Down-spread Control (0x0107)
#define DP_DOWNSPREAD_CTL 0x0107 // Reg
#define DP_DOWNSPREAD_CTL_FREQ_MASK 0x0001 // Int
#define DP_DOWNSPREAD_CTL_AMP_MASK 0x0010 // Int
#define DP_DOWNSPREAD_CTRL 0x0107 // Reg
#define DP_DOWNSPREAD_CTRL_FREQ_MASK 0x0001 // Int
#define DP_DOWNSPREAD_CTRL_AMP_EN 0x0010 // Int
// DP Main Link Channel Coding (0x0108)
#define DP_MAIN_CHAN_CODE 0x0108 // Reg
#define DP_MAIN_CHAN_CODE_EN_ANSI_MASK 0x0001 // Bool
headers/private/graphics/radeon_hd/displayport_reg.h
-72
View File
@@ -16,88 +16,23 @@
* place this into graphic private common code
*/
#define AUX_NATIVE_WRITE 0x8
#define AUX_NATIVE_READ 0x9
#define AUX_I2C_WRITE 0x0
#define AUX_I2C_READ 0x1
#define AUX_I2C_STATUS 0x2
#define AUX_I2C_MOT 0x4
#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
#define AUX_I2C_REPLY_ACK (0x0 << 6)
#define AUX_I2C_REPLY_NACK (0x1 << 6)
#define AUX_I2C_REPLY_DEFER (0x2 << 6)
#define AUX_I2C_REPLY_MASK (0x3 << 6)
// ** AUX channel addresses
// * DisplayPort Configuration data
#define DP_DPCD_REV 0x000
#define DP_MAX_LINK_RATE 0x001
#define DP_MAX_LANE_COUNT 0x002
#define DP_MAX_LANE_COUNT_MASK 0x1f
#define DP_TPS3_SUPPORTED (1 << 6)
#define DP_ENHANCED_FRAME_CAP (1 << 7)
#define DP_MAX_DOWNSPREAD 0x003
#define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
#define DP_NORP 0x004
// Down stream DisplayPort status
#define DP_DOWNSTREAMPORT_PRESENT 0x005
# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
// Down stream port types:
// 00 = DisplayPort
// 01 = Analog
// 10 = TMDS or HDMI
// 11 = Other
#define DP_FORMAT_CONVERSION (1 << 3)
#define DP_MAIN_LINK_CHANNEL_CODING 0x006
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
// DisplayPort link configuration
#define DP_LINK_BW_SET 0x100
#define DP_LINK_BW_1_62 0x06
#define DP_LINK_BW_2_7 0x0a
#define DP_LINK_BW_5_4 0x14
#define DP_LANE_COUNT_SET 0x101
#define DP_LANE_COUNT_MASK 0x0f
#define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
// DisplayPort training patern (used for link training)
#define DP_TRAINING_PATTERN_SET 0x102
#define DP_TRAINING_PATTERN_DISABLE 0
#define DP_TRAINING_PATTERN_1 1
#define DP_TRAINING_PATTERN_2 2
#define DP_TRAINING_PATTERN_3 3
#define DP_TRAINING_PATTERN_MASK 0x3
#define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
#define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
#define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
#define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
#define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
#define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
#define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
#define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
#define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
#define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
#define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
#define DP_TRAINING_LANE0_SET 0x103
#define DP_TRAINING_LANE1_SET 0x104
#define DP_TRAINING_LANE2_SET 0x105
#define DP_TRAINING_LANE3_SET 0x106
#define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
#define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
#define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
@@ -112,15 +47,8 @@
#define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
#define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
#define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
#define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
#define DP_DOWNSPREAD_CTRL 0x107
#define DP_SPREAD_AMP_0_5 (1 << 4)
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
#define DP_SET_ANSI_8B10B (1 << 0)
#define DP_LANE0_1_STATUS 0x202
#define DP_LANE2_3_STATUS 0x203
#define DP_LANE_CR_DONE (1 << 0)
src/add-ons/accelerants/radeon_hd/displayport.cpp
+24 -25
View File
@@ -13,6 +13,7 @@
#include "accelerant_protos.h"
#include "connector.h"
#include "dp_raw.h"
#include "mode.h"
@@ -338,12 +339,12 @@ dp_get_link_clock_encode(uint32 dpLinkClock)
{
switch (dpLinkClock) {
case 270000:
return DP_LINK_BW_2_7;
return DP_LINK_RATE_270;
case 540000:
return DP_LINK_BW_5_4;
return DP_LINK_RATE_540;
}
return DP_LINK_BW_1_62;
return DP_LINK_RATE_162;
}
@@ -351,9 +352,9 @@ uint32
dp_get_link_clock_decode(uint32 dpLinkClock)
{
switch (dpLinkClock) {
case DP_LINK_BW_2_7:
case DP_LINK_RATE_270:
return 270000;
case DP_LINK_BW_5_4:
case DP_LINK_RATE_540:
return 540000;
}
return 162000;
@@ -469,7 +470,7 @@ dp_update_vs_emph(dp_info* dp)
ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH);
// Set vs and emph on the sink
dp_aux_write(dp->auxPin, DP_TRAINING_LANE0_SET,
dp_aux_write(dp->auxPin, DP_LINK_TRAIN_LANE0,
dp->trainingSet, dp->laneCount, 0);
}
@@ -482,7 +483,7 @@ dp_get_adjust_request_voltage(dp_info* dp, int lane)
: DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
uint8 l = dp->linkStatus[i - DP_LANE0_1_STATUS];
return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
return ((l >> s) & 0x3) << DP_LINK_TRAIN_LANE_VCCSWING_SHIFT;
}
@@ -494,7 +495,7 @@ dp_get_adjust_request_pre_emphasis(dp_info* dp, int lane)
: DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
uint8 l = dp->linkStatus[i - DP_LANE0_1_STATUS];
return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
return ((l >> s) & 0x3) << DP_LINK_TRAIN_LANE_PREE_SHIFT;
}
@@ -523,8 +524,8 @@ dp_get_adjust_train(dp_info* dp)
uint8 lanePreEmphasis = dp_get_adjust_request_pre_emphasis(dp, lane);
TRACE("%s: Requested %s at %s for lane %d\n", __func__,
preEmphasisNames[lanePreEmphasis >> DP_TRAIN_PRE_EMPHASIS_SHIFT],
voltageNames[laneVoltage >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
preEmphasisNames[lanePreEmphasis >> DP_LINK_TRAIN_LANE_PREE_SHIFT],
voltageNames[laneVoltage >> DP_LINK_TRAIN_LANE_VCCSWING_SHIFT],
lane);
if (laneVoltage > voltage)
@@ -556,13 +557,13 @@ dp_set_tp(dp_info* dp, int trainingPattern)
/* set training pattern on the source */
if (info.dceMajor >= 4 || !dp->trainingUseEncoder) {
switch (trainingPattern) {
case DP_TRAINING_PATTERN_1:
case DP_LINK_TRAIN_PATTERN_1:
rawTrainingPattern = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
break;
case DP_TRAINING_PATTERN_2:
case DP_LINK_TRAIN_PATTERN_2:
rawTrainingPattern = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
break;
case DP_TRAINING_PATTERN_3:
case DP_LINK_TRAIN_PATTERN_3:
rawTrainingPattern = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
break;
}
@@ -587,7 +588,7 @@ dp_set_tp(dp_info* dp, int trainingPattern)
}
// Enable training pattern on the sink
dpcd_reg_write(dp->auxPin, DP_TRAINING_PATTERN_SET, trainingPattern);
dpcd_reg_write(dp->auxPin, DP_LINK_TRAIN, trainingPattern);
}
@@ -602,7 +603,7 @@ dp_link_train_cr(dp_info* dp)
uint8 voltage = 0xff;
int lane;
dp_set_tp(dp, DP_TRAINING_PATTERN_1);
dp_set_tp(dp, DP_LINK_TRAIN_PATTERN_1);
memset(dp->trainingSet, 0, 4);
dp_update_vs_emph(dp);
@@ -654,8 +655,8 @@ dp_link_train_cr(dp_info* dp)
TRACE("%s: clock recovery at voltage %d pre-emphasis %d\n",
__func__, dp->trainingSet[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
(dp->trainingSet[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
>> DP_TRAIN_PRE_EMPHASIS_SHIFT);
(dp->trainingSet[0] & DP_LINK_TRAIN_LANE_PREE_MASK)
>> DP_LINK_TRAIN_LANE_PREE_SHIFT);
return B_OK;
}
@@ -722,7 +723,7 @@ dp_link_train(uint8 crtcID, display_mode* mode)
// Possibly enable downspread on the sink
if ((dp->config[3] & 0x1) != 0)
dpcd_reg_write(hwPin, DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
dpcd_reg_write(hwPin, DP_DOWNSPREAD_CTRL, DP_DOWNSPREAD_CTRL_AMP_EN);
else
dpcd_reg_write(hwPin, DP_DOWNSPREAD_CTRL, 0);
@@ -730,12 +731,12 @@ dp_link_train(uint8 crtcID, display_mode* mode)
ATOM_ENCODER_CMD_SETUP_PANEL_MODE);
if (dp->config[0] >= 0x11)
sandbox |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
dpcd_reg_write(hwPin, DP_LANE_COUNT_SET, sandbox);
sandbox |= DP_ENHANCED_FRAME_EN_MASK;
dpcd_reg_write(hwPin, DP_LANE_COUNT, sandbox);
// Set the link rate on the DP sink
sandbox = dp_get_link_clock_encode(dp->clock);
dpcd_reg_write(hwPin, DP_LINK_BW_SET, sandbox);
dpcd_reg_write(hwPin, DP_LINK_RATE, sandbox);
// Start link training on source
if (info.dceMajor >= 4 || !dp->trainingUseEncoder) {
@@ -747,8 +748,7 @@ dp_link_train(uint8 crtcID, display_mode* mode)
}
// Disable the training pattern on the sink
dpcd_reg_write(hwPin, DP_TRAINING_PATTERN_SET,
DP_TRAINING_PATTERN_DISABLE);
dpcd_reg_write(hwPin, DP_LINK_TRAIN, DP_LINK_TRAIN_PATTERN_DISABLED);
dp_link_train_cr(dp);
// TODO: dp_link_train_ce
@@ -758,8 +758,7 @@ dp_link_train(uint8 crtcID, display_mode* mode)
snooze(400);
// Disable the training pattern on the sink
dpcd_reg_write(hwPin, DP_TRAINING_PATTERN_SET,
DP_TRAINING_PATTERN_DISABLE);
dpcd_reg_write(hwPin, DP_LINK_TRAIN, DP_LINK_TRAIN_PATTERN_DISABLED);
// Disable the training pattern on the source
if (info.dceMajor >= 4 || !dp->trainingUseEncoder) {