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radeon_hd: Begin to widdle down DP to common code

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This commit is contained in:
Alexander von Gluck IV
2012-04-02 17:00:24 -05:00
parent 37550d80c9
commit 64dcb00f9f
3 changed files with 36 additions and 107 deletions
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headers/private/graphics/common/dp_raw.h
+12 -10
View File
@@ -70,12 +70,12 @@
// DP Port Capability 0
#define DP_PORT0_CAPABILITY0 0x0008 // Reg
#define DP_PORT1_CAPABILITY0 0x000A // Reg
#define DP_PORTX_CAPABILITY0_EN_EDID_MASK 0x0002 // Bool
#define DP_PORTX_CAPABILITY0_EN_SECOND_MASK 0x0004 // Bool
#define DP_PORT_CAPABILITY0_EN_EDID_MASK 0x0002 // Bool
#define DP_PORT_CAPABILITY0_EN_SECOND_MASK 0x0004 // Bool
// DP Port Capability 1
#define DP_PORT0_CAPABILITY1 0x0009 // Reg
#define DP_PORT1_CAPABILITY1 0x000B // Reg
#define DP_PORT0_CAPABILITY1_BUF_SIZE_MASK 0x00FF // Size
#define DP_PORT_CAPABILITY1_BUF_SIZE_MASK 0x00FF // Size
// (value + 1) * 32 bytes per lane
/* *** DPCD Link Configuration Field (0x0100) *** */
@@ -110,14 +110,16 @@
#define DP_LINK_TRAIN_LANE1 0x0104 // Reg
#define DP_LINK_TRAIN_LANE2 0x0105 // Reg
#define DP_LINK_TRAIN_LANE3 0x0106 // Reg
#define DP_LINK_TRAIN_LANEn_VCCSWING_MASK 0x0003 // Mask
#define DP_LINK_TRAIN_LANEn_MAXSWING_MASK 0x0004 // Mask
#define DP_LINK_TRAIN_LANEn_PREE_MASK 0x0018 // Mask
#define DP_LINK_TRAIN_LANEn_MAXPREE_MASK 0x0020 // Mask
#define DP_LINK_TRAIN_LANE_VCCSWING_SHIFT 0x0000 // Shift
#define DP_LINK_TRAIN_LANE_VCCSWING_MASK 0x0003 // Mask
#define DP_LINK_TRAIN_LANE_MAXSWING_MASK 0x0004 // Mask
#define DP_LINK_TRAIN_LANE_PREE_MASK 0x0018 // Mask
#define DP_LINK_TRAIN_LANE_PREE_SHIFT 0x0003 // Shift
#define DP_LINK_TRAIN_LANE_MAXPREE_MASK 0x0020 // Mask
// DP Down-spread Control (0x0107)
#define DP_DOWNSPREAD_CTL 0x0107 // Reg
#define DP_DOWNSPREAD_CTL_FREQ_MASK 0x0001 // Int
#define DP_DOWNSPREAD_CTL_AMP_MASK 0x0010 // Int
#define DP_DOWNSPREAD_CTRL 0x0107 // Reg
#define DP_DOWNSPREAD_CTRL_FREQ_MASK 0x0001 // Int
#define DP_DOWNSPREAD_CTRL_AMP_EN 0x0010 // Int
// DP Main Link Channel Coding (0x0108)
#define DP_MAIN_CHAN_CODE 0x0108 // Reg
#define DP_MAIN_CHAN_CODE_EN_ANSI_MASK 0x0001 // Bool
headers/private/graphics/radeon_hd/displayport_reg.h
-72
View File
@@ -16,88 +16,23 @@
* place this into graphic private common code
*/
#define AUX_NATIVE_WRITE 0x8
#define AUX_NATIVE_READ 0x9
#define AUX_I2C_WRITE 0x0
#define AUX_I2C_READ 0x1
#define AUX_I2C_STATUS 0x2
#define AUX_I2C_MOT 0x4
#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
#define AUX_I2C_REPLY_ACK (0x0 << 6)
#define AUX_I2C_REPLY_NACK (0x1 << 6)
#define AUX_I2C_REPLY_DEFER (0x2 << 6)
#define AUX_I2C_REPLY_MASK (0x3 << 6)
// ** AUX channel addresses
// * DisplayPort Configuration data
#define DP_DPCD_REV 0x000
#define DP_MAX_LINK_RATE 0x001
#define DP_MAX_LANE_COUNT 0x002
#define DP_MAX_LANE_COUNT_MASK 0x1f
#define DP_TPS3_SUPPORTED (1 << 6)
#define DP_ENHANCED_FRAME_CAP (1 << 7)
#define DP_MAX_DOWNSPREAD 0x003
#define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
#define DP_NORP 0x004
// Down stream DisplayPort status
#define DP_DOWNSTREAMPORT_PRESENT 0x005
# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
// Down stream port types:
// 00 = DisplayPort
// 01 = Analog
// 10 = TMDS or HDMI
// 11 = Other
#define DP_FORMAT_CONVERSION (1 << 3)
#define DP_MAIN_LINK_CHANNEL_CODING 0x006
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
// DisplayPort link configuration
#define DP_LINK_BW_SET 0x100
#define DP_LINK_BW_1_62 0x06
#define DP_LINK_BW_2_7 0x0a
#define DP_LINK_BW_5_4 0x14
#define DP_LANE_COUNT_SET 0x101
#define DP_LANE_COUNT_MASK 0x0f
#define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
// DisplayPort training patern (used for link training)
#define DP_TRAINING_PATTERN_SET 0x102
#define DP_TRAINING_PATTERN_DISABLE 0
#define DP_TRAINING_PATTERN_1 1
#define DP_TRAINING_PATTERN_2 2
#define DP_TRAINING_PATTERN_3 3
#define DP_TRAINING_PATTERN_MASK 0x3
#define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
#define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
#define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
#define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
#define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
#define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
#define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
#define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
#define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
#define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
#define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
#define DP_TRAINING_LANE0_SET 0x103
#define DP_TRAINING_LANE1_SET 0x104
#define DP_TRAINING_LANE2_SET 0x105
#define DP_TRAINING_LANE3_SET 0x106
#define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
#define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
#define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
@@ -112,15 +47,8 @@
#define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
#define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
#define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
#define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
#define DP_DOWNSPREAD_CTRL 0x107
#define DP_SPREAD_AMP_0_5 (1 << 4)
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
#define DP_SET_ANSI_8B10B (1 << 0)
#define DP_LANE0_1_STATUS 0x202
#define DP_LANE2_3_STATUS 0x203
#define DP_LANE_CR_DONE (1 << 0)