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sdhci: readable dump of capabilities register

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Change-Id: If97b8fbc20f4d064561698d8bf9601d7ed42d083
Reviewed-on: https://review.haiku-os.org/c/haiku/+/9693
Tested-by: Commit checker robot <[email protected]>
Reviewed-by: Adrien Destugues <[email protected]>
This commit is contained in:
PulkoMandy
2025-10-15 06:09:43 +00:00
committed by Adrien Destugues
parent c66bb38463
commit 660f1dc9dd
2 changed files with 53 additions and 3 deletions
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src/add-ons/kernel/busses/mmc/sdhci.cpp
+32 -1
View File
@@ -80,7 +80,38 @@ SdhciBus::SdhciBus(struct registers* registers, uint8_t irq, bool poll)
fRegisters->host_controller_version.specVersion,
fRegisters->host_controller_version.vendorVersion);
TRACE("Capabilities: %" PRIx64 "\n", fRegisters->capabilities.Bits());
TRACE("Capabilities: %s%s%s%s%s%s%s%s%s%s%s%s%s%s\n"
" Clock multiplier: %" PRIx8 "\n"
" Retuning modes: %" PRIx8 "\n"
" Retuning timer count: %" PRIx8 "\n"
" Slot type: %" PRIx8 "\n"
" Supported voltages: %" PRIx8 "\n"
" Max block length: %" PRIx8 "\n"
" Base clock frequency: %" PRId8 " MHz\n"
" Timeout clock: %" PRId8 " %s\n",
fRegisters->capabilities.UseTuningForSDR50() ? "SDR50 needs retuning, " : "",
fRegisters->capabilities.TypeDSupport() ? "Type-D, " : "",
fRegisters->capabilities.TypeCSupport() ? "Type-C, " : "",
fRegisters->capabilities.TypeASupport() ? "Type-A, " : "",
fRegisters->capabilities.DDR50Support() ? "DDR50, " : "",
fRegisters->capabilities.SDR104Support() ? "SDR104, " : "",
fRegisters->capabilities.SDR50Support() ? "SDR50, " : "",
fRegisters->capabilities.AsynchronousInterrupts() ? "Asynchronous interrupts, " : "",
fRegisters->capabilities.SystemBus64Bits() ? "64-bit system bus, " : "",
fRegisters->capabilities.SuspendResume() ? "Suspend/Resume, " : "",
fRegisters->capabilities.SimpleDMA() ? "Simple DMA, " : "",
fRegisters->capabilities.HighSpeed() ? "High speed, " : "",
fRegisters->capabilities.AdvancedDMA() ? "Advanced DMA, " : "",
fRegisters->capabilities.Embedded8Bit() ? "8-bit Embedded mode, " : "",
fRegisters->capabilities.ClockMultiplier(),
fRegisters->capabilities.RetuningModes(),
fRegisters->capabilities.RetuningTimerCount(),
fRegisters->capabilities.SlotType(),
fRegisters->capabilities.SupportedVoltages(),
fRegisters->capabilities.MaxBlockLength(),
fRegisters->capabilities.BaseClockFrequency(),
fRegisters->capabilities.TimeoutClockFrequency(),
fRegisters->capabilities.TimeoutClockUnit() ? "MHz" : "kHz");
TRACE("Initial host control: %x\n", fRegisters->host_control.Bits());
TRACE("Initial host control 2: %x\n", fRegisters->host_control_2);
src/add-ons/kernel/busses/mmc/sdhci.h
+21 -2
View File
@@ -230,10 +230,29 @@ class SoftwareReset {
class Capabilities
{
public:
uint64_t Bits() { return fBits; }
uint8_t ClockMultiplier() { return (fBits >> 48) & 0xFF; }
uint8_t RetuningModes() { return (fBits >> 46) & 3; }
bool UseTuningForSDR50() { return (fBits >> 45) & 1; }
uint8_t RetuningTimerCount() { return (fBits >> 40) & 7; }
bool TypeDSupport() { return (fBits >> 38) & 1; }
bool TypeCSupport() { return (fBits >> 37) & 1; }
bool TypeASupport() { return (fBits >> 36) & 1; }
bool DDR50Support() { return (fBits >> 34) & 1; }
bool SDR104Support() { return (fBits >> 33) & 1; }
bool SDR50Support() { return (fBits >> 32) & 1; }
uint8_t SlotType() { return (fBits >> 30) & 3; }
bool AsynchronousInterrupts() { return (fBits >> 29) & 1; }
bool SystemBus64Bits() { return (fBits >> 28) & 1; }
uint8_t SupportedVoltages() { return (fBits >> 24) & 7; }
bool SuspendResume() { return (fBits >> 23) & 1; }
bool SimpleDMA() { return (fBits >> 22) & 1; }
bool HighSpeed() { return (fBits >> 21) & 1; }
bool AdvancedDMA() { return (fBits >> 19) & 1; }
bool Embedded8Bit() { return (fBits >> 18) & 1; }
uint8_t MaxBlockLength() { return (fBits >> 16) & 3; }
uint8_t BaseClockFrequency() { return (fBits >> 8) & 0xFF; }
uint8_t TimeoutClockUnit() { return (fBits >> 7) & 1; }
uint8_t TimeoutClockFrequency() { return (fBits >> 0) & 0x1F; }
static const uint8_t k3v3 = 1;
static const uint8_t k3v0 = 2;