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* style fix

Browse Source 
* clean up int types
* curly brace cleanup
* move vars away from top of functions
  when possible
* split DDR timings to seperate header to
  avoid warnings on unused items
* quite a few automated changes, please excuse
  things within diff still not fixed / incorrect


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42761 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
2011-09-20 13:39:40 +00:00
parent 6fca1a84fc
commit 6655050606
14 changed files with 1148 additions and 1147 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemCPU.cpp
+3 -3
View File
@@ -33,7 +33,7 @@ BeceemCPU::CPUInit(WIMAX_DEVICE* swmxdevice)
status_t
BeceemCPU::CPURun()
{
unsigned int clockRegister = 0;
uint32 clockRegister = 0;
// Read current clock register contents
if (BizarroReadRegister(CLOCK_RESET_CNTRL_REG_1,
@@ -62,7 +62,7 @@ BeceemCPU::CPURun()
status_t
BeceemCPU::CPUReset()
{
unsigned int value = 0;
uint32 value = 0;
if (fWmxDevice->deviceChipID >= T3LPB) {
BizarroReadRegister(SYS_CFG, sizeof(value), &value);
@@ -114,7 +114,7 @@ BeceemCPU::CPUReset()
}
// TODO : ELSE OLDER CHIP ID's < T3LP see Misc.c:1048
unsigned int uiResetValue = 0;
uint32 uiResetValue = 0;
if (fWmxDevice->CPUFlashBoot) {
// In flash boot mode MIPS state register has reverse polarity.
src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemCPU.h
+8 -8
View File
@@ -24,15 +24,15 @@ public:
status_t CPUReset();
// yuck. These are in a parent class
virtual status_t ReadRegister(unsigned int reg, size_t size,
uint32_t* buffer) { return NULL; };
virtual status_t WriteRegister(unsigned int reg, size_t size,
uint32_t* buffer) { return NULL; };
virtual status_t BizarroReadRegister(unsigned int reg,
size_t size, uint32_t* buffer)
virtual status_t ReadRegister(uint32 reg, size_t size,
uint32* buffer) { return NULL; };
virtual status_t WriteRegister(uint32 reg, size_t size,
uint32* buffer) { return NULL; };
virtual status_t BizarroReadRegister(uint32 reg,
size_t size, uint32* buffer)
{ return NULL; };
virtual status_t BizarroWriteRegister(unsigned int reg,
size_t size, uint32_t* buffer)
virtual status_t BizarroWriteRegister(uint32 reg,
size_t size, uint32* buffer)
{ return NULL; };
private:
src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemDDR.cpp
+26 -25
View File
@@ -10,6 +10,7 @@
#include "BeceemDDR.h"
#include "BeceemDDRTiming.h"
#include "Settings.h"
@@ -25,21 +26,21 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
fWmxDevice = swmxdevice;
PDDR_SETTING psDDRSetting = NULL;
unsigned int chipID = fWmxDevice->deviceChipID;
uint32 chipID = fWmxDevice->deviceChipID;
unsigned long registerCount = 0;
unsigned long value = 0;
unsigned int uiResetValue = 0;
unsigned int uiClockSetting = 0;
uint32 uiResetValue = 0;
uint32 uiClockSetting = 0;
int retval = B_OK;
// Grab the Config6 metric from the vendor config and convert endianness
unsigned int vendorConfig6raw = fWmxDevice->vendorcfg.HostDrvrConfig6;
uint32 vendorConfig6raw = fWmxDevice->vendorcfg.HostDrvrConfig6;
vendorConfig6raw &= ~(htonl(1 << 15));
unsigned int vendorConfig6 = ntohl(vendorConfig6raw);
uint32 vendorConfig6 = ntohl(vendorConfig6raw);
// Read our vendor provided Config6 metric and populate memory settings
unsigned int vendorDDRSetting = (ntohl(vendorConfig6raw) >> 8) & 0x0F;
uint32 vendorDDRSetting = (ntohl(vendorConfig6raw) >> 8) & 0x0F;
bool vendorPmuMode = (vendorConfig6 >> 24) & 0x03;
bool vendorMipsConfig = (vendorConfig6 >> 20) & 0x01;
bool vendorPLLConfig = (vendorConfig6 >> 19) & 0x01;
@@ -84,7 +85,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
if ((chipID != BCS220_2)
&& (chipID != BCS220_2BC)
&& (chipID != BCS220_3)) {
retval = BizarroReadRegister((unsigned int)0x0f000830,
retval = BizarroReadRegister((uint32)0x0f000830,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
@@ -93,7 +94,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
return retval;
}
uiResetValue |= 0x44;
retval = BizarroWriteRegister((unsigned int)0x0f000830,
retval = BizarroWriteRegister((uint32)0x0f000830,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
@@ -227,7 +228,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
value = psDDRSetting->ulRegValue;
retval = BizarroWriteRegister(psDDRSetting->ulRegAddress,
sizeof(value), (unsigned int*)&value);
sizeof(value), (uint32*)&value);
if (B_OK != retval) {
TRACE_ALWAYS(
@@ -248,7 +249,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
&& (chipID != BCS220_3)) {
/* drive MDDR to half in case of UMA-B: */
uiResetValue = 0x01010001;
retval = BizarroWriteRegister((unsigned int)0x0F007018,
retval = BizarroWriteRegister((uint32)0x0F007018,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
@@ -257,7 +258,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
return retval;
}
uiResetValue = 0x00040020;
retval = BizarroWriteRegister((unsigned int)0x0F007094,
retval = BizarroWriteRegister((uint32)0x0F007094,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
@@ -266,7 +267,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
return retval;
}
uiResetValue = 0x01020101;
retval = BizarroWriteRegister((unsigned int)0x0F00701c,
retval = BizarroWriteRegister((uint32)0x0F00701c,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
@@ -275,7 +276,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
return retval;
}
uiResetValue = 0x01010000;
retval = BizarroWriteRegister((unsigned int)0x0F007018,
retval = BizarroWriteRegister((uint32)0x0F007018,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
@@ -295,7 +296,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
*/
if (vendorPmuMode == HYBRID_MODE_7C) {
TRACE("Debug: Hybrid Power Mode 7C\n");
retval = BizarroReadRegister((unsigned int)0x0f000c00,
retval = BizarroReadRegister((uint32)0x0f000c00,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
@@ -303,7 +304,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
__FUNCTION__, __LINE__);
return retval;
}
retval = BizarroReadRegister((unsigned int)0x0f000c00,
retval = BizarroReadRegister((uint32)0x0f000c00,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
@@ -311,21 +312,21 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
return retval;
}
uiResetValue = 0x1322a8;
retval = BizarroWriteRegister((unsigned int)0x0f000d1c,
retval = BizarroWriteRegister((uint32)0x0f000d1c,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
}
retval = BizarroReadRegister((unsigned int)0x0f000c00,
retval = BizarroReadRegister((uint32)0x0f000c00,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
}
retval = BizarroReadRegister((unsigned int)0x0f000c00,
retval = BizarroReadRegister((uint32)0x0f000c00,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
@@ -333,7 +334,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
return retval;
}
uiResetValue = 0x132296;
retval = BizarroWriteRegister((unsigned int)0x0f000d14,
retval = BizarroWriteRegister((uint32)0x0f000d14,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
@@ -343,14 +344,14 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
} else if (vendorPmuMode == HYBRID_MODE_6) {
TRACE("Debug: Hybrid Power Mode 6\n");
retval = BizarroReadRegister((unsigned int)0x0f000c00,
retval = BizarroReadRegister((uint32)0x0f000c00,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
}
retval = BizarroReadRegister((unsigned int)0x0f000c00,
retval = BizarroReadRegister((uint32)0x0f000c00,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
@@ -358,21 +359,21 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
return retval;
}
uiResetValue = 0x6003229a;
retval = BizarroWriteRegister((unsigned int)0x0f000d14,
retval = BizarroWriteRegister((uint32)0x0f000d14,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
}
retval = BizarroReadRegister((unsigned int)0x0f000c00,
retval = BizarroReadRegister((uint32)0x0f000c00,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
__FUNCTION__, __LINE__);
return retval;
}
retval = BizarroReadRegister((unsigned int)0x0f000c00,
retval = BizarroReadRegister((uint32)0x0f000c00,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroReadRegister failed\n",
@@ -380,7 +381,7 @@ BeceemDDR::DDRInit(WIMAX_DEVICE* swmxdevice)
return retval;
}
uiResetValue = 0x1322a8;
retval = BizarroWriteRegister((unsigned int)0x0f000d1c,
retval = BizarroWriteRegister((uint32)0x0f000d1c,
sizeof(uiResetValue), &uiResetValue);
if (retval < 0) {
TRACE_ALWAYS("%s:%d BizarroWriteRegister failed\n",
src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemDDR.h
+12 -845
View File
@@ -1,9 +1,7 @@
/*
* Beceem WiMax USB Driver.
* Copyright (c) 2010 Alexander von Gluck <[email protected]>
* Distributed under the terms of the GNU General Public License.
*
* Based on GPL code developed by: Beceem Communications Pvt. Ltd
* Beceem WiMax USB Driver.
* Copyright (c) 2010 Alexander von Gluck <[email protected]>
* Distributed under the terms of the MIT license.
*
* Description: Wrangle Beceem volatile DDR memory.
*/
@@ -15,24 +13,6 @@
#include "DeviceStruct.h"
#define DDR_DUMP_INTERNAL_DEVICE_MEMORY 0xBFC02B00
#define MIPS_CLOCK_REG 0x0f000820
#define MIPS_200_MHZ 0
#define MIPS_160_MHZ 1
#define PLL_800_MHZ 0
#define PLL_266_MHZ 1
#define DDR_80_MHZ 0
#define DDR_100_MHZ 1
#define DDR_120_MHZ 2 // Additional Frequency for T3LP
#define DDR_133_MHZ 3
#define DDR_140_MHZ 4 // Not Used (Reserved for future)
#define DDR_160_MHZ 5 // Additional Frequency for T3LP
#define DDR_180_MHZ 6 // Not Used (Reserved for future)
#define DDR_200_MHZ 7 // Not Used (Reserved for future)
class BeceemDDR {
public:
BeceemDDR();
@@ -41,831 +21,18 @@ public:
WIMAX_DEVICE* fWmxDevice;
// yuck. These are in a child class class
virtual status_t ReadRegister(unsigned int reg, size_t size,
uint32_t* buffer) { return NULL; };
virtual status_t WriteRegister(unsigned int reg, size_t size,
uint32_t* buffer) { return NULL; };
virtual status_t BizarroReadRegister(unsigned int reg,
size_t size, uint32_t* buffer)
virtual status_t ReadRegister(uint32 reg, size_t size,
uint32* buffer) { return NULL; };
virtual status_t WriteRegister(uint32 reg, size_t size,
uint32* buffer) { return NULL; };
virtual status_t BizarroReadRegister(uint32 reg,
size_t size, uint32* buffer)
{ return NULL; };
virtual status_t BizarroWriteRegister(unsigned int reg,
size_t size, uint32_t* buffer)
virtual status_t BizarroWriteRegister(uint32 reg,
size_t size, uint32* buffer)
{ return NULL; };
};
/*
* DDR Power modes
*/
typedef enum ePMU_MODES
{
HYBRID_MODE_7C = 0,
INTERNAL_MODE_6 = 1,
HYBRID_MODE_6 = 2
}PMU_MODE;
/*
* DDR Init maps, taken from Beceem GPL Linux Driver
*/
typedef struct _DDR_SETTING
{
unsigned long ulRegAddress;
unsigned long ulRegValue;
} DDR_SETTING, *PDDR_SETTING;
typedef DDR_SETTING DDR_SET_NODE, *PDDR_SET_NODE;
// DDR INIT 133Mhz
#define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12 // index for 0x0F007000
static DDR_SET_NODE asT3_DDRSetting133MHz[]= {// DPLL Clock Setting
{0x0F000800, 0x00007212},
{0x0f000820, 0x07F13FFF},
{0x0f000810, 0x00000F95},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
// Changed source for Xbar and MIPS clock to APLL
{0x0f000840, 0x0FFF1B00},
{0x0f000870, 0x00000002},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00a04C, 0x0000000C},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020001}, // POP - 0x00020001 Normal 0x01020001
{0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x02000007},
{0x0F007028, 0x02020202},
{0x0F00702c, 0x0206060a}, // ROB - 0x0205050a, 0x0206060a
{0x0F007030, 0x05000000},
{0x0F007034, 0x00000003},
{0x0F007038, 0x110a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C, 0x02101010}, // ROB - 0x02101010, 0x02101018},
{0x0F007040, 0x45751200}, // ROB - 0x45751200, 0x450f1200},
{0x0F007044, 0x110a0d00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x081b0306},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0000001c},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x0010246c},
{0x0F007064, 0x00000010},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00007000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
// # Enable BW improvement within memory controller
{0x0F007094, 0x00000104},
// # Enable 2 ports within Xbar
{0x0F00A000, 0x00000016},
// # Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
// 80Mhz
#define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10 // index for 0x0F007000
static DDR_SET_NODE asT3_DDRSetting80MHz[]= {// DPLL Clock Setting
{0x0f000810, 0x00000F95},
{0x0f000820, 0x07f1ffff},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00a000, 0x00000016},
{0x0F00a04C, 0x0000000C},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01000000},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020000},
{0x0F007020, 0x04020107},
{0x0F007024, 0x00000007},
{0x0F007028, 0x02020201},
{0x0F00702c, 0x0204040a},
{0x0F007030, 0x04000000},
{0x0F007034, 0x00000002},
{0x0F007038, 0x1F060200},
{0x0F00703C, 0x1C22221F},
{0x0F007040, 0x8A006600},
{0x0F007044, 0x221a0800},
{0x0F007048, 0x02690204},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0000001c},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x000A15D6},
{0x0F007064, 0x0000000A},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00004000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
{0x0F007094, 0x00000104},
// Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
// 100Mhz
#define T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 13 // index for 0x0F007000
static DDR_SET_NODE asT3_DDRSetting100MHz[]= {// DPLL Clock Setting
{0x0F000800, 0x00007008},
{0x0f000810, 0x00000F95},
{0x0f000820, 0x07F13E3F},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
// Changed source for Xbar and MIPS clock to APLL
// 0x0f000840, 0x0FFF1800,
{0x0f000840, 0x0FFF1B00},
{0x0f000870, 0x00000002},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00a04C, 0x0000000C},
// Enable 2 ports within Xbar
{0x0F00A000, 0x00000016},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020001}, // POP - 0x00020000 Normal 0x01020000
{0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x00000007},
{0x0F007028, 0x01020201},
{0x0F00702c, 0x0204040A},
{0x0F007030, 0x06000000},
{0x0F007034, 0x00000004},
{0x0F007038, 0x20080200},
{0x0F00703C, 0x02030320},
{0x0F007040, 0x6E7F1200},
{0x0F007044, 0x01190A00},
{0x0F007048, 0x06120305}, // 0x02690204 // 0x06120305
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0000001C},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x00082ED6},
{0x0F007064, 0x0000000A},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00005000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
// Enable BW improvement within memory controller
{0x0F007094, 0x00000104},
// Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
// Net T3B DDR Settings
// DDR INIT 133Mhz
static DDR_SET_NODE asDPLL_266MHZ[] = {
{0x0F000800, 0x00007212},
{0x0f000820, 0x07F13FFF},
{0x0f000810, 0x00000F95},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
// Changed source for X - bar and MIPS clock to APLL
{0x0f000840, 0x0FFF1B00},
{0x0f000870, 0x00000002}
};
#if 0
static DDR_SET_NODE asDPLL_800MHZ[] = {
{0x0f000810, 0x00000F95},
{0x0f000810, 0x00000F95},
{0x0f000810, 0x00000F95},
{0x0f000820, 0x03F1365B},
{0x0f000840, 0x0FFF0000},
{0x0f000880, 0x000003DD},
{0x0f000860, 0x00000000}
};
#endif
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 11 // index for 0x0F007000
static DDR_SET_NODE asT3B_DDRSetting133MHz[] = {// DPLL Clock Setting
{0x0f000810, 0x00000F95},
{0x0f000810, 0x00000F95},
{0x0f000810, 0x00000F95},
{0x0f000820, 0x07F13652},
{0x0f000840, 0x0FFF0800},
// Changed source for Xbar and MIPS clock to APLL
{0x0f000880, 0x000003DD},
{0x0f000860, 0x00000000},
// Changed source for Xbar and MIPS clock to APLL
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
// Enable 2 ports within Xbar
{0x0F00A000, 0x00000016},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020001}, // POP - 0x00020001 Normal 0x01020001
{0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x02000007},
{0x0F007028, 0x02020202},
{0x0F00702c, 0x0206060a}, // ROB- 0x0205050a, 0x0206060a
{0x0F007030, 0x05000000},
{0x0F007034, 0x00000003},
{0x0F007038, 0x130a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C, 0x02101012}, // ROB - 0x02101010, 0x02101018},
{0x0F007040, 0x457D1200}, // ROB - 0x45751200, 0x450f1200},
{0x0F007044, 0x11130d00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x040D0306},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0000001c},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x0010246c},
{0x0F007064, 0x00000012},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00007000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
// # Enable BW improvement within memory controller
{0x0F007094, 0x00000104},
// # Enable start bit within memory controller
{0x0F007018, 0x01010000},
};
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 // index for 0x0F007000
static DDR_SET_NODE asT3B_DDRSetting80MHz[] = {// DPLL Clock Setting
{0x0f000810, 0x00000F95},
{0x0f000820, 0x07F13FFF},
{0x0f000840, 0x0FFF1F00},
{0x0f000880, 0x000003DD},
{0x0f000860, 0x00000000},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00a000, 0x00000016},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01000000},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020000},
{0x0F007020, 0x04020107},
{0x0F007024, 0x00000007},
{0x0F007028, 0x02020201},
{0x0F00702c, 0x0204040a},
{0x0F007030, 0x04000000},
{0x0F007034, 0x02000002},
{0x0F007038, 0x1F060202},
{0x0F00703C, 0x1C22221F},
{0x0F007040, 0x8A006600},
{0x0F007044, 0x221a0800},
{0x0F007048, 0x02690204},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x000A15D6},
{0x0F007064, 0x0000000A},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00004000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
{0x0F007094, 0x00000104},
// Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
// 100Mhz
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 9 // index for 0x0F007000
static DDR_SET_NODE asT3B_DDRSetting100MHz[] = {// DPLL Clock Setting
{0x0f000810, 0x00000F95},
{0x0f000820, 0x07F1369B},
{0x0f000840, 0x0FFF0800},
{0x0f000880, 0x000003DD},
{0x0f000860, 0x00000000},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
// Enable 2 ports within Xbar
{0x0F00A000, 0x00000016},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020000}, // POP - 0x00020000 Normal 0x01020000
{0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x00000007},
{0x0F007028, 0x01020201},
{0x0F00702c, 0x0204040A},
{0x0F007030, 0x06000000},
{0x0F007034, 0x02000004},
{0x0F007038, 0x20080200},
{0x0F00703C, 0x02030320},
{0x0F007040, 0x6E7F1200},
{0x0F007044, 0x01190A00},
{0x0F007048, 0x06120305}, // 0x02690204 // 0x06120305
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001C},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x00082ED6},
{0x0F007064, 0x0000000A},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00005000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
// # Enable BW improvement within memory controller
{0x0F007094, 0x00000104},
// # Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 9 // index for 0x0F007000
static DDR_SET_NODE asT3LP_DDRSetting133MHz[] = {// DPLL Clock Setting
{0x0f000820, 0x03F1365B},
{0x0f000810, 0x00002F95},
{0x0f000880, 0x000003DD},
// Changed source for Xbar and MIPS clock to APLL
{0x0f000840, 0x0FFF0000},
{0x0f000860, 0x00000000},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00A000, 0x00000016},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020001}, // POP - 0x00020001 Normal 0x01020001
{0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x02000007},
{0x0F007028, 0x02020200},
{0x0F00702c, 0x0206060a}, // ROB - 0x0205050a, 0x0206060a
{0x0F007030, 0x05000000},
{0x0F007034, 0x00000003},
{0x0F007038, 0x200a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C, 0x02101020}, // ROB - 0x02101010, 0x02101018,
{0x0F007040, 0x45711200}, // ROB - 0x45751200, 0x450f1200,
{0x0F007044, 0x110D0D00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x04080306},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x0010245F},
{0x0F007064, 0x00000010},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00007000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
{0x0F007088, 0x01000001},
{0x0F00708c, 0x00000101},
{0x0F007090, 0x00000000},
// Enable BW improvement within memory controller
{0x0F007094, 0x00040000},
{0x0F007098, 0x00000000},
{0x0F0070c8, 0x00000104},
// Enable 2 ports within Xbar
// Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 11 // index for 0x0F007000
static DDR_SET_NODE asT3LP_DDRSetting100MHz[]= {// # DPLL Clock Setting
{0x0f000810, 0x00002F95},
{0x0f000820, 0x03F1369B},
{0x0f000840, 0x0fff0000},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
// Changed source for Xbar and MIPS clock to APLL
{0x0f000840, 0x0FFF0000},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020000}, // POP - 0x00020001 Normal 0x01020001
{0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x00000007},
{0x0F007028, 0x01020200},
{0x0F00702c, 0x0204040a}, // ROB- 0x0205050a, 0x0206060a
{0x0F007030, 0x06000000},
{0x0F007034, 0x00000004},
{0x0F007038, 0x1F080200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C, 0x0203031F}, // ROB - 0x02101010, 0x02101018,
{0x0F007040, 0x6e001200}, // ROB - 0x45751200, 0x450f1200,
{0x0F007044, 0x011a0a00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x03000305},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x00082ED6},
{0x0F007064, 0x0000000A},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00005000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
{0x0F007088, 0x01000001},
{0x0F00708c, 0x00000101},
{0x0F007090, 0x00000000},
{0x0F007094, 0x00010000},
{0x0F007098, 0x00000000},
{0x0F0070C8, 0x00000104},
// Enable 2 ports within Xbar
{0x0F00A000, 0x00000016},
// Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 // index for 0x0F007000
static DDR_SET_NODE asT3LP_DDRSetting80MHz[]= {// # DPLL Clock Setting
{0x0f000820, 0x07F13FFF},
{0x0f000810, 0x00002F95},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
{0x0f000840, 0x0FFF1F00},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00A000, 0x00000016},
{0x0f007000, 0x00010001},
{0x0f007004, 0x01000000},
{0x0f007008, 0x01000001},
{0x0f00700c, 0x00000000},
{0x0f007010, 0x01000000},
{0x0f007014, 0x01000100},
{0x0f007018, 0x01000000},
{0x0f00701c, 0x01020000},
{0x0f007020, 0x04020107},
{0x0f007024, 0x00000007},
{0x0f007028, 0x02020200},
{0x0f00702c, 0x0204040a},
{0x0f007030, 0x04000000},
{0x0f007034, 0x00000002},
{0x0f007038, 0x1d060200},
{0x0f00703c, 0x1c22221d},
{0x0f007040, 0x8A116600},
{0x0f007044, 0x222d0800},
{0x0f007048, 0x02690204},
{0x0f00704c, 0x00000000},
{0x0f007050, 0x0100001c},
{0x0f007054, 0x00000000},
{0x0f007058, 0x00000000},
{0x0f00705c, 0x00000000},
{0x0f007060, 0x000A15D6},
{0x0f007064, 0x0000000A},
{0x0f007068, 0x00000000},
{0x0f00706c, 0x00000001},
{0x0f007070, 0x00004000},
{0x0f007074, 0x00000000},
{0x0f007078, 0x00000000},
{0x0f00707c, 0x00000000},
{0x0f007080, 0x00000000},
{0x0f007084, 0x00000000},
{0x0f007088, 0x01000001},
{0x0f00708c, 0x00000101},
{0x0f007090, 0x00000000},
{0x0f007094, 0x00010000},
{0x0f007098, 0x00000000},
{0x0F0070C8, 0x00000104},
{0x0F007018, 0x01010000}
};
// T3 LP-B (UMA-B)
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ 7 // index for 0x0F007000
static DDR_SET_NODE asT3LPB_DDRSetting160MHz[]= {// # DPLL Clock Setting
{0x0f000820, 0x03F137DB},
{0x0f000810, 0x01842795},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
{0x0f000840, 0x0FFF0400},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to 20 MHz
{0x0F00a084, 0x1Cffffff}, // Now dump from her in internal memory
{0x0F00a080, 0x1C000000},
{0x0F00A000, 0x00000016},
{0x0f007000, 0x00010001},
{0x0f007004, 0x01000001},
{0x0f007008, 0x01000101},
{0x0f00700c, 0x00000000},
{0x0f007010, 0x01000100},
{0x0f007014, 0x01000100},
{0x0f007018, 0x01000000},
{0x0f00701c, 0x01020000},
{0x0f007020, 0x04030107},
{0x0f007024, 0x02000007},
{0x0f007028, 0x02020200},
{0x0f00702c, 0x0206060a},
{0x0f007030, 0x050d0d00},
{0x0f007034, 0x00000003},
{0x0f007038, 0x170a0200},
{0x0f00703c, 0x02101012},
{0x0f007040, 0x45161200},
{0x0f007044, 0x11250c00},
{0x0f007048, 0x04da0307},
{0x0f00704c, 0x00000000},
{0x0f007050, 0x0000001c},
{0x0f007054, 0x00000000},
{0x0f007058, 0x00000000},
{0x0f00705c, 0x00000000},
{0x0f007060, 0x00142bb6},
{0x0f007064, 0x20430014},
{0x0f007068, 0x00000000},
{0x0f00706c, 0x00000001},
{0x0f007070, 0x00009000},
{0x0f007074, 0x00000000},
{0x0f007078, 0x00000000},
{0x0f00707c, 0x00000000},
{0x0f007080, 0x00000000},
{0x0f007084, 0x00000000},
{0x0f007088, 0x01000001},
{0x0f00708c, 0x00000101},
{0x0f007090, 0x00000000},
{0x0f007094, 0x00040000},
{0x0f007098, 0x00000000},
{0x0F0070C8, 0x00000104},
{0x0F007018, 0x01010000}
};
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 7 // index for 0x0F007000
static DDR_SET_NODE asT3LPB_DDRSetting133MHz[]= {// # DPLL Clock Setting
{0x0f000820, 0x03F1365B},
{0x0f000810, 0x00002F95},
{0x0f000880, 0x000003DD},
// Changed source for Xbar and MIPS clock to APLL
{0x0f000840, 0x0FFF0000},
{0x0f000860, 0x00000000},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to 20 MHz
{0x0F00a084, 0x1Cffffff}, // dump from here in internal memory
{0x0F00a080, 0x1C000000},
{0x0F00A000, 0x00000016},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020001}, // POP - 0x00020001 Normal 0x01020001
{0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x02000007},
{0x0F007028, 0x02020200},
{0x0F00702c, 0x0206060a}, // ROB- 0x0205050a, 0x0206060a
{0x0F007030, 0x05000000},
{0x0F007034, 0x00000003},
{0x0F007038, 0x190a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C, 0x02101017}, // ROB - 0x02101010, 0x02101018,
{0x0F007040, 0x45171200}, // ROB - 0x45751200, 0x450f1200,
{0x0F007044, 0x11290D00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x04080306},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x0010245F},
{0x0F007064, 0x00000010},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00007000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
{0x0F007088, 0x01000001},
{0x0F00708c, 0x00000101},
{0x0F007090, 0x00000000},
// Enable BW improvement within memory controller
{0x0F007094, 0x00040000},
{0x0F007098, 0x00000000},
{0x0F0070c8, 0x00000104},
// Enable 2 ports within Xbar
// Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 8 // index for 0x0F007000
static DDR_SET_NODE asT3LPB_DDRSetting100MHz[]= {// # DPLL Clock Setting
{0x0f000810, 0x00002F95},
{0x0f000820, 0x03F1369B},
{0x0f000840, 0x0fff0000},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
// Changed source for Xbar and MIPS clock to APLL
{0x0f000840, 0x0FFF0000},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to 20 MHz
{0x0F00a084, 0x1Cffffff}, // dump from here in internal memory
{0x0F00a080, 0x1C000000},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020000}, // POP - 0x00020001 Normal 0x01020001
{0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x00000007},
{0x0F007028, 0x01020200},
{0x0F00702c, 0x0204040a}, // ROB- 0x0205050a, 0x0206060a
{0x0F007030, 0x06000000},
{0x0F007034, 0x00000004},
{0x0F007038, 0x1F080200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C, 0x0203031F}, // ROB - 0x02101010, 0x02101018,
{0x0F007040, 0x6e001200}, // ROB - 0x45751200, 0x450f1200,
{0x0F007044, 0x011a0a00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x03000305},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x00082ED6},
{0x0F007064, 0x0000000A},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00005000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
{0x0F007088, 0x01000001},
{0x0F00708c, 0x00000101},
{0x0F007090, 0x00000000},
{0x0F007094, 0x00010000},
{0x0F007098, 0x00000000},
{0x0F0070C8, 0x00000104},
// # Enable 2 ports within Xbar
{0x0F00A000, 0x00000016},
// # Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 7 // index for 0x0F007000
static DDR_SET_NODE asT3LPB_DDRSetting80MHz[]= {// DPLL Clock Setting
{0x0f000820, 0x07F13FFF},
{0x0f000810, 0x00002F95},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
{0x0f000840, 0x0FFF1F00},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to 20 MHz
{0x0F00a084, 0x1Cffffff}, // dump from here in internal memory
{0x0F00a080, 0x1C000000},
{0x0F00A000, 0x00000016},
{0x0f007000, 0x00010001},
{0x0f007004, 0x01000000},
{0x0f007008, 0x01000001},
{0x0f00700c, 0x00000000},
{0x0f007010, 0x01000000},
{0x0f007014, 0x01000100},
{0x0f007018, 0x01000000},
{0x0f00701c, 0x01020000},
{0x0f007020, 0x04020107},
{0x0f007024, 0x00000007},
{0x0f007028, 0x02020200},
{0x0f00702c, 0x0204040a},
{0x0f007030, 0x04000000},
{0x0f007034, 0x00000002},
{0x0f007038, 0x1d060200},
{0x0f00703c, 0x1c22221d},
{0x0f007040, 0x8A116600},
{0x0f007044, 0x222d0800},
{0x0f007048, 0x02690204},
{0x0f00704c, 0x00000000},
{0x0f007050, 0x0100001c},
{0x0f007054, 0x00000000},
{0x0f007058, 0x00000000},
{0x0f00705c, 0x00000000},
{0x0f007060, 0x000A15D6},
{0x0f007064, 0x0000000A},
{0x0f007068, 0x00000000},
{0x0f00706c, 0x00000001},
{0x0f007070, 0x00004000},
{0x0f007074, 0x00000000},
{0x0f007078, 0x00000000},
{0x0f00707c, 0x00000000},
{0x0f007080, 0x00000000},
{0x0f007084, 0x00000000},
{0x0f007088, 0x01000001},
{0x0f00708c, 0x00000101},
{0x0f007090, 0x00000000},
{0x0f007094, 0x00010000},
{0x0f007098, 0x00000000},
{0x0F0070C8, 0x00000104},
{0x0F007018, 0x01010000}
};
#endif // _USB_BECEEM_DDR_H_
#endif /* _USB_BECEEM_DDR_H_ */
src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemDDRTiming.h
+849
View File
@@ -0,0 +1,849 @@
/*
* Beceem WiMax USB Driver.
* Copyright (c) 2010 Alexander von Gluck <[email protected]>
* Distributed under the terms of the GNU General Public License.
*
* Based on GPL code developed by: Beceem Communications Pvt. Ltd
*
* Description: Beceem DDR memory timings
*/
#ifndef _USB_BECEEM_DDR_TIMING_H_
#define _USB_BECEEM_DDR_TIMING_H_
#include <ByteOrder.h>
#include "DeviceStruct.h"
#define DDR_DUMP_INTERNAL_DEVICE_MEMORY 0xBFC02B00
#define MIPS_CLOCK_REG 0x0f000820
#define MIPS_200_MHZ 0
#define MIPS_160_MHZ 1
#define PLL_800_MHZ 0
#define PLL_266_MHZ 1
#define DDR_80_MHZ 0
#define DDR_100_MHZ 1
#define DDR_120_MHZ 2 // Additional Frequency for T3LP
#define DDR_133_MHZ 3
#define DDR_140_MHZ 4 // Not Used (Reserved for future)
#define DDR_160_MHZ 5 // Additional Frequency for T3LP
#define DDR_180_MHZ 6 // Not Used (Reserved for future)
#define DDR_200_MHZ 7 // Not Used (Reserved for future)
/*
* DDR Power modes
*/
typedef enum ePMU_MODES
{
HYBRID_MODE_7C = 0,
INTERNAL_MODE_6 = 1,
HYBRID_MODE_6 = 2
}PMU_MODE;
/*
* DDR Init maps, taken from Beceem GPL Linux Driver
*/
typedef struct _DDR_SETTING
{
unsigned long ulRegAddress;
unsigned long ulRegValue;
} DDR_SETTING, *PDDR_SETTING;
typedef DDR_SETTING DDR_SET_NODE, *PDDR_SET_NODE;
// DDR INIT 133Mhz
#define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12 // index for 0x0F007000
static DDR_SET_NODE asT3_DDRSetting133MHz[]= {// DPLL Clock Setting
{0x0F000800, 0x00007212},
{0x0f000820, 0x07F13FFF},
{0x0f000810, 0x00000F95},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
// Changed source for Xbar and MIPS clock to APLL
{0x0f000840, 0x0FFF1B00},
{0x0f000870, 0x00000002},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00a04C, 0x0000000C},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020001}, // POP - 0x00020001 Normal 0x01020001
{0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x02000007},
{0x0F007028, 0x02020202},
{0x0F00702c, 0x0206060a}, // ROB - 0x0205050a, 0x0206060a
{0x0F007030, 0x05000000},
{0x0F007034, 0x00000003},
{0x0F007038, 0x110a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C, 0x02101010}, // ROB - 0x02101010, 0x02101018},
{0x0F007040, 0x45751200}, // ROB - 0x45751200, 0x450f1200},
{0x0F007044, 0x110a0d00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x081b0306},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0000001c},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x0010246c},
{0x0F007064, 0x00000010},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00007000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
// # Enable BW improvement within memory controller
{0x0F007094, 0x00000104},
// # Enable 2 ports within Xbar
{0x0F00A000, 0x00000016},
// # Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
// 80Mhz
#define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10 // index for 0x0F007000
static DDR_SET_NODE asT3_DDRSetting80MHz[]= {// DPLL Clock Setting
{0x0f000810, 0x00000F95},
{0x0f000820, 0x07f1ffff},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00a000, 0x00000016},
{0x0F00a04C, 0x0000000C},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01000000},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020000},
{0x0F007020, 0x04020107},
{0x0F007024, 0x00000007},
{0x0F007028, 0x02020201},
{0x0F00702c, 0x0204040a},
{0x0F007030, 0x04000000},
{0x0F007034, 0x00000002},
{0x0F007038, 0x1F060200},
{0x0F00703C, 0x1C22221F},
{0x0F007040, 0x8A006600},
{0x0F007044, 0x221a0800},
{0x0F007048, 0x02690204},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0000001c},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x000A15D6},
{0x0F007064, 0x0000000A},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00004000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
{0x0F007094, 0x00000104},
// Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
// 100Mhz
#define T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 13 // index for 0x0F007000
static DDR_SET_NODE asT3_DDRSetting100MHz[]= {// DPLL Clock Setting
{0x0F000800, 0x00007008},
{0x0f000810, 0x00000F95},
{0x0f000820, 0x07F13E3F},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
// Changed source for Xbar and MIPS clock to APLL
// 0x0f000840, 0x0FFF1800,
{0x0f000840, 0x0FFF1B00},
{0x0f000870, 0x00000002},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00a04C, 0x0000000C},
// Enable 2 ports within Xbar
{0x0F00A000, 0x00000016},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020001}, // POP - 0x00020000 Normal 0x01020000
{0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x00000007},
{0x0F007028, 0x01020201},
{0x0F00702c, 0x0204040A},
{0x0F007030, 0x06000000},
{0x0F007034, 0x00000004},
{0x0F007038, 0x20080200},
{0x0F00703C, 0x02030320},
{0x0F007040, 0x6E7F1200},
{0x0F007044, 0x01190A00},
{0x0F007048, 0x06120305}, // 0x02690204 // 0x06120305
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0000001C},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x00082ED6},
{0x0F007064, 0x0000000A},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00005000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
// Enable BW improvement within memory controller
{0x0F007094, 0x00000104},
// Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
// Net T3B DDR Settings
// DDR INIT 133Mhz
static DDR_SET_NODE asDPLL_266MHZ[] = {
{0x0F000800, 0x00007212},
{0x0f000820, 0x07F13FFF},
{0x0f000810, 0x00000F95},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
// Changed source for X - bar and MIPS clock to APLL
{0x0f000840, 0x0FFF1B00},
{0x0f000870, 0x00000002}
};
#if 0
static DDR_SET_NODE asDPLL_800MHZ[] = {
{0x0f000810, 0x00000F95},
{0x0f000810, 0x00000F95},
{0x0f000810, 0x00000F95},
{0x0f000820, 0x03F1365B},
{0x0f000840, 0x0FFF0000},
{0x0f000880, 0x000003DD},
{0x0f000860, 0x00000000}
};
#endif
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 11 // index for 0x0F007000
static DDR_SET_NODE asT3B_DDRSetting133MHz[] = {// DPLL Clock Setting
{0x0f000810, 0x00000F95},
{0x0f000810, 0x00000F95},
{0x0f000810, 0x00000F95},
{0x0f000820, 0x07F13652},
{0x0f000840, 0x0FFF0800},
// Changed source for Xbar and MIPS clock to APLL
{0x0f000880, 0x000003DD},
{0x0f000860, 0x00000000},
// Changed source for Xbar and MIPS clock to APLL
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
// Enable 2 ports within Xbar
{0x0F00A000, 0x00000016},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020001}, // POP - 0x00020001 Normal 0x01020001
{0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x02000007},
{0x0F007028, 0x02020202},
{0x0F00702c, 0x0206060a}, // ROB- 0x0205050a, 0x0206060a
{0x0F007030, 0x05000000},
{0x0F007034, 0x00000003},
{0x0F007038, 0x130a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C, 0x02101012}, // ROB - 0x02101010, 0x02101018},
{0x0F007040, 0x457D1200}, // ROB - 0x45751200, 0x450f1200},
{0x0F007044, 0x11130d00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x040D0306},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0000001c},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x0010246c},
{0x0F007064, 0x00000012},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00007000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
// # Enable BW improvement within memory controller
{0x0F007094, 0x00000104},
// # Enable start bit within memory controller
{0x0F007018, 0x01010000},
};
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 // index for 0x0F007000
static DDR_SET_NODE asT3B_DDRSetting80MHz[] = {// DPLL Clock Setting
{0x0f000810, 0x00000F95},
{0x0f000820, 0x07F13FFF},
{0x0f000840, 0x0FFF1F00},
{0x0f000880, 0x000003DD},
{0x0f000860, 0x00000000},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00a000, 0x00000016},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01000000},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020000},
{0x0F007020, 0x04020107},
{0x0F007024, 0x00000007},
{0x0F007028, 0x02020201},
{0x0F00702c, 0x0204040a},
{0x0F007030, 0x04000000},
{0x0F007034, 0x02000002},
{0x0F007038, 0x1F060202},
{0x0F00703C, 0x1C22221F},
{0x0F007040, 0x8A006600},
{0x0F007044, 0x221a0800},
{0x0F007048, 0x02690204},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x000A15D6},
{0x0F007064, 0x0000000A},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00004000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
{0x0F007094, 0x00000104},
// Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
// 100Mhz
#define T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 9 // index for 0x0F007000
static DDR_SET_NODE asT3B_DDRSetting100MHz[] = {// DPLL Clock Setting
{0x0f000810, 0x00000F95},
{0x0f000820, 0x07F1369B},
{0x0f000840, 0x0FFF0800},
{0x0f000880, 0x000003DD},
{0x0f000860, 0x00000000},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
// Enable 2 ports within Xbar
{0x0F00A000, 0x00000016},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020000}, // POP - 0x00020000 Normal 0x01020000
{0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x00000007},
{0x0F007028, 0x01020201},
{0x0F00702c, 0x0204040A},
{0x0F007030, 0x06000000},
{0x0F007034, 0x02000004},
{0x0F007038, 0x20080200},
{0x0F00703C, 0x02030320},
{0x0F007040, 0x6E7F1200},
{0x0F007044, 0x01190A00},
{0x0F007048, 0x06120305}, // 0x02690204 // 0x06120305
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001C},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x00082ED6},
{0x0F007064, 0x0000000A},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00005000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
// # Enable BW improvement within memory controller
{0x0F007094, 0x00000104},
// # Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 9 // index for 0x0F007000
static DDR_SET_NODE asT3LP_DDRSetting133MHz[] = {// DPLL Clock Setting
{0x0f000820, 0x03F1365B},
{0x0f000810, 0x00002F95},
{0x0f000880, 0x000003DD},
// Changed source for Xbar and MIPS clock to APLL
{0x0f000840, 0x0FFF0000},
{0x0f000860, 0x00000000},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00A000, 0x00000016},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020001}, // POP - 0x00020001 Normal 0x01020001
{0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x02000007},
{0x0F007028, 0x02020200},
{0x0F00702c, 0x0206060a}, // ROB - 0x0205050a, 0x0206060a
{0x0F007030, 0x05000000},
{0x0F007034, 0x00000003},
{0x0F007038, 0x200a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C, 0x02101020}, // ROB - 0x02101010, 0x02101018,
{0x0F007040, 0x45711200}, // ROB - 0x45751200, 0x450f1200,
{0x0F007044, 0x110D0D00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x04080306},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x0010245F},
{0x0F007064, 0x00000010},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00007000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
{0x0F007088, 0x01000001},
{0x0F00708c, 0x00000101},
{0x0F007090, 0x00000000},
// Enable BW improvement within memory controller
{0x0F007094, 0x00040000},
{0x0F007098, 0x00000000},
{0x0F0070c8, 0x00000104},
// Enable 2 ports within Xbar
// Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 11 // index for 0x0F007000
static DDR_SET_NODE asT3LP_DDRSetting100MHz[]= {// # DPLL Clock Setting
{0x0f000810, 0x00002F95},
{0x0f000820, 0x03F1369B},
{0x0f000840, 0x0fff0000},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
// Changed source for Xbar and MIPS clock to APLL
{0x0f000840, 0x0FFF0000},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020000}, // POP - 0x00020001 Normal 0x01020001
{0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x00000007},
{0x0F007028, 0x01020200},
{0x0F00702c, 0x0204040a}, // ROB- 0x0205050a, 0x0206060a
{0x0F007030, 0x06000000},
{0x0F007034, 0x00000004},
{0x0F007038, 0x1F080200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C, 0x0203031F}, // ROB - 0x02101010, 0x02101018,
{0x0F007040, 0x6e001200}, // ROB - 0x45751200, 0x450f1200,
{0x0F007044, 0x011a0a00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x03000305},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x00082ED6},
{0x0F007064, 0x0000000A},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00005000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
{0x0F007088, 0x01000001},
{0x0F00708c, 0x00000101},
{0x0F007090, 0x00000000},
{0x0F007094, 0x00010000},
{0x0F007098, 0x00000000},
{0x0F0070C8, 0x00000104},
// Enable 2 ports within Xbar
{0x0F00A000, 0x00000016},
// Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 // index for 0x0F007000
static DDR_SET_NODE asT3LP_DDRSetting80MHz[]= {// # DPLL Clock Setting
{0x0f000820, 0x07F13FFF},
{0x0f000810, 0x00002F95},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
{0x0f000840, 0x0FFF1F00},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0F00a084, 0x1Cffffff},
{0x0F00a080, 0x1C000000},
{0x0F00A000, 0x00000016},
{0x0f007000, 0x00010001},
{0x0f007004, 0x01000000},
{0x0f007008, 0x01000001},
{0x0f00700c, 0x00000000},
{0x0f007010, 0x01000000},
{0x0f007014, 0x01000100},
{0x0f007018, 0x01000000},
{0x0f00701c, 0x01020000},
{0x0f007020, 0x04020107},
{0x0f007024, 0x00000007},
{0x0f007028, 0x02020200},
{0x0f00702c, 0x0204040a},
{0x0f007030, 0x04000000},
{0x0f007034, 0x00000002},
{0x0f007038, 0x1d060200},
{0x0f00703c, 0x1c22221d},
{0x0f007040, 0x8A116600},
{0x0f007044, 0x222d0800},
{0x0f007048, 0x02690204},
{0x0f00704c, 0x00000000},
{0x0f007050, 0x0100001c},
{0x0f007054, 0x00000000},
{0x0f007058, 0x00000000},
{0x0f00705c, 0x00000000},
{0x0f007060, 0x000A15D6},
{0x0f007064, 0x0000000A},
{0x0f007068, 0x00000000},
{0x0f00706c, 0x00000001},
{0x0f007070, 0x00004000},
{0x0f007074, 0x00000000},
{0x0f007078, 0x00000000},
{0x0f00707c, 0x00000000},
{0x0f007080, 0x00000000},
{0x0f007084, 0x00000000},
{0x0f007088, 0x01000001},
{0x0f00708c, 0x00000101},
{0x0f007090, 0x00000000},
{0x0f007094, 0x00010000},
{0x0f007098, 0x00000000},
{0x0F0070C8, 0x00000104},
{0x0F007018, 0x01010000}
};
// T3 LP-B (UMA-B)
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ 7 // index for 0x0F007000
static DDR_SET_NODE asT3LPB_DDRSetting160MHz[]= {// # DPLL Clock Setting
{0x0f000820, 0x03F137DB},
{0x0f000810, 0x01842795},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
{0x0f000840, 0x0FFF0400},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to 20 MHz
{0x0F00a084, 0x1Cffffff}, // Now dump from her in internal memory
{0x0F00a080, 0x1C000000},
{0x0F00A000, 0x00000016},
{0x0f007000, 0x00010001},
{0x0f007004, 0x01000001},
{0x0f007008, 0x01000101},
{0x0f00700c, 0x00000000},
{0x0f007010, 0x01000100},
{0x0f007014, 0x01000100},
{0x0f007018, 0x01000000},
{0x0f00701c, 0x01020000},
{0x0f007020, 0x04030107},
{0x0f007024, 0x02000007},
{0x0f007028, 0x02020200},
{0x0f00702c, 0x0206060a},
{0x0f007030, 0x050d0d00},
{0x0f007034, 0x00000003},
{0x0f007038, 0x170a0200},
{0x0f00703c, 0x02101012},
{0x0f007040, 0x45161200},
{0x0f007044, 0x11250c00},
{0x0f007048, 0x04da0307},
{0x0f00704c, 0x00000000},
{0x0f007050, 0x0000001c},
{0x0f007054, 0x00000000},
{0x0f007058, 0x00000000},
{0x0f00705c, 0x00000000},
{0x0f007060, 0x00142bb6},
{0x0f007064, 0x20430014},
{0x0f007068, 0x00000000},
{0x0f00706c, 0x00000001},
{0x0f007070, 0x00009000},
{0x0f007074, 0x00000000},
{0x0f007078, 0x00000000},
{0x0f00707c, 0x00000000},
{0x0f007080, 0x00000000},
{0x0f007084, 0x00000000},
{0x0f007088, 0x01000001},
{0x0f00708c, 0x00000101},
{0x0f007090, 0x00000000},
{0x0f007094, 0x00040000},
{0x0f007098, 0x00000000},
{0x0F0070C8, 0x00000104},
{0x0F007018, 0x01010000}
};
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 7 // index for 0x0F007000
static DDR_SET_NODE asT3LPB_DDRSetting133MHz[]= {// # DPLL Clock Setting
{0x0f000820, 0x03F1365B},
{0x0f000810, 0x00002F95},
{0x0f000880, 0x000003DD},
// Changed source for Xbar and MIPS clock to APLL
{0x0f000840, 0x0FFF0000},
{0x0f000860, 0x00000000},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to 20 MHz
{0x0F00a084, 0x1Cffffff}, // dump from here in internal memory
{0x0F00a080, 0x1C000000},
{0x0F00A000, 0x00000016},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020001}, // POP - 0x00020001 Normal 0x01020001
{0x0F007020, 0x04030107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x02000007},
{0x0F007028, 0x02020200},
{0x0F00702c, 0x0206060a}, // ROB- 0x0205050a, 0x0206060a
{0x0F007030, 0x05000000},
{0x0F007034, 0x00000003},
{0x0F007038, 0x190a0200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C, 0x02101017}, // ROB - 0x02101010, 0x02101018,
{0x0F007040, 0x45171200}, // ROB - 0x45751200, 0x450f1200,
{0x0F007044, 0x11290D00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x04080306},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x0010245F},
{0x0F007064, 0x00000010},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00007000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
{0x0F007088, 0x01000001},
{0x0F00708c, 0x00000101},
{0x0F007090, 0x00000000},
// Enable BW improvement within memory controller
{0x0F007094, 0x00040000},
{0x0F007098, 0x00000000},
{0x0F0070c8, 0x00000104},
// Enable 2 ports within Xbar
// Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 8 // index for 0x0F007000
static DDR_SET_NODE asT3LPB_DDRSetting100MHz[]= {// # DPLL Clock Setting
{0x0f000810, 0x00002F95},
{0x0f000820, 0x03F1369B},
{0x0f000840, 0x0fff0000},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
// Changed source for Xbar and MIPS clock to APLL
{0x0f000840, 0x0FFF0000},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to 20 MHz
{0x0F00a084, 0x1Cffffff}, // dump from here in internal memory
{0x0F00a080, 0x1C000000},
// Memcontroller Default values
{0x0F007000, 0x00010001},
{0x0F007004, 0x01010100},
{0x0F007008, 0x01000001},
{0x0F00700c, 0x00000000},
{0x0F007010, 0x01000000},
{0x0F007014, 0x01000100},
{0x0F007018, 0x01000000},
{0x0F00701c, 0x01020000}, // POP - 0x00020001 Normal 0x01020001
{0x0F007020, 0x04020107}, // Normal - 0x04030107 POP - 0x05030107
{0x0F007024, 0x00000007},
{0x0F007028, 0x01020200},
{0x0F00702c, 0x0204040a}, // ROB- 0x0205050a, 0x0206060a
{0x0F007030, 0x06000000},
{0x0F007034, 0x00000004},
{0x0F007038, 0x1F080200}, // ROB - 0x110a0200, 0x180a0200, 0x1f0a0200
{0x0F00703C, 0x0203031F}, // ROB - 0x02101010, 0x02101018,
{0x0F007040, 0x6e001200}, // ROB - 0x45751200, 0x450f1200,
{0x0F007044, 0x011a0a00}, // ROB - 0x110a0d00, 0x111f0d00
{0x0F007048, 0x03000305},
{0x0F00704c, 0x00000000},
{0x0F007050, 0x0100001c},
{0x0F007054, 0x00000000},
{0x0F007058, 0x00000000},
{0x0F00705c, 0x00000000},
{0x0F007060, 0x00082ED6},
{0x0F007064, 0x0000000A},
{0x0F007068, 0x00000000},
{0x0F00706c, 0x00000001},
{0x0F007070, 0x00005000},
{0x0F007074, 0x00000000},
{0x0F007078, 0x00000000},
{0x0F00707C, 0x00000000},
{0x0F007080, 0x00000000},
{0x0F007084, 0x00000000},
{0x0F007088, 0x01000001},
{0x0F00708c, 0x00000101},
{0x0F007090, 0x00000000},
{0x0F007094, 0x00010000},
{0x0F007098, 0x00000000},
{0x0F0070C8, 0x00000104},
// # Enable 2 ports within Xbar
{0x0F00A000, 0x00000016},
// # Enable start bit within memory controller
{0x0F007018, 0x01010000}
};
#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 7 // index for 0x0F007000
static DDR_SET_NODE asT3LPB_DDRSetting80MHz[]= {// DPLL Clock Setting
{0x0f000820, 0x07F13FFF},
{0x0f000810, 0x00002F95},
{0x0f000860, 0x00000000},
{0x0f000880, 0x000003DD},
{0x0f000840, 0x0FFF1F00},
{0x0F00a044, 0x1fffffff},
{0x0F00a040, 0x1f000000},
{0x0f003050, 0x00000021}, // nvm clock divisor set the flash clock to 20 MHz
{0x0F00a084, 0x1Cffffff}, // dump from here in internal memory
{0x0F00a080, 0x1C000000},
{0x0F00A000, 0x00000016},
{0x0f007000, 0x00010001},
{0x0f007004, 0x01000000},
{0x0f007008, 0x01000001},
{0x0f00700c, 0x00000000},
{0x0f007010, 0x01000000},
{0x0f007014, 0x01000100},
{0x0f007018, 0x01000000},
{0x0f00701c, 0x01020000},
{0x0f007020, 0x04020107},
{0x0f007024, 0x00000007},
{0x0f007028, 0x02020200},
{0x0f00702c, 0x0204040a},
{0x0f007030, 0x04000000},
{0x0f007034, 0x00000002},
{0x0f007038, 0x1d060200},
{0x0f00703c, 0x1c22221d},
{0x0f007040, 0x8A116600},
{0x0f007044, 0x222d0800},
{0x0f007048, 0x02690204},
{0x0f00704c, 0x00000000},
{0x0f007050, 0x0100001c},
{0x0f007054, 0x00000000},
{0x0f007058, 0x00000000},
{0x0f00705c, 0x00000000},
{0x0f007060, 0x000A15D6},
{0x0f007064, 0x0000000A},
{0x0f007068, 0x00000000},
{0x0f00706c, 0x00000001},
{0x0f007070, 0x00004000},
{0x0f007074, 0x00000000},
{0x0f007078, 0x00000000},
{0x0f00707c, 0x00000000},
{0x0f007080, 0x00000000},
{0x0f007084, 0x00000000},
{0x0f007088, 0x01000001},
{0x0f00708c, 0x00000101},
{0x0f007090, 0x00000000},
{0x0f007094, 0x00010000},
{0x0f007098, 0x00000000},
{0x0F0070C8, 0x00000104},
{0x0F007018, 0x01010000}
};
#endif // _USB_BECEEM_DDR_TIMING_H_
src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemDevice.cpp
+17 -17
View File
@@ -47,7 +47,7 @@ public:
status_t
BeceemDevice::ReadRegister(unsigned int reg, size_t size, uint32_t* buffer)
BeceemDevice::ReadRegister(uint32 reg, size_t size, uint32* buffer)
{
USBSmartLock USBSubsystemLock; // released on exit
@@ -92,7 +92,7 @@ BeceemDevice::ReadRegister(unsigned int reg, size_t size, uint32_t* buffer)
status_t
BeceemDevice::WriteRegister(unsigned int reg, size_t size, uint32_t* buffer)
BeceemDevice::WriteRegister(uint32 reg, size_t size, uint32* buffer)
{
USBSmartLock USBSubsystemLock; // released on exit
@@ -139,8 +139,8 @@ BeceemDevice::WriteRegister(unsigned int reg, size_t size, uint32_t* buffer)
status_t
BeceemDevice::BizarroReadRegister(unsigned int reg, size_t size,
uint32_t* buffer)
BeceemDevice::BizarroReadRegister(uint32 reg, size_t size,
uint32* buffer)
{
// NET_TO_HOST long
@@ -154,12 +154,12 @@ BeceemDevice::BizarroReadRegister(unsigned int reg, size_t size,
status_t
BeceemDevice::BizarroWriteRegister(unsigned int reg, size_t size,
uint32_t* buffer)
BeceemDevice::BizarroWriteRegister(uint32 reg, size_t size,
uint32* buffer)
{
// HOST_TO_NET long
volatile uint32_t reload = *buffer;
volatile uint32 reload = *buffer;
convertEndian(true, size, buffer);
@@ -577,7 +577,7 @@ status_t
BeceemDevice::IdentifyChipset()
{
if (BizarroReadRegister(CHIP_ID_REG, sizeof(unsigned int),
if (BizarroReadRegister(CHIP_ID_REG, sizeof(uint32),
&pwmxdevice->deviceChipID) != B_OK)
{
TRACE_ALWAYS("Error: Beceem device identification read failure\n");
@@ -647,7 +647,7 @@ BeceemDevice::SetupDevice(bool deviceReplugged)
return B_ERROR;
if (pwmxdevice->deviceChipID >= T3LPB) {
unsigned int value = 0;
uint32 value = 0;
BizarroReadRegister(SYS_CFG, sizeof(value), &value);
pwmxdevice->syscfgBefFw = value;
if ((value & 0x60) == 0) {
@@ -689,12 +689,12 @@ BeceemDevice::SetupDevice(bool deviceReplugged)
if (pwmxdevice->nvmVerMajor < 5) {
TRACE("Debug: VerMajor < 5 PARAM pointer\n");
NVMRead(GPIO_PARAM_POINTER, 2,
(unsigned int*)&pwmxdevice->hwParamPtr);
(uint32*)&pwmxdevice->hwParamPtr);
pwmxdevice->hwParamPtr = ntohs(pwmxdevice->hwParamPtr);
} else {
TRACE("Debug: VerMajor 5+ PARAM pointer\n");
NVMRead(GPIO_PARAM_POINTER_MAP5, 4,
(unsigned int*)&pwmxdevice->hwParamPtr);
(uint32*)&pwmxdevice->hwParamPtr);
// TODO : NVM : validate v5+ nvm params a-la ValidateDSDParamsChecksum
pwmxdevice->hwParamPtr = ntohl(pwmxdevice->hwParamPtr);
}
@@ -714,7 +714,7 @@ BeceemDevice::SetupDevice(bool deviceReplugged)
dwReadValue = dwReadValue + GPIO_START_OFFSET;
// add GPIO start offset
NVMRead(dwReadValue, 32, (uint32_t*)&pwmxdevice->gpioInfo);
NVMRead(dwReadValue, 32, (uint32*)&pwmxdevice->gpioInfo);
// populate for LED information
ValidateDSD(pwmxdevice->hwParamPtr);
@@ -1010,7 +1010,7 @@ BeceemDevice::LoadConfig()
size_t file_size = cfgStat.st_size;
unsigned int* buffer = (unsigned int*)malloc(MAX_USB_TRANSFER);
uint32* buffer = (uint32*)malloc(MAX_USB_TRANSFER);
if (buffer == NULL) {
TRACE_ALWAYS("Error: Memory allocation error.\n");
@@ -1103,7 +1103,7 @@ BeceemDevice::DumpConfig()
status_t
BeceemDevice::PushConfig(unsigned int loc)
BeceemDevice::PushConfig(uint32 loc)
{
int fh = open(FIRM_CFG, O_RDONLY);
@@ -1117,7 +1117,7 @@ BeceemDevice::PushConfig(unsigned int loc)
TRACE_ALWAYS("Info: Vendor configuration to be pushed to 0x%x on device.\n",
loc);
unsigned int* buffer = (unsigned int*)malloc(MAX_USB_TRANSFER);
uint32* buffer = (uint32*)malloc(MAX_USB_TRANSFER);
if (!buffer) {
TRACE_ALWAYS("Error: Memory allocation error.\n");
@@ -1175,7 +1175,7 @@ BeceemDevice::PushConfig(unsigned int loc)
status_t
BeceemDevice::PushFirmware(unsigned int loc)
BeceemDevice::PushFirmware(uint32 loc)
{
int fh = open(FIRM_BIN, O_RDONLY);
@@ -1195,7 +1195,7 @@ BeceemDevice::PushFirmware(unsigned int loc)
file_size, loc);
// For the push we load the file into the buffer
unsigned int* buffer = (unsigned int*)malloc(MAX_USB_TRANSFER);
uint32* buffer = (uint32*)malloc(MAX_USB_TRANSFER);
if (!buffer) {
TRACE_ALWAYS("Error: Memory allocation error.\n");
src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemDevice.h
+10 -10
View File
@@ -58,22 +58,22 @@ virtual ~BeceemDevice();
status_t Control(uint32 op, void *buffer, size_t length);
status_t LoadConfig();
void DumpConfig();
status_t PushConfig(unsigned int loc);
status_t PushFirmware(unsigned int loc);
status_t PushConfig(uint32 loc);
status_t PushFirmware(uint32 loc);
void Removed();
status_t CompareAndReattach(usb_device device);
virtual status_t SetupDevice(bool deviceReplugged);
status_t ReadRegister(unsigned int reg,
size_t size, uint32_t* buffer);
status_t WriteRegister(unsigned int reg,
size_t size, uint32_t* buffer);
status_t BizarroReadRegister(unsigned int reg,
size_t size, uint32_t* buffer);
status_t BizarroWriteRegister(unsigned int reg,
size_t size, uint32_t* buffer);
status_t ReadRegister(uint32 reg,
size_t size, uint32* buffer);
status_t WriteRegister(uint32 reg,
size_t size, uint32* buffer);
status_t BizarroReadRegister(uint32 reg,
size_t size, uint32* buffer);
status_t BizarroWriteRegister(uint32 reg,
size_t size, uint32* buffer);
private:
static void _ReadCallback(void *cookie, int32 status,
src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemLED.cpp
+42 -58
View File
@@ -27,21 +27,18 @@ BeceemLED::LEDInit(WIMAX_DEVICE* wmxdevice)
{
pwmxdevice = wmxdevice;
uint8_t GPIO_Array[NUM_OF_LEDS+1];
unsigned char ucIndex = 0;
uint32_t uiIndex = 0;
unsigned char* puCFGData = NULL;
unsigned char bData = 0;
uint8 GPIO_Array[NUM_OF_LEDS + 1];
uint8 ucIndex = 0;
uint32 uiIndex = 0;
memset(GPIO_Array, GPIO_DISABLE_VAL, NUM_OF_LEDS+1);
memset(GPIO_Array, GPIO_DISABLE_VAL, NUM_OF_LEDS + 1);
TRACE("Debug: Raw GPIO information: 0x%x\n", pwmxdevice->gpioInfo);
snooze(500000);
if (pwmxdevice->deviceChipID == 0xbece0120
|| pwmxdevice->deviceChipID == 0xbece0121)
{
|| pwmxdevice->deviceChipID == 0xbece0121) {
/*Hardcode the values of GPIO numbers for ASIC board.*/
GPIO_Array[RED_LED] = 2;
GPIO_Array[BLUE_LED] = 3;
@@ -49,29 +46,27 @@ BeceemLED::LEDInit(WIMAX_DEVICE* wmxdevice)
GPIO_Array[GREEN_LED] = 4;
} else {
// for all possible GPIO pins...
for (ucIndex = 0; ucIndex < 32; ucIndex++)
{
switch(pwmxdevice->gpioInfo[ucIndex])
{
for (ucIndex = 0; ucIndex < 32; ucIndex++) {
switch(pwmxdevice->gpioInfo[ucIndex]) {
case RED_LED:
TRACE("Debug: GPIO: %d found RED_LED!\n", ucIndex);
GPIO_Array[RED_LED] = ucIndex;
pwmxdevice->gpioBitMap |= (1<<ucIndex);
pwmxdevice->gpioBitMap |= (1 << ucIndex);
break;
case BLUE_LED:
TRACE("Debug: GPIO: %d found BLUE_LED!\n", ucIndex);
GPIO_Array[BLUE_LED] = ucIndex;
pwmxdevice->gpioBitMap |= (1<<ucIndex);
pwmxdevice->gpioBitMap |= (1 << ucIndex);
break;
case YELLOW_LED:
TRACE("Debug: GPIO: %d found YELLOW_LED!\n", ucIndex);
GPIO_Array[YELLOW_LED] = ucIndex;
pwmxdevice->gpioBitMap |= (1<<ucIndex);
pwmxdevice->gpioBitMap |= (1 << ucIndex);
break;
case GREEN_LED:
TRACE("Debug: GPIO: %d found GREEN_LED!\n", ucIndex);
GPIO_Array[GREEN_LED] = ucIndex;
pwmxdevice->gpioBitMap |= (1<<ucIndex);
pwmxdevice->gpioBitMap |= (1 << ucIndex);
break;
default:
// TRACE("Debug: GPIO: %d found NO_LED!\n", ucIndex);
@@ -84,15 +79,14 @@ BeceemLED::LEDInit(WIMAX_DEVICE* wmxdevice)
pwmxdevice->gpioBitMap);
// Load GPIO configuration data from vendor config
puCFGData = (unsigned char *)&pwmxdevice->vendorcfg.HostDrvrConfig1;
uint8* puCFGData = (uint8*)&pwmxdevice->vendorcfg.HostDrvrConfig1;
for (uiIndex = 0; uiIndex < NUM_OF_LEDS; uiIndex++)
{
bData = *puCFGData;
for (uiIndex = 0; uiIndex < NUM_OF_LEDS; uiIndex++) {
uint8 bData = *puCFGData;
// Check Bit 8 for polarity. If it is set, polarity is reverse
if (bData & 0x80)
{
if (bData & 0x80) {
pwmxdevice->LEDMap.LEDState[uiIndex].BitPolarity = 0;
// unset bit 8
bData = bData & 0x7f;
@@ -123,8 +117,7 @@ BeceemLED::LEDInit(WIMAX_DEVICE* wmxdevice)
GPIOReset(); // Set all GPIO pins to off
for (uiIndex = 0; uiIndex<NUM_OF_LEDS; uiIndex++)
{
for (uiIndex = 0; uiIndex < NUM_OF_LEDS; uiIndex++) {
if (pwmxdevice->LEDMap.LEDState[uiIndex].GPIO_Num != GPIO_DISABLE_VAL) {
LEDOn(uiIndex);
TRACE("Debug: LED[%d].LED_Type = %x\n",
@@ -144,12 +137,12 @@ BeceemLED::LEDInit(WIMAX_DEVICE* wmxdevice)
// Spawn LED monitor / blink thread
pwmxdevice->LEDThreadID = spawn_kernel_thread(LEDThread,
"usb_beceemwmx GPIO:LED",
B_NORMAL_PRIORITY, this);
pwmxdevice->LEDThreadID = spawn_kernel_thread(LEDThread,
"usb_beceemwmx GPIO:LED", B_NORMAL_PRIORITY, this);
if (pwmxdevice->LEDThreadID < 1) {
TRACE("Error: Problem spawning LED Thread: %i\n", pwmxdevice->LEDThreadID);
TRACE("Error: Problem spawning LED Thread: %i\n",
pwmxdevice->LEDThreadID);
return B_ERROR;
}
@@ -196,10 +189,9 @@ BeceemLED::LEDThreadTerminate()
status_t
BeceemLED::LightsOut()
{
unsigned int uiIndex = 0;
uint32 uiIndex;
for (uiIndex = 0; uiIndex < NUM_OF_LEDS; uiIndex++)
{
for (uiIndex = 0; uiIndex < NUM_OF_LEDS; uiIndex++) {
if (pwmxdevice->LEDMap.LEDState[uiIndex].GPIO_Num != GPIO_DISABLE_VAL) {
LEDOff(uiIndex);
}
@@ -209,13 +201,11 @@ BeceemLED::LightsOut()
status_t
BeceemLED::LEDOn(unsigned int index)
BeceemLED::LEDOn(uint32 index)
{
status_t result;
uint32_t gpio_towrite = 0;
uint32_t uiResetValue = 0;
status_t result;
gpio_towrite = 1<<pwmxdevice->LEDMap.LEDState[index].GPIO_Num;
uint32 gpio_towrite = 1 << pwmxdevice->LEDMap.LEDState[index].GPIO_Num;
if (pwmxdevice->LEDMap.LEDState[index].BitPolarity == 0)
result = BizarroWriteRegister(GPIO_OUTPUT_SET_REG,
@@ -229,23 +219,22 @@ BeceemLED::LEDOn(unsigned int index)
index, gpio_towrite, pwmxdevice->LEDMap.LEDState[index].GPIO_Num);
}
uiResetValue = BizarroReadRegister(GPIO_MODE_REGISTER,
uint32 uiResetValue = BizarroReadRegister(GPIO_MODE_REGISTER,
sizeof(uiResetValue), &uiResetValue);
uiResetValue |= gpio_towrite;
BizarroWriteRegister(GPIO_MODE_REGISTER, sizeof(uiResetValue), &uiResetValue);
BizarroWriteRegister(GPIO_MODE_REGISTER,
sizeof(uiResetValue), &uiResetValue);
return B_OK;
}
status_t
BeceemLED::LEDOff(unsigned int index)
BeceemLED::LEDOff(uint32 index)
{
status_t result;
uint32_t gpio_towrite = 0;
uint32_t uiResetValue = 0;
status_t result;
gpio_towrite = 1<<pwmxdevice->LEDMap.LEDState[index].GPIO_Num;
uint32 gpio_towrite = 1 << pwmxdevice->LEDMap.LEDState[index].GPIO_Num;
if (pwmxdevice->LEDMap.LEDState[index].BitPolarity == 0)
result = BizarroWriteRegister(GPIO_OUTPUT_CLR_REG,
@@ -259,7 +248,7 @@ BeceemLED::LEDOff(unsigned int index)
index, gpio_towrite, pwmxdevice->LEDMap.LEDState[index].GPIO_Num);
}
uiResetValue = BizarroReadRegister(GPIO_MODE_REGISTER,
uint32 uiResetValue = BizarroReadRegister(GPIO_MODE_REGISTER,
sizeof(uiResetValue), &uiResetValue);
uiResetValue |= gpio_towrite;
BizarroWriteRegister(GPIO_MODE_REGISTER,
@@ -276,24 +265,21 @@ BeceemLED::LEDThread(void *cookie)
BeceemLED *led = (BeceemLED *)cookie;
// While the driver is active
while (!led->pwmxdevice->driverHalt)
{
unsigned int uiIndex = 0;
unsigned int uiLedIndex = 0;
bool blink = false;
while (!led->pwmxdevice->driverHalt) {
bool blink = false;
// LED state changes will be at least 500ms apart
snooze(500000);
uint32 uiIndex;
uint32 uiLedIndex = 0;
// determine what the LED is doing in each state
switch(led->pwmxdevice->driverState)
{
case STATE_FWPUSH:
for (uiIndex = 0; uiIndex < NUM_OF_LEDS; uiIndex++)
{
if (led->pwmxdevice->LEDMap.LEDState[uiIndex].LED_Blink_State
& STATE_FWPUSH)
{
for (uiIndex = 0; uiIndex < NUM_OF_LEDS; uiIndex++) {
if (led->pwmxdevice->LEDMap
.LEDState[uiIndex].LED_Blink_State & STATE_FWPUSH) {
if (led->pwmxdevice->LEDMap.LEDState[uiIndex].GPIO_Num
!= GPIO_DISABLE_VAL) {
uiLedIndex = uiIndex;
@@ -304,11 +290,9 @@ BeceemLED::LEDThread(void *cookie)
break;
case STATE_NONET:
for (uiIndex = 0; uiIndex < NUM_OF_LEDS; uiIndex++)
{
for (uiIndex = 0; uiIndex < NUM_OF_LEDS; uiIndex++) {
if (led->pwmxdevice->LEDMap.LEDState[uiIndex].LED_On_State
& STATE_NONET)
{
& STATE_NONET) {
if (led->pwmxdevice->LEDMap.LEDState[uiIndex].GPIO_Num
!= GPIO_DISABLE_VAL) {
uiLedIndex = uiIndex;
src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemLED.h
+10 -10
View File
@@ -20,25 +20,25 @@ public:
BeceemLED();
status_t LEDInit(WIMAX_DEVICE* wmxdevice);
status_t LEDThreadTerminate();
status_t LEDOff(unsigned int index);
status_t LEDOn(unsigned int index);
status_t LEDOff(uint32 index);
status_t LEDOn(uint32 index);
status_t LightsOut();
static status_t LEDThread(void *cookie);
WIMAX_DEVICE* pwmxdevice;
// yuck. These are in a parent class
virtual status_t ReadRegister(unsigned int reg,
size_t size, uint32_t* buffer)
virtual status_t ReadRegister(uint32 reg,
size_t size, uint32* buffer)
{ return NULL; };
virtual status_t WriteRegister(unsigned int reg,
size_t size, uint32_t* buffer)
virtual status_t WriteRegister(uint32 reg,
size_t size, uint32* buffer)
{ return NULL; };
virtual status_t BizarroReadRegister(unsigned int reg,
size_t size, uint32_t* buffer)
virtual status_t BizarroReadRegister(uint32 reg,
size_t size, uint32* buffer)
{ return NULL; };
virtual status_t BizarroWriteRegister(unsigned int reg,
size_t size, uint32_t* buffer)
virtual status_t BizarroWriteRegister(uint32 reg,
size_t size, uint32* buffer)
{ return NULL; };
private:
src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemNVM.cpp
+66 -66
View File
@@ -43,7 +43,7 @@ BeceemNVM::NVMInit(WIMAX_DEVICE* swmxdevice)
unsigned short usNVMVersion = 0;
NVMRead(NVM_VERSION_OFFSET, 2, (unsigned int*)&usNVMVersion);
NVMRead(NVM_VERSION_OFFSET, 2, (uint32*)&usNVMVersion);
pwmxdevice->nvmVerMinor = usNVMVersion&0xFF;
pwmxdevice->nvmVerMajor = ((usNVMVersion>>8)&0xFF);
@@ -62,7 +62,7 @@ BeceemNVM::NVMFlush()
* But we get 0x00001122. */
TRACE("Debug: Fixing reset value on 0x0f003004\n");
unsigned int value = NVM_READ_DATA_AVAIL;
uint32 value = NVM_READ_DATA_AVAIL;
BizarroWriteRegister(NVM_SPI_Q_STATUS1_REG, sizeof(value), &value);
/* Flush the all of the NVM queues. */
@@ -79,7 +79,7 @@ BeceemNVM::NVMFlush()
status_t
BeceemNVM::NVMDetect()
{
unsigned int uiData = 0;
uint32 uiData = 0;
EEPROMBulkRead(0x0, 4, &uiData);
if (uiData == BECM) {
@@ -111,7 +111,7 @@ BeceemNVM::NVMDetect()
status_t
BeceemNVM::NVMChipSelect(unsigned int offset)
BeceemNVM::NVMChipSelect(uint32 offset)
{
int chipIndex = offset / FLASH_PART_SIZE;
@@ -125,16 +125,16 @@ BeceemNVM::NVMChipSelect(unsigned int offset)
// Migrate selected chip to new selection
bSelectedChip = chipIndex;
unsigned int flashConfig = 0;
uint32 flashConfig = 0;
BizarroReadRegister(FLASH_CONFIG_REG, 4, &flashConfig);
unsigned int gpioConfig = 0;
uint32 gpioConfig = 0;
BizarroReadRegister(FLASH_GPIO_CONFIG_REG, 4, &gpioConfig);
// TRACE("Reading GPIO config 0x%x\n", &GPIOConfig);
// TRACE("Reading Flash config 0x%x\n", &FlashConfig);
unsigned int partitionNumber = 0;
uint32 partitionNumber = 0;
switch (chipIndex) {
case 0:
partitionNumber = 0;
@@ -175,12 +175,12 @@ BeceemNVM::NVMChipSelect(unsigned int offset)
int
BeceemNVM::NVMRead(unsigned int offset, unsigned int size, unsigned int* buffer)
BeceemNVM::NVMRead(uint32 offset, uint32 size, uint32* buffer)
{
unsigned int temp = 0;
unsigned int value = 0;
uint32 temp = 0;
uint32 value = 0;
int status = 0;
unsigned int myOffset = 0;
uint32 myOffset = 0;
if (pwmxdevice->nvmType == NVM_FLASH) {
@@ -218,11 +218,11 @@ BeceemNVM::NVMRead(unsigned int offset, unsigned int size, unsigned int* buffer)
int
BeceemNVM::NVMWrite(unsigned int offset, unsigned int size,
unsigned int* buffer)
BeceemNVM::NVMWrite(uint32 offset, uint32 size,
uint32* buffer)
{
unsigned int temp = 0;
unsigned int value = 0;
uint32 temp = 0;
uint32 value = 0;
int status = 0;
if (pwmxdevice->nvmType == NVM_FLASH) {
@@ -277,7 +277,7 @@ BeceemNVM::FlashGetBaseAddr()
}
unsigned int
uint32
BeceemNVM::FlashGetSize()
{
// TODO : Check for Flash2X
@@ -289,7 +289,7 @@ unsigned long
BeceemNVM::FlashReadID()
{
// Read the ID from FLASH_CMD_READ_ID
unsigned int value = FLASH_CMD_READ_ID << 24;
uint32 value = FLASH_CMD_READ_ID << 24;
BizarroWriteRegister(FLASH_SPI_CMDQ_REG, sizeof(value), &value);
snooze(10);
@@ -298,7 +298,7 @@ BeceemNVM::FlashReadID()
// The ID is the first 3 bytes.
unsigned long readQID = 0;
BizarroReadRegister(FLASH_SPI_READQ_REG, sizeof(readQID),
(unsigned int*)&readQID);
(uint32*)&readQID);
return readQID >> 8;
}
@@ -318,13 +318,13 @@ BeceemNVM::FlashReadCS()
if (pwmxdevice->driverDDRinit == false)
{
unsigned int value = FLASH_CONTIGIOUS_START_ADDR_BEFORE_INIT;
uint32 value = FLASH_CONTIGIOUS_START_ADDR_BEFORE_INIT;
BizarroWriteRegister(0xAF00A080, sizeof(value), &value);
}
// CS Signature(4), Minor(2), Major(2)
FlashBulkRead(pwmxdevice->nvmFlashCSStart, 8,
(unsigned int*)pwmxdevice->nvmFlashCSInfo);
(uint32*)pwmxdevice->nvmFlashCSInfo);
pwmxdevice->nvmFlashCSInfo->FlashLayoutVersion
= ntohl(pwmxdevice->nvmFlashCSInfo->FlashLayoutVersion);
@@ -349,7 +349,7 @@ BeceemNVM::FlashReadCS()
{
// device is older flash map
FlashBulkRead(pwmxdevice->nvmFlashCSStart, sizeof(FLASH_CS_INFO),
(unsigned int*)pwmxdevice->nvmFlashCSInfo);
(uint32*)pwmxdevice->nvmFlashCSInfo);
snooze(100);
FlashCSFlip(pwmxdevice->nvmFlashCSInfo);
FlashCSDump(pwmxdevice->nvmFlashCSInfo);
@@ -495,8 +495,8 @@ BeceemNVM::FlashCSDump(PFLASH_CS_INFO FlashCSInfo)
status_t
BeceemNVM::FlashBulkRead(unsigned int offset, unsigned int size,
unsigned int* buffer)
BeceemNVM::FlashBulkRead(uint32 offset, uint32 size,
uint32* buffer)
{
if (pwmxdevice->driverHalt == true)
return -ENODEV;
@@ -508,24 +508,24 @@ BeceemNVM::FlashBulkRead(unsigned int offset, unsigned int size,
TRACE("Debug: About to read %d bytes from 0x%x \n", size, offset);
unsigned int workOffset = offset; // our scratch work offset
unsigned int bytesLeft = size; // counter holding bytes left
unsigned int outputOffset = 0; // where we are in the output
uint32 workOffset = offset; // our scratch work offset
uint32 bytesLeft = size; // counter holding bytes left
uint32 outputOffset = 0; // where we are in the output
while (bytesLeft > 0)
{
NVMChipSelect(workOffset);
unsigned int partOffset = (workOffset & (FLASH_PART_SIZE - 1))
uint32 partOffset = (workOffset & (FLASH_PART_SIZE - 1))
+ FlashGetBaseAddr();
unsigned int workBytes = MIN(MAX_RW_SIZE, bytesLeft);
uint32 workBytes = MIN(MAX_RW_SIZE, bytesLeft);
// We read the max RW size or whats left
TRACE("Debug: reading %d bytes from 0x%x to 0x%x (output offset %d)\n",
workBytes, partOffset, partOffset + workBytes, outputOffset);
if (ReadRegister(partOffset, workBytes,
(unsigned int*)((unsigned char*)buffer + outputOffset)) != B_OK) {
(uint32*)((unsigned char*)buffer + outputOffset)) != B_OK) {
// I've only done this once before.
TRACE_ALWAYS("Error: Read error at 0x%x."
" Read of %d bytes failed.\n",
@@ -550,7 +550,7 @@ BeceemNVM::FlashBulkRead(unsigned int offset, unsigned int size,
status_t
BeceemNVM::RestoreBlockProtect(unsigned long writestatus)
{
unsigned int value = (FLASH_CMD_WRITE_ENABLE<< 24);
uint32 value = (FLASH_CMD_WRITE_ENABLE<< 24);
BizarroWriteRegister(FLASH_SPI_CMDQ_REG, sizeof(value), &value);
snooze(20);
@@ -563,15 +563,15 @@ BeceemNVM::RestoreBlockProtect(unsigned long writestatus)
unsigned long
BeceemNVM::DisableBlockProtect(unsigned int offset, size_t size)
BeceemNVM::DisableBlockProtect(uint32 offset, size_t size)
{
return 0;
}
status_t
BeceemNVM::FlashBulkWrite(unsigned int offset, unsigned int size,
unsigned int* buffer)
BeceemNVM::FlashBulkWrite(uint32 offset, uint32 size,
uint32* buffer)
{
// TODO : Implement flash writing, not really needed for normal use
TRACE_ALWAYS("%s: Not yet implemented\n", __func__);
@@ -580,19 +580,19 @@ BeceemNVM::FlashBulkWrite(unsigned int offset, unsigned int size,
status_t
BeceemNVM::FlashSectorErase(unsigned int addr, unsigned int numOfSectors)
BeceemNVM::FlashSectorErase(uint32 addr, uint32 numOfSectors)
{
TRACE("Debug: Erasing %d sectors at 0x%x\n", numOfSectors, addr);
unsigned int uiStatus = 0;
unsigned int iIndex;
uint32 uiStatus = 0;
uint32 iIndex;
for (iIndex = 0 ; iIndex < numOfSectors ; iIndex++) {
unsigned int value = 0x06000000;
uint32 value = 0x06000000;
BizarroWriteRegister(FLASH_SPI_CMDQ_REG, sizeof(value), &value);
value = (0xd8000000 | (addr & 0xFFFFFF));
BizarroWriteRegister(FLASH_SPI_CMDQ_REG, sizeof(value), &value);
unsigned int iRetries = 0;
uint32 iRetries = 0;
do {
value = (FLASH_CMD_STATUS_REG_READ << 24);
@@ -630,14 +630,14 @@ status_t
BeceemNVM::ReadMACFromNVM(ether_address *address)
{
unsigned char MacAddr[6] = {0};
status_t status = NVMRead(MAC_ADDR_OFFSET, 6, (unsigned int*)&MacAddr[0]);
status_t status = NVMRead(MAC_ADDR_OFFSET, 6, (uint32*)&MacAddr[0]);
memcpy(address, MacAddr, 6);
return (status);
}
unsigned int
uint32
BeceemNVM::EEPROMGetSize()
{
// To find the EEPROM size read the possible boundaries of the
@@ -645,12 +645,12 @@ BeceemNVM::EEPROMGetSize()
// result in wrap around. So when we get the End of the EEPROM we will
// get 'BECM' string which is indeed at offset 0.
unsigned int uiData = 0;
uint32 uiData = 0;
EEPROMBulkRead(0x0, 4, &uiData);
if (ntohl(uiData) == BECM) {
// If EEPROM is present, it will have 'BECM' string at 0th offset.
unsigned int uiIndex;
uint32 uiIndex;
for (uiIndex = 1 ; uiIndex <= 256; uiIndex *= 2) {
EEPROMBulkRead(uiIndex * 1024, 4, &uiData);
@@ -664,16 +664,16 @@ BeceemNVM::EEPROMGetSize()
status_t
BeceemNVM::EEPROMRead(unsigned int offset, unsigned int *pdwData)
BeceemNVM::EEPROMRead(uint32 offset, uint32 *pdwData)
{
// Read 4 bytes from EEPROM
// read 0x0f003020 until bit 2 of 0x0f003008 is set.
unsigned int regValue = 0;
uint32 regValue = 0;
BizarroReadRegister(EEPROM_SPI_Q_STATUS_REG,
sizeof(unsigned int), &regValue);
sizeof(uint32), &regValue);
unsigned int retries = 16;
uint32 retries = 16;
while (((regValue >> 2) & 1) == 0) {
retries--;
@@ -685,7 +685,7 @@ BeceemNVM::EEPROMRead(unsigned int offset, unsigned int *pdwData)
}
BizarroReadRegister(EEPROM_SPI_Q_STATUS_REG,
sizeof(unsigned int), &regValue);
sizeof(uint32), &regValue);
}
// wrm (0x0f003018, 0xNbXXXXXX)
@@ -697,11 +697,11 @@ BeceemNVM::EEPROMRead(unsigned int offset, unsigned int *pdwData)
offset |= 0x3b000000;
BizarroWriteRegister(EEPROM_CMDQ_SPI_REG, sizeof(unsigned int), &offset);
BizarroWriteRegister(EEPROM_CMDQ_SPI_REG, sizeof(uint32), &offset);
retries = 50;
BizarroReadRegister(EEPROM_SPI_Q_STATUS_REG, sizeof(unsigned int),
BizarroReadRegister(EEPROM_SPI_Q_STATUS_REG, sizeof(uint32),
&regValue);
while (((regValue >> 1) & 1) == 1) {
@@ -714,23 +714,23 @@ BeceemNVM::EEPROMRead(unsigned int offset, unsigned int *pdwData)
return B_ERROR;
}
BizarroReadRegister(EEPROM_SPI_Q_STATUS_REG, sizeof(unsigned int),
BizarroReadRegister(EEPROM_SPI_Q_STATUS_REG, sizeof(uint32),
&regValue);
}
BizarroReadRegister(EEPROM_READ_DATAQ_REG, sizeof(unsigned int), &regValue);
BizarroReadRegister(EEPROM_READ_DATAQ_REG, sizeof(uint32), &regValue);
unsigned int dwReadValue = regValue;
uint32 dwReadValue = regValue;
BizarroReadRegister(EEPROM_READ_DATAQ_REG, sizeof(unsigned int), &regValue);
BizarroReadRegister(EEPROM_READ_DATAQ_REG, sizeof(uint32), &regValue);
dwReadValue |= regValue << 8;
BizarroReadRegister(EEPROM_READ_DATAQ_REG, sizeof(unsigned int), &regValue);
BizarroReadRegister(EEPROM_READ_DATAQ_REG, sizeof(uint32), &regValue);
dwReadValue |= regValue << 16;
BizarroReadRegister(EEPROM_READ_DATAQ_REG, sizeof(unsigned int), &regValue);
BizarroReadRegister(EEPROM_READ_DATAQ_REG, sizeof(uint32), &regValue);
dwReadValue |= regValue << 24;
@@ -741,15 +741,15 @@ BeceemNVM::EEPROMRead(unsigned int offset, unsigned int *pdwData)
status_t
BeceemNVM::EEPROMBulkRead(unsigned int offset, size_t numBytes,
unsigned int* buffer)
BeceemNVM::EEPROMBulkRead(uint32 offset, size_t numBytes,
uint32* buffer)
{
unsigned int uiData[4] = {0};
unsigned int uiBytesRemaining = numBytes;
unsigned int uiIndex = 0;
uint32 uiData[4] = {0};
uint32 uiBytesRemaining = numBytes;
uint32 uiIndex = 0;
unsigned int uiTempOffset = 0;
unsigned int uiExtraBytes = 0;
uint32 uiTempOffset = 0;
uint32 uiExtraBytes = 0;
unsigned char* pcBuff = (unsigned char*)buffer;
TRACE("Debug: Reading %x bytes at offset %x.\n", numBytes, offset);
@@ -758,7 +758,7 @@ BeceemNVM::EEPROMBulkRead(unsigned int offset, size_t numBytes,
uiTempOffset = offset - (offset%16);
uiExtraBytes = offset - uiTempOffset;
EEPROMBulkRead(uiTempOffset, 16, (unsigned int*)&uiData[0]);
EEPROMBulkRead(uiTempOffset, 16, (uint32*)&uiData[0]);
if (uiBytesRemaining >= (16 - uiExtraBytes)) {
memcpy(buffer,
@@ -827,7 +827,7 @@ BeceemNVM::ValidateDSD(unsigned long hwParam)
/* Read the Length of structure */
unsigned short hwParamLen = 0;
NVMRead(dwReadValue, 2, (unsigned int*)&hwParamLen);
NVMRead(dwReadValue, 2, (uint32*)&hwParamLen);
hwParamLen = ntohs(hwParamLen);
/* Validate length */
@@ -846,7 +846,7 @@ BeceemNVM::ValidateDSD(unsigned long hwParam)
return B_ERROR;
}
NVMRead(dwReadValue, hwParamLen, (unsigned int*)puBuffer);
NVMRead(dwReadValue, hwParamLen, (uint32*)puBuffer);
// Populate allocated memory with string for checksum
unsigned short usChksmCalc = 0;
@@ -854,7 +854,7 @@ BeceemNVM::ValidateDSD(unsigned long hwParam)
// Perform checksum on values
unsigned short usChksmOrg = 0;
NVMRead(dwReadValue + hwParamLen, 2, (unsigned int*)&usChksmOrg);
NVMRead(dwReadValue + hwParamLen, 2, (uint32*)&usChksmOrg);
// Read what the device thinks the checksum should be
usChksmOrg = ntohs(usChksmOrg);
src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/BeceemNVM.h
+26 -26
View File
@@ -83,23 +83,23 @@ public:
status_t ValidateDSD(unsigned long hwParam);
int NVMRead(unsigned int offset, unsigned int size,
unsigned int* buffer);
int NVMWrite(unsigned int offset, unsigned int size,
unsigned int* buffer);
int NVMRead(uint32 offset, uint32 size,
uint32* buffer);
int NVMWrite(uint32 offset, uint32 size,
uint32* buffer);
// yuck. These are in a child class class
virtual status_t ReadRegister(unsigned int reg,
size_t size, uint32_t* buffer)
virtual status_t ReadRegister(uint32 reg,
size_t size, uint32* buffer)
{ return NULL; };
virtual status_t WriteRegister(unsigned int reg,
size_t size, uint32_t* buffer)
virtual status_t WriteRegister(uint32 reg,
size_t size, uint32* buffer)
{ return NULL; };
virtual status_t BizarroReadRegister(unsigned int reg,
size_t size, uint32_t* buffer)
virtual status_t BizarroReadRegister(uint32 reg,
size_t size, uint32* buffer)
{ return NULL; };
virtual status_t BizarroWriteRegister(unsigned int reg,
size_t size, uint32_t* buffer)
virtual status_t BizarroWriteRegister(uint32 reg,
size_t size, uint32* buffer)
{ return NULL; };
int bSelectedChip; // selected chip
@@ -109,30 +109,30 @@ private:
status_t NVMDetect();
status_t NVMFlush();
status_t NVMChipSelect(unsigned int offset);
status_t NVMChipSelect(uint32 offset);
status_t RestoreBlockProtect(unsigned long writestatus);
unsigned long DisableBlockProtect(unsigned int offset,
unsigned long DisableBlockProtect(uint32 offset,
size_t size);
int FlashGetBaseAddr();
unsigned long FlashReadID();
status_t FlashReadCS();
status_t FlashSectorErase(unsigned int addr,
unsigned int numOfSectors);
status_t FlashBulkRead(unsigned int offset,
unsigned int size, unsigned int* buffer);
status_t FlashBulkWrite(unsigned int offset,
unsigned int size, unsigned int* buffer);
status_t FlashSectorErase(uint32 addr,
uint32 numOfSectors);
status_t FlashBulkRead(uint32 offset,
uint32 size, uint32* buffer);
status_t FlashBulkWrite(uint32 offset,
uint32 size, uint32* buffer);
status_t FlashCSFlip(PFLASH_CS_INFO FlashCSInfo);
status_t FlashCSDump(PFLASH_CS_INFO FlashCSInfo);
unsigned int EEPROMGetSize();
unsigned int FlashGetSize();
uint32 EEPROMGetSize();
uint32 FlashGetSize();
status_t EEPROMRead(unsigned int offset,
unsigned int *pdwData);
status_t EEPROMBulkRead( unsigned int offset,
size_t numBytes, unsigned int* buffer);
status_t EEPROMRead(uint32 offset,
uint32 *pdwData);
status_t EEPROMBulkRead( uint32 offset,
size_t numBytes, uint32* buffer);
};
src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/DeviceStruct.h
+72 -72
View File
@@ -97,7 +97,7 @@ typedef struct _VENDORCFG
# Ack generation
# Version 50 - Added flag for handling partial nacking of PDUs, and retxing
# only nacked blocks */
unsigned int m_u32CfgVersion;
uint32 m_u32CfgVersion;
/*
Scanning Parameters
@@ -105,19 +105,19 @@ typedef struct _VENDORCFG
Or use: 2336, 2345, 2354, 2367.5, 2385.5
Choosing the center frequency non-zero will
disable scanning! */
unsigned int m_u32CenterFrequency;
unsigned int m_u32BandAScan;
unsigned int m_u32BandBScan;
unsigned int m_u32BandCScan;
uint32 m_u32CenterFrequency;
uint32 m_u32BandAScan;
uint32 m_u32BandBScan;
uint32 m_u32BandCScan;
// QoS Params
unsigned int m_u32minGrantsize; // size of minimum grant is 0 or 6
unsigned int m_u32PHSEnable;
uint32 m_u32minGrantsize; // size of minimum grant is 0 or 6
uint32 m_u32PHSEnable;
// HO Params
unsigned int m_u32HoEnable;
unsigned int m_u32HoReserved1;
unsigned int m_u32HoReserved2;
uint32 m_u32HoEnable;
uint32 m_u32HoReserved1;
uint32 m_u32HoReserved2;
/*
MIMO Enable ==> 0xddccbbaa
@@ -127,7 +127,7 @@ typedef struct _VENDORCFG
0xdd Reserved
0x0101 => Enables DL MIMO and UL CSM
0x010101 =? Enable DL MIMO, UL CSM, and disable MIMO B in DL */
unsigned int m_u32MimoEnable;
uint32 m_u32MimoEnable;
/*
Security Parameters
@@ -136,20 +136,20 @@ typedef struct _VENDORCFG
bit 2 = Enable domain restriction for security
bit 3 = Disable encryption support
bit[31:4] = Unused. */
unsigned int m_u32SecurityEnable;
uint32 m_u32SecurityEnable;
/*
PowerSaving enable
bit 1 = 1 Idlemode enable
bit 2 = 1 Sleepmode Enable */
unsigned int m_u32PowerSavingModesEnable;
uint32 m_u32PowerSavingModesEnable;
/*
PowerSaving Mode Options
bit 0 = 1: CPE mode - to keep pcmcia if alive;
bit 1 = 1: CINR reporing in Idlemode Msg
bit 2 = 1: Default PSC Enable in sleepmode */
unsigned int m_u32PowerSavingModeOptions;
uint32 m_u32PowerSavingModeOptions;
/*
ARQ Enable ==> 0xddccbbaa
@@ -159,7 +159,7 @@ typedef struct _VENDORCFG
cc => 0x01 Enable ARQ FB BW req enh
dd => 0th bit Disable ARQ Cut thru for Ack Generation
dd => 1st bit enables handling of partial nacking of PDUs, and retxing */
unsigned int m_u32ArqEnable;
uint32 m_u32ArqEnable;
/*
HARQ Enable ==> 0xddccbbaa
@@ -175,28 +175,28 @@ typedef struct _VENDORCFG
Enables out of deliver on the non-ARQ rx ERTPS HARQ connections
Eg. 0x0501 => Enables HARQ on Management and HARQ on Transport Connections
Enables out of deliver on the non-ARQ RX HARQ connections */
unsigned int m_u32HarqEnable;
uint32 m_u32HarqEnable;
// EEPROM Param Location
unsigned int m_u32EEPROMFlag;
uint32 m_u32EEPROMFlag;
/*
Customize
Normal Mode should be set to (0x00000100)
Set bit 0 for using D5 CQICH IE (WiBro NW)
Bit 26 should be set to disable the BEU */
unsigned int m_u32Customize;
uint32 m_u32Customize;
/*
Config Bandwidth
Should be in Hz i.e. 8750000, 10000000 */
unsigned int m_u32ConfigBW;
uint32 m_u32ConfigBW;
/*
Shutdown Timer
number of frames (5 ms)
ShutDown Timer Value = 0x7fffffff */
unsigned int m_u32ShutDownTimer;
uint32 m_u32ShutDownTimer;
/*
Radio Parameter
@@ -217,7 +217,7 @@ typedef struct _VENDORCFG
# 3.5GHz MS120 single band unit needs 0x42
# 2.3G and/or 3.5G BCS200 unit needs 0x40022
# 2.5G and/or 3.5G BCS200 unit needs 0x40032 */
unsigned int m_u32RadioParameter;
uint32 m_u32RadioParameter;
/*
PhyParameter1 e.g. 0xccccbbaa
@@ -226,7 +226,7 @@ typedef struct _VENDORCFG
aa = [7:0] Number of UL symbols
Special value of 0xFFFFFFFF indicates use of embedded logic
PhyParameter1 = 0xFFFFFFFF */
unsigned int m_u32PhyParameter1;
uint32 m_u32PhyParameter1;
/*
PhyParameter2
@@ -234,11 +234,11 @@ typedef struct _VENDORCFG
If set to 1, note the BTS Link Adaptation tables may need change
[15:8] Backoff in 0.25dBm steps in Transmit power to be
applied for an uncalibrated unit */
unsigned int m_u32PhyParameter2;
uint32 m_u32PhyParameter2;
/*
PhyParameter3 = 0x0 */
unsigned int m_u32PhyParameter3;
uint32 m_u32PhyParameter3;
/*
TestOptions
@@ -271,14 +271,14 @@ typedef struct _VENDORCFG
-#define ENABLE__BF_WA 0x20000000
-#define ENABLE_BR_PWR_INCR_AND_IGNORE_PC_IE_OUT_DYNAMIC_RNG 0x40000000
-#define ENABLE_BR_CODE_TIMEOUT_PWR_ADJ_PDUS 0x80000000*/
unsigned int m_u32TestOptions;
uint32 m_u32TestOptions;
/*
Max MAC Data per Frame to be sent in REG-REQ */
unsigned int m_u32MaxMACDataperDLFrame;
unsigned int m_u32MaxMACDataperULFrame;
uint32 m_u32MaxMACDataperDLFrame;
uint32 m_u32MaxMACDataperULFrame;
unsigned int m_u32Corr2MacFlags;
uint32 m_u32Corr2MacFlags;
/*
HostDrvrConfig1/HostDrvrConfig2/HostDrvrConfig3
@@ -287,9 +287,9 @@ typedef struct _VENDORCFG
ON State (This makes sure that the LED is ON till a state is achieved)
Blink State (This makes sure that the LED Keeps Blinking till a state is
achieved e.g. firmware download state)*/
unsigned int HostDrvrConfig1;
unsigned int HostDrvrConfig2;
unsigned int HostDrvrConfig3;
uint32 HostDrvrConfig1;
uint32 HostDrvrConfig2;
uint32 HostDrvrConfig3;
/*
HostDrvrConfig4/HostDrvrConfig5
@@ -300,8 +300,8 @@ typedef struct _VENDORCFG
HostDrvrConfig5 [31:0]
To set WiMAX Trigger Threshold for the type
selected in HostDrvrConfig4 */
unsigned int HostDrvrConfig4;
unsigned int HostDrvrConfig5;
uint32 HostDrvrConfig4;
uint32 HostDrvrConfig5;
/*
HostDrvrConfig6:
@@ -322,13 +322,13 @@ typedef struct _VENDORCFG
DEVICE_POWERSAVE_MODE_AS_PMU_SHUTDOWN = 0x2
Bit[15] Idlemode Auto correct mode.
0-Enable, 1- Disable. */
unsigned int HostDrvrConfig6;
uint32 HostDrvrConfig6;
/*
Segmented PSUC
Option to enable support of Segmented PUSC.
If set to 0, only full reuse profiles are supported */
unsigned int m_u32SegmentedPUSCenable;
uint32 m_u32SegmentedPUSCenable;
/*
BAMC Related Parameters
@@ -339,7 +339,7 @@ typedef struct _VENDORCFG
Bit[16..31] Band AMC Data configuration:
Bit 16 = 1 Band AMC 2x3 support.
Bit 0 is effective only if bit 16 is set. */
unsigned int m_u32BandAMCEnable;
uint32 m_u32BandAMCEnable;
} VENDORCFG, *PSVENDORCFG;
@@ -384,69 +384,69 @@ typedef struct _GPIO_LED_MAP
typedef struct _FLASH_CS_INFO
{
uint32_t MagicNumber;
uint32 MagicNumber;
// 0xBECE - F1A5 for FLAS(H)
uint32_t FlashLayoutVersion;
uint32 FlashLayoutVersion;
// Flash layout version
uint32_t ISOImageVersion;
uint32 ISOImageVersion;
// ISO Image / Format / Eng version
uint32_t SCSIFirmwareVersion;
uint32 SCSIFirmwareVersion;
// SCSI Firmware Version
uint32_t OffsetFromZeroForPart1ISOImage;
uint32 OffsetFromZeroForPart1ISOImage;
// Normally 0
uint32_t OffsetFromZeroForScsiFirmware;
uint32 OffsetFromZeroForScsiFirmware;
// Normally 12MB
uint32_t SizeOfScsiFirmware;
uint32 SizeOfScsiFirmware;
// Size of firmware, varies
uint32_t OffsetFromZeroForPart2ISOImage;
uint32 OffsetFromZeroForPart2ISOImage;
// 1st word offset 12MB + sizeofScsiFirmware
uint32_t OffsetFromZeroForCalibrationStart;
uint32_t OffsetFromZeroForCalibrationEnd;
uint32 OffsetFromZeroForCalibrationStart;
uint32 OffsetFromZeroForCalibrationEnd;
uint32_t OffsetFromZeroForVSAStart;
uint32_t OffsetFromZeroForVSAEnd;
uint32 OffsetFromZeroForVSAStart;
uint32 OffsetFromZeroForVSAEnd;
// VSA0 offsets
uint32_t OffsetFromZeroForControlSectionStart;
uint32_t OffsetFromZeroForControlSectionData;
uint32 OffsetFromZeroForControlSectionStart;
uint32 OffsetFromZeroForControlSectionData;
// Control Section offsets
uint32_t CDLessInactivityTimeout;
uint32 CDLessInactivityTimeout;
// NO Data Activity timeout to switch from MSC to NW Mode
uint32_t NewImageSignature;
uint32 NewImageSignature;
// New ISO Image Signature
uint32_t FlashSectorSizeSig;
uint32 FlashSectorSizeSig;
// Signature to validate the sector size.
uint32_t FlashSectorSize;
uint32 FlashSectorSize;
// Sector Size
uint32_t FlashWriteSupportSize;
uint32 FlashWriteSupportSize;
// Write Size Support
uint32_t TotalFlashSize;
uint32 TotalFlashSize;
// Total Flash Size
uint32_t FlashBaseAddr;
uint32 FlashBaseAddr;
// Flash Base Address for offset specified
uint32_t FlashPartMaxSize;
uint32 FlashPartMaxSize;
// Flash Part Max Size
uint32_t IsCDLessDeviceBootSig;
uint32 IsCDLessDeviceBootSig;
// Is CDLess or Flash Bootloader
uint32_t MassStorageTimeout;
uint32 MassStorageTimeout;
// MSC Timeout after reset to switch from MSC to NW Mode
} FLASH_CS_INFO, *PFLASH_CS_INFO;
@@ -455,15 +455,15 @@ struct WIMAX_DEVICE
{
VENDORCFG vendorcfg;
// we memcpy the vendor cfg here
unsigned int syscfgBefFw;
uint32 syscfgBefFw;
// SYS_CFG before firmware
bool CPUFlashBoot;
// Reverse MIPS
unsigned int deviceChipID;
uint32 deviceChipID;
// Beceem interface chip model
volatile bool driverHalt;
// gets set to true when driver is being shutdown
volatile unsigned int driverState;
volatile uint32 driverState;
// Driver state, defined in Driver.h
volatile bool driverDDRinit;
// has the DDR memory been initialized?
@@ -476,16 +476,16 @@ volatile bool driverFwPushed;
thread_id LEDThreadID;
// Thread ID of LED state handler
unsigned int nvmType;
uint32 nvmType;
// NVM Type (FLASH|EEPROM|UNKNOWN)
unsigned int nvmDSDSize;
uint32 nvmDSDSize;
// NVM DSD Size
unsigned int nvmVerMajor;
uint32 nvmVerMajor;
// NVM Major
unsigned int nvmVerMinor;
uint32 nvmVerMinor;
// NVM Minor
volatile uint32_t nvmFlashBaseAddr;
volatile uint32 nvmFlashBaseAddr;
// NVM Flash base address
unsigned long nvmFlashCalStart;
// NVM Flash calibrated start
@@ -500,16 +500,16 @@ volatile bool nvmFlashCSDone;
volatile bool nvmFlashRaw;
// Do we need raw access at the moment?
unsigned int nvmFlashMajor;
uint32 nvmFlashMajor;
// NVM Flash layout major version
unsigned int nvmFlashMinor;
uint32 nvmFlashMinor;
// NVM Flash layout major version
unsigned int hwParamPtr;
uint32 hwParamPtr;
// Pointer to the NVM Param section address
unsigned char gpioInfo[32];
// Stored GPIO information
unsigned int gpioBitMap;
uint32 gpioBitMap;
// GPIO LED bitmap
};
src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/util.cpp
+5 -5
View File
@@ -10,23 +10,23 @@
#include "util.h"
void
convertEndian(bool write, unsigned int uiByteCount, unsigned int* buffer)
convertEndian(bool write, uint32 uiByteCount, uint32* buffer)
{
unsigned int uiIndex = 0;
uint32 uiIndex = 0;
if( write == true ) {
for(uiIndex = 0; uiIndex < (uiByteCount/sizeof(unsigned int)); uiIndex++) {
for(uiIndex = 0; uiIndex < (uiByteCount/sizeof(uint32)); uiIndex++) {
buffer[uiIndex] = htonl(buffer[uiIndex]);
}
} else {
for(uiIndex = 0; uiIndex < (uiByteCount/sizeof(unsigned int)); uiIndex++) {
for(uiIndex = 0; uiIndex < (uiByteCount/sizeof(uint32)); uiIndex++) {
buffer[uiIndex] = ntohl(buffer[uiIndex]);
}
}
}
uint16_t
CalculateHWChecksum(uint8_t* pu8Buffer, uint32_t u32Size)
CalculateHWChecksum(uint8_t* pu8Buffer, uint32 u32Size)
{
uint16_t u16CheckSum=0;
while(u32Size--) {
src/add-ons/kernel/drivers/network/wwan/usb_beceemwmx/util.h
+2 -2
View File
@@ -7,6 +7,6 @@
#include "Driver.h"
void convertEndian(bool write, unsigned int uiByteCount, unsigned int* buffer);
uint16_t CalculateHWChecksum(uint8_t* pu8Buffer, uint32_t u32Size);
void convertEndian(bool write, uint32 uiByteCount, uint32* buffer);
uint16_t CalculateHWChecksum(uint8_t* pu8Buffer, uint32 u32Size);