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fixed NV31 pixelPLL programming (hack: unknown register)

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@5828 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2003-12-30 13:41:29 +00:00
parent eeaae9ecc4
commit 68efb73adf
3 changed files with 45 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files
headers/private/graphics/nvidia/DriverInterface.h
+9 -4
View File
@@ -5,7 +5,7 @@
Other authors:
Mark Watson;
Apsed;
Rudolf Cornelissen 10/2002-4/2003.
Rudolf Cornelissen 10/2002-12/2003.
*/
#ifndef DRIVERINTERFACE_H
@@ -200,7 +200,9 @@ typedef struct {
CH7006,
CH7007,
SAA7102,
SAA7104,
SAA7108,
SAA7114,
BT868,
BT869,
CX25870,
@@ -249,13 +251,16 @@ typedef struct {
uint32 memory_size; /* memory (Mb) */
} ps;
/*mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb)*/
/* mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb) */
uint8 rom_mirror[32768];
/*CRTC delay -> used in timing for MAVEN, depending on which CRTC is driving it*/
/* CRTC delay -> used in timing for MAVEN, depending on which CRTC is driving it */
uint8 crtc_delay;
/* apsed: some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */
/* NV31 (FX5600) tweak to get pixelPLL going (unknown register) */
uint16 pixpll_vco_div2;
/* apsed: some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */
settings settings;
struct
src/add-ons/accelerants/nvidia/engine/nv_dac.c
+10 -2
View File
@@ -1,6 +1,6 @@
/* program the DAC */
/* Author:
Rudolf Cornelissen 7/2003
Rudolf Cornelissen 12/2003
*/
#define MODULE_BIT 0x00010000
@@ -234,6 +234,9 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
/* check if this is within range of the VCO specs */
if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco))
{
/* NV31 (FX5600) tweak (missing register for 2nd VCO postscaler) */
f_vco /= si->pixpll_vco_div2;
/* iterate trough all valid reference-frequency postscaler settings */
for (m = 7; m <= 14; m++)
{
@@ -246,7 +249,9 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
if ((n < 1) || (n > 255)) continue;
/* find error in frequency this setting gives */
error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p));
/* si->pixpll_vco_div2 below is NV31 (FX5600) tweak (missing register) */
error =
fabs((req_pclk / si->pixpll_vco_div2) - (((si->ps.f_ref / m) * n) / p));
/* note the setting if best yet */
if (error < error_best)
@@ -267,6 +272,9 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
/* log the VCO frequency found */
f_vco = ((si->ps.f_ref / m) * n);
/* NV31 (FX5600) tweak (missing register for 2nd VCO postscaler) */
f_vco *= si->pixpll_vco_div2;
LOG(2,("DAC: pix VCO frequency found %fMhz\n", f_vco));
/* return the results */
src/add-ons/accelerants/nvidia/engine/nv_general.c
+26 -1
View File
@@ -81,7 +81,7 @@ status_t nv_general_powerup()
{
status_t status;
LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.07 running.\n"));
LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.08-1 running.\n"));
/* preset no laptop */
si->ps.laptop = false;
@@ -819,6 +819,31 @@ status_t nv_general_bios_to_powergraphics()
NV_REG32(NV32_2FUNCSEL) &= ~0x00001000;
}
//fixme: FX5600 cards have a second postdivider for the pixel PLL VCO.
//find it and program it, instead of relying on the cards BIOS...
//BIOS tested: FX5600 BIOS V4.31.20.38.00
/* non-NV31 cards have no second postdivider */
si->pixpll_vco_div2 = 1;
if (si->ps.card_type == NV31)
{
/* only reading b0-7, as the rest seems to be write-only */
uint16 v_display = CRTCR(VDISPE) + 1;
if ((!(CRTCR(REPAINT1) & 0x01)) &&
((v_display == (600 & 0xff)) || (v_display == (1200 & 0xff))))
{
/* if a VESA mode was already set, and the mode was 800x600 or 1600x1200
* the BIOS programs the second VCO postdivider to 5 */
si->pixpll_vco_div2 = 5;
LOG(2, ("INIT: assuming NV31 pixPLL second VCO postdivider is set to 5!\n"));
}
else
{
/* else the BIOS programs the second VCO postdivider to 4 */
si->pixpll_vco_div2 = 4;
LOG(2, ("INIT: assuming NV31 pixPLL second VCO postdiviver is set to 4!\n"));
}
}
/* enable 'enhanced mode', enable Vsync & Hsync,
* set DAC palette to 8-bit width, disable large screen */
CRTCW(REPAINT1, 0x04);