arm64: Discover PCI from ACPI.
Change-Id: I2e40c8a531f319cce25363ab83d4d0fe9f8702d2 Reviewed-on: https://review.haiku-os.org/c/haiku/+/5274 Tested-by: Commit checker robot <[email protected]> Reviewed-by: David Karoly <[email protected]> Reviewed-by: Fredrik Holmqvist <[email protected]>
This commit is contained in:
milek7
@@ -10,6 +10,7 @@
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#define ACPI_RSDT_SIGNATURE "RSDT"
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#define ACPI_XSDT_SIGNATURE "XSDT"
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#define ACPI_MADT_SIGNATURE "APIC"
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#define ACPI_MCFG_SIGNATURE "MCFG"
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#define ACPI_SPCR_SIGNATURE "SPCR"
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#define ACPI_LOCAL_APIC_ENABLED 0x01
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@@ -248,6 +249,21 @@ typedef struct acpi_gas {
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uint64 address;
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} _PACKED acpi_gas;
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typedef struct acpi_mcfg
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{
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acpi_descriptor_header header;
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uint8 reserved[8];
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} _PACKED acpi_mcfg;
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typedef struct acpi_mcfg_allocation
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{
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uint64 address;
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uint16 pci_segment;
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uint8 start_bus_number;
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uint8 end_bus_number;
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uint32 reserved;
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} _PACKED acpi_mcfg_allocation;
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typedef struct acpi_spcr {
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acpi_descriptor_header header;
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uint32 interface_type;
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@@ -293,6 +309,92 @@ typedef struct acpi_resource_fixed_memory32 {
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uint32 address_length;
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} _PACKED acpi_resource_fixed_memory32;
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typedef struct acpi_memory_attribute {
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uint8 write_protect;
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uint8 caching;
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uint8 range_type;
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uint8 translation;
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} _PACKED acpi_memory_attribute;
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typedef struct acpi_io_attribute {
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uint8 range_type;
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uint8 translation;
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uint8 translation_type;
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uint8 reserved1;
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} _PACKED acpi_io_attribute;
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typedef union acpi_resource_attribute {
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acpi_memory_attribute mem;
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acpi_io_attribute io;
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uint8 type_specific;
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} acpi_resource_attribute;
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typedef struct acpi_address16_attribute {
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uint16 granularity;
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uint16 minimum;
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uint16 maximum;
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uint16 translation_offset;
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uint16 address_length;
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} _PACKED acpi_address16_attribute;
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typedef struct acpi_address32_attribute {
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uint32 granularity;
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uint32 minimum;
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uint32 maximum;
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uint32 translation_offset;
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uint32 address_length;
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} _PACKED acpi_address32_attribute;
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typedef struct acpi_address64_attribute {
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uint64 granularity;
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uint64 minimum;
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uint64 maximum;
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uint64 translation_offset;
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uint64 address_length;
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} _PACKED acpi_address64_attribute;
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typedef struct acpi_resource_address {
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uint8 resource_type;
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uint8 producer_consumer;
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uint8 decode;
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uint8 minAddress_fixed;
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uint8 maxAddress_fixed;
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acpi_resource_attribute info;
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} _PACKED acpi_resource_address;
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typedef struct acpi_resource_address16 {
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uint8 resource_type;
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uint8 producer_consumer;
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uint8 decode;
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uint8 minAddress_fixed;
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uint8 maxAddress_fixed;
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acpi_resource_attribute info;
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acpi_address16_attribute address;
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acpi_resource_source resource_source;
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} _PACKED acpi_resource_address16;
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typedef struct acpi_resource_address32 {
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uint8 resource_type;
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uint8 producer_consumer;
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uint8 decode;
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uint8 minAddress_fixed;
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uint8 maxAddress_fixed;
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acpi_resource_attribute info;
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acpi_address32_attribute address;
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acpi_resource_source resource_source;
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} _PACKED acpi_resource_address32;
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typedef struct acpi_resource_address64 {
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uint8 resource_type;
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uint8 producer_consumer;
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uint8 decode;
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uint8 minAddress_fixed;
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uint8 maxAddress_fixed;
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acpi_resource_attribute info;
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acpi_address64_attribute address;
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acpi_resource_source resource_source;
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} _PACKED acpi_resource_address64;
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typedef struct acpi_resource_extended_irq {
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uint8 producer_consumer;
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uint8 triggering;
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@@ -306,7 +408,12 @@ typedef struct acpi_resource_extended_irq {
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typedef union acpi_resource_data {
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acpi_resource_fixed_memory32 fixed_memory32;
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acpi_resource_address16 address16;
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acpi_resource_address32 address32;
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acpi_resource_address64 address64;
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acpi_resource_extended_irq extended_irq;
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acpi_resource_address address;
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} acpi_resource_data;
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typedef struct acpi_resource {
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@@ -317,6 +424,9 @@ typedef struct acpi_resource {
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enum {
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ACPI_RESOURCE_TYPE_FIXED_MEMORY32 = 10,
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ACPI_RESOURCE_TYPE_ADDRESS16 = 11,
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ACPI_RESOURCE_TYPE_ADDRESS32 = 12,
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ACPI_RESOURCE_TYPE_ADDRESS64 = 13,
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ACPI_RESOURCE_TYPE_EXTENDED_IRQ = 15,
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};
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@@ -1,10 +1,15 @@
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SubDir HAIKU_TOP src add-ons kernel bus_managers pci arch $(TARGET_ARCH) ;
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SubDirHdrs [ FDirName $(SUBDIR) $(DOTDOT) $(DOTDOT) ] ;
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UsePrivateKernelHeaders ;
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UsePrivateHeaders kernel [ FDirName kernel arch $(TARGET_ARCH) ]
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[ FDirName kernel boot platform $(HAIKU_BOOT_PLATFORM) ] ;
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SEARCH_SOURCE += [ FDirName $(SUBDIR) $(DOTDOT) generic ] ;
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KernelStaticLibrary pci_arch_bus_manager :
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pci_controller.cpp
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pci_io.c
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pci_io.cpp
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pci_ecam.cpp
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;
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@@ -1,27 +0,0 @@
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/*
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* Copyright 2009, Haiku Inc.
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* Distributed under the terms of the MIT License.
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*/
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#include "pci_controller.h"
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//#include <arch_platform.h>
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#include "pci_private.h"
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status_t
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pci_controller_init(void)
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{
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/* no support yet */
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#warning ARM:WRITEME
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return B_OK;
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}
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phys_addr_t
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pci_ram_address(phys_addr_t physical_address_in_system_memory)
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{
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return physical_address_in_system_memory;
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}
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@@ -1,61 +0,0 @@
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/*
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* Copyright 2009, Haiku Inc.
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* Distributed under the terms of the MIT License.
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*/
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#include "pci_io.h"
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#include "pci_private.h"
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#warning ARM:WRITEME
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status_t
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pci_io_init()
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{
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return B_OK;
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}
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uint8
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pci_read_io_8(int mapped_io_addr)
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{
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/* NOT IMPLEMENTED */
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return 0;
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}
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void
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pci_write_io_8(int mapped_io_addr, uint8 value)
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{
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/* NOT IMPLEMENTED */
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}
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uint16
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pci_read_io_16(int mapped_io_addr)
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{
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/* NOT IMPLEMENTED */
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return 0;
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}
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void
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pci_write_io_16(int mapped_io_addr, uint16 value)
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{
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/* NOT IMPLEMENTED */
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}
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uint32
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pci_read_io_32(int mapped_io_addr)
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{
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/* NOT IMPLEMENTED */
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return 0;
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}
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void
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pci_write_io_32(int mapped_io_addr, uint32 value)
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{
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/* NOT IMPLEMENTED */
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}
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@@ -1,12 +0,0 @@
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/*
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* Copyright 2009, Haiku Inc.
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* All rights reserved. Distributed under the terms of the MIT License.
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*/
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#ifndef PCI_BUS_MANAGER_ARM_IO_H
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#define PCI_BUS_MANAGER_ARM_IO_H
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#include <SupportDefs.h>
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#endif // PCI_BUS_MANAGER_ARM_IO_H
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@@ -0,0 +1,208 @@
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/*
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* Copyright 2009-2022, Haiku Inc.
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* Distributed under the terms of the MIT License.
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*/
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#include "pci_controller.h"
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#include <kernel/debug.h>
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#include <util/Vector.h>
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#include <AutoDeleterDrivers.h>
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#include "pci_private.h"
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#include <ACPI.h> // module
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#include <acpi.h>
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addr_t gPCIeBase;
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uint8 gStartBusNumber;
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uint8 gEndBusNumber;
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addr_t gPCIioBase;
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extern pci_controller pci_controller_ecam;
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enum RangeType
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{
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RANGE_IO,
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RANGE_MEM
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};
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struct PciRange
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{
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RangeType type;
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phys_addr_t hostAddr;
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phys_addr_t pciAddr;
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size_t length;
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};
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static Vector<PciRange> *sRanges;
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template<typename T>
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acpi_address64_attribute AcpiCopyAddressAttr(const T &src)
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{
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acpi_address64_attribute dst;
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dst.granularity = src.granularity;
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dst.minimum = src.minimum;
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dst.maximum = src.maximum;
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dst.translation_offset = src.translation_offset;
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dst.address_length = src.address_length;
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return dst;
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}
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static acpi_status
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AcpiCrsScanCallback(acpi_resource *res, void *context)
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{
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Vector<PciRange> &ranges = *(Vector<PciRange>*)context;
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acpi_address64_attribute address;
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if (res->type == ACPI_RESOURCE_TYPE_ADDRESS16)
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address = AcpiCopyAddressAttr(res->data.address16.address);
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else if (res->type == ACPI_RESOURCE_TYPE_ADDRESS32)
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address = AcpiCopyAddressAttr(res->data.address32.address);
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else if (res->type == ACPI_RESOURCE_TYPE_ADDRESS64)
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address = AcpiCopyAddressAttr(res->data.address64.address);
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else
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return B_OK;
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acpi_resource_address &common = res->data.address;
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if (common.resource_type != 0 && common.resource_type != 1)
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return B_OK;
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ASSERT(address.minimum + address.address_length - 1 == address.maximum);
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PciRange range;
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range.type = (common.resource_type == 0 ? RANGE_MEM : RANGE_IO);
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range.hostAddr = address.minimum + address.translation_offset;
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range.pciAddr = address.minimum;
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range.length = address.address_length;
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ranges.PushBack(range);
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return B_OK;
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}
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status_t
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pci_controller_init(void)
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{
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if (gPCIRootNode == NULL)
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return B_DEV_NOT_READY;
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dprintf("PCI: pci_controller_init\n");
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DeviceNodePutter<&gDeviceManager>
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parent(gDeviceManager->get_parent_node(gPCIRootNode));
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if (parent.Get() == NULL)
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return B_ERROR;
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const char *bus;
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if (gDeviceManager->get_attr_string(parent.Get(), B_DEVICE_BUS, &bus, false) < B_OK)
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return B_ERROR;
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if (strcmp(bus, "acpi") == 0) {
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dprintf("initialize PCI controller from ACPI\n");
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status_t res;
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acpi_module_info *acpiModule;
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acpi_device_module_info *acpiDeviceModule;
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acpi_device acpiDevice;
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res = get_module(B_ACPI_MODULE_NAME, (module_info**)&acpiModule);
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if (res != B_OK)
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return B_ERROR;
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acpi_mcfg *mcfg;
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res = acpiModule->get_table(ACPI_MCFG_SIGNATURE, 0, (void**)&mcfg);
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if (res != B_OK)
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return B_ERROR;
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res = gDeviceManager->get_driver(parent.Get(),
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(driver_module_info**)&acpiDeviceModule, (void**)&acpiDevice);
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if (res != B_OK)
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return B_ERROR;
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sRanges = new Vector<PciRange>();
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acpi_status acpi_res = acpiDeviceModule->walk_resources(acpiDevice,
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(char *)"_CRS", AcpiCrsScanCallback, sRanges);
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if (acpi_res != 0)
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return B_ERROR;
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for (Vector<PciRange>::Iterator it = sRanges->Begin(); it != sRanges->End(); it++) {
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if (it->type != RANGE_IO)
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continue;
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if (gPCIioBase != 0) {
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dprintf("PCI: multiple io ranges not supported!");
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continue;
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}
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area_id area = map_physical_memory("pci io",
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it->hostAddr, it->length, B_ANY_KERNEL_ADDRESS,
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B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void **)&gPCIioBase);
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if (area < 0)
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return B_ERROR;
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}
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acpi_mcfg_allocation *end = (acpi_mcfg_allocation *) ((char*)mcfg + mcfg->header.length);
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acpi_mcfg_allocation *alloc = (acpi_mcfg_allocation *) (mcfg + 1);
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if (alloc + 1 != end)
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dprintf("PCI: multiple host bridges not supported!");
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for (; alloc < end; alloc++) {
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dprintf("PCI: mechanism addr: %" B_PRIx64 ", seg: %x, start: %x, end: %x\n",
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alloc->address, alloc->pci_segment, alloc->start_bus_number, alloc->end_bus_number);
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if (alloc->pci_segment != 0) {
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dprintf("PCI: multiple segments not supported!");
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continue;
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}
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gStartBusNumber = alloc->start_bus_number;
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gEndBusNumber = alloc->end_bus_number;
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area_id area = map_physical_memory("pci config",
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alloc->address, (gEndBusNumber - gStartBusNumber + 1) << 20, B_ANY_KERNEL_ADDRESS,
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B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void **)&gPCIeBase);
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if (area < 0)
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break;
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dprintf("PCI: ecam controller found\n");
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return pci_controller_add(&pci_controller_ecam, NULL);
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}
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}
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return B_ERROR;
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}
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phys_addr_t
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pci_ram_address(phys_addr_t addr)
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{
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for (Vector<PciRange>::Iterator it = sRanges->Begin(); it != sRanges->End(); it++) {
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if (addr >= it->pciAddr && addr < it->pciAddr + it->length) {
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phys_addr_t result = addr - it->pciAddr;
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if (it->type != RANGE_IO)
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result += it->hostAddr;
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return result;
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}
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}
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dprintf("PCI: requested translation of invalid address %" B_PRIxPHYSADDR "\n", addr);
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return 0;
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}
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@@ -0,0 +1,112 @@
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/*
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* Copyright 2009-2022, Haiku Inc.
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* Distributed under the terms of the MIT License.
|
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*/
|
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|
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#include "pci_controller.h"
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#include <kernel/debug.h>
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extern addr_t gPCIeBase;
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extern uint8 gStartBusNumber;
|
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extern uint8 gEndBusNumber;
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#define PCIE_VADDR(base, bus, slot, func, reg) \
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((base) + ((((bus) & 0xff) << 20) | (((slot) & 0x1f) << 15) \
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| (((func) & 0x7) << 12) | ((reg) & 0xfff)))
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static status_t
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read_pci_config(void *cookie, uint8 bus, uint8 device, uint8 function,
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uint16 offset, uint8 size, uint32 *value)
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{
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if (!(bus >= gStartBusNumber && bus <= gEndBusNumber))
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return B_ERROR;
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status_t status = B_OK;
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addr_t address = PCIE_VADDR(gPCIeBase, bus - gStartBusNumber, device, function, offset);
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switch (size) {
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case 1:
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*value = *(uint8*)address;
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break;
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case 2:
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*value = *(uint16*)address;
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break;
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case 4:
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*value = *(uint32*)address;
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break;
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default:
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status = B_ERROR;
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break;
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}
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return status;
|
||||
}
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||||
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static status_t
|
||||
write_pci_config(void *cookie, uint8 bus, uint8 device, uint8 function,
|
||||
uint16 offset, uint8 size, uint32 value)
|
||||
{
|
||||
if (!(bus >= gStartBusNumber && bus <= gEndBusNumber))
|
||||
return B_ERROR;
|
||||
|
||||
status_t status = B_OK;
|
||||
|
||||
addr_t address = PCIE_VADDR(gPCIeBase, bus - gStartBusNumber, device, function, offset);
|
||||
switch (size) {
|
||||
case 1:
|
||||
*(uint8*)address = value;
|
||||
break;
|
||||
case 2:
|
||||
*(uint16*)address = value;
|
||||
break;
|
||||
case 4:
|
||||
*(uint32*)address = value;
|
||||
break;
|
||||
default:
|
||||
status = B_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
static status_t
|
||||
get_max_bus_devices(void *cookie, int32 *count)
|
||||
{
|
||||
*count = 32;
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
|
||||
static status_t
|
||||
read_pci_irq(void *cookie, uint8 bus, uint8 device, uint8 function, uint8 pin,
|
||||
uint8 *irq)
|
||||
{
|
||||
dprintf("read_pci_irq\n");
|
||||
return B_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
|
||||
static status_t
|
||||
write_pci_irq(void *cookie, uint8 bus, uint8 device, uint8 function, uint8 pin,
|
||||
uint8 irq)
|
||||
{
|
||||
dprintf("write_pci_irq\n");
|
||||
return B_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
|
||||
pci_controller pci_controller_ecam =
|
||||
{
|
||||
read_pci_config,
|
||||
write_pci_config,
|
||||
get_max_bus_devices,
|
||||
read_pci_irq,
|
||||
write_pci_irq,
|
||||
};
|
||||
@@ -0,0 +1,80 @@
|
||||
/*
|
||||
* Copyright 2022, Haiku Inc.
|
||||
* Distributed under the terms of the MIT License.
|
||||
*/
|
||||
|
||||
|
||||
#include <SupportDefs.h>
|
||||
|
||||
#include "pci_private.h"
|
||||
|
||||
//#define TRACE_PCI_IO
|
||||
#ifdef TRACE_PCI_IO
|
||||
# define TRACE(x...) dprintf("PCI_IO: " x)
|
||||
#else
|
||||
# define TRACE(x...) ;
|
||||
#endif
|
||||
|
||||
|
||||
extern addr_t gPCIioBase;
|
||||
|
||||
status_t
|
||||
pci_io_init()
|
||||
{
|
||||
TRACE("pci_io_init()\n");
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
|
||||
uint8
|
||||
pci_read_io_8(int mapped_io_addr)
|
||||
{
|
||||
TRACE("pci_read_io_8(%d)\n", mapped_io_addr);
|
||||
volatile uint8* ptr = (uint8*)(gPCIioBase + mapped_io_addr);
|
||||
return *ptr;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
pci_write_io_8(int mapped_io_addr, uint8 value)
|
||||
{
|
||||
TRACE("pci_write_io_8(%d)\n", mapped_io_addr);
|
||||
volatile uint8* ptr = (uint8*)(gPCIioBase + mapped_io_addr);
|
||||
*ptr = value;
|
||||
}
|
||||
|
||||
|
||||
uint16
|
||||
pci_read_io_16(int mapped_io_addr)
|
||||
{
|
||||
TRACE("pci_read_io_16(%d)\n", mapped_io_addr);
|
||||
volatile uint16* ptr = (uint16*)(gPCIioBase + mapped_io_addr);
|
||||
return *ptr;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
pci_write_io_16(int mapped_io_addr, uint16 value)
|
||||
{
|
||||
TRACE("pci_write_io_16(%d)\n", mapped_io_addr);
|
||||
volatile uint16* ptr = (uint16*)(gPCIioBase + mapped_io_addr);
|
||||
*ptr = value;
|
||||
}
|
||||
|
||||
|
||||
uint32
|
||||
pci_read_io_32(int mapped_io_addr)
|
||||
{
|
||||
TRACE("pci_read_io_32(%d)\n", mapped_io_addr);
|
||||
volatile uint32* ptr = (uint32*)(gPCIioBase + mapped_io_addr);
|
||||
return *ptr;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
pci_write_io_32(int mapped_io_addr, uint32 value)
|
||||
{
|
||||
TRACE("pci_write_io_32(%d)\n", mapped_io_addr);
|
||||
volatile uint32* ptr = (uint32*)(gPCIioBase + mapped_io_addr);
|
||||
*ptr = value;
|
||||
}
|
||||
@@ -8,6 +8,7 @@
|
||||
|
||||
#include <device_manager.h>
|
||||
#include <PCI.h>
|
||||
#include <drivers/ACPI.h>
|
||||
#include <drivers/bus/FDT.h>
|
||||
|
||||
#include <string.h>
|
||||
@@ -30,7 +31,7 @@ pci_root_supports_device(device_node* parent)
|
||||
if (gDeviceManager->get_attr_string(parent, B_DEVICE_BUS, &bus, false) < B_OK)
|
||||
return -1.0f;
|
||||
|
||||
#ifdef __riscv
|
||||
#if defined(__riscv)
|
||||
const char* compatible;
|
||||
if (gDeviceManager->get_attr_string(parent, "fdt/compatible", &compatible,
|
||||
false) < B_OK)
|
||||
@@ -43,6 +44,17 @@ pci_root_supports_device(device_node* parent)
|
||||
&& strcmp(compatible, "sifive,fu740-pcie") != 0) {
|
||||
return 0.0f;
|
||||
}
|
||||
#elif defined(__aarch64__)
|
||||
if (strcmp(bus, "acpi") != 0)
|
||||
return -1.0f;
|
||||
|
||||
const char* hid;
|
||||
if (gDeviceManager->get_attr_string(parent, ACPI_DEVICE_HID_ITEM, &hid,
|
||||
false) < B_OK)
|
||||
return -1.0f;
|
||||
|
||||
if (strcmp(hid, "PNP0A03") != 0 && strcmp(hid, "PNP0A08") != 0)
|
||||
return -1.0f;
|
||||
#else
|
||||
if (strcmp(bus, "root") != 0)
|
||||
return 0.0f;
|
||||
|
||||
Reference in New Issue
Block a user