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added rdc driver based on vte FreeBSD driver

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* built as is.
* untested, some interrupt handler changes might be needed.
This commit is contained in:
Jérôme Duval
2013-01-08 22:45:31 +01:00
committed by Jerome Duval
parent d997b26243
commit 713f1b8c05
11 changed files with 2947 additions and 0 deletions
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src/add-ons/kernel/drivers/network/Jamfile
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@@ -34,6 +34,7 @@ SubInclude HAIKU_TOP src add-ons kernel drivers network dec21xxx ;
SubInclude HAIKU_TOP src add-ons kernel drivers network ipro100 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network ipro1000 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network jmicron2x0 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network rdc ;
SubInclude HAIKU_TOP src add-ons kernel drivers network rtl8139 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network vt612x ;
src/add-ons/kernel/drivers/network/rdc/Jamfile
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@@ -0,0 +1,3 @@
SubDir HAIKU_TOP src add-ons kernel drivers network rdc ;
SubInclude HAIKU_TOP src add-ons kernel drivers network rdc dev ;
src/add-ons/kernel/drivers/network/rdc/dev/Jamfile
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@@ -0,0 +1,5 @@
SubDir HAIKU_TOP src add-ons kernel drivers network rdc dev ;
SubInclude HAIKU_TOP src add-ons kernel drivers network rdc dev mii ;
SubInclude HAIKU_TOP src add-ons kernel drivers network rdc dev vte ;
src/add-ons/kernel/drivers/network/rdc/dev/mii/Jamfile
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@@ -0,0 +1,18 @@
SubDir HAIKU_TOP src add-ons kernel drivers network rdc dev mii ;
UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ;
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
UsePrivateHeaders net ;
UsePrivateKernelHeaders ;
SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
KernelStaticLibrary rdc_mii.a
:
rdcphy.c
;
ObjectHdrs [ FGristFiles rdcphy$(SUFOBJ) ]
: [ FDirName $(TARGET_COMMON_DEBUG_OBJECT_DIR) libs compat freebsd_network ] ;
Includes [ FGristFiles rdcphy.c ] : <src!libs!compat!freebsd_network>miidevs.h ;
src/add-ons/kernel/drivers/network/rdc/dev/mii/rdcphy.c
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@@ -0,0 +1,240 @@
/*-
* Copyright (c) 2010, Pyun YongHyeon <[email protected]>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice unmodified, this list of conditions, and the following
* disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* Driver for the RDC Semiconductor R6040 10/100 PHY.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/socket.h>
#include <sys/bus.h>
#include <net/if.h>
#include <net/if_media.h>
#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
#include "miidevs.h"
#include <dev/mii/rdcphyreg.h>
#include "miibus_if.h"
static device_probe_t rdcphy_probe;
static device_attach_t rdcphy_attach;
struct rdcphy_softc {
struct mii_softc mii_sc;
int mii_link_tick;
#define RDCPHY_MANNEG_TICK 3
};
static device_method_t rdcphy_methods[] = {
/* device interface */
DEVMETHOD(device_probe, rdcphy_probe),
DEVMETHOD(device_attach, rdcphy_attach),
DEVMETHOD(device_detach, mii_phy_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
DEVMETHOD_END
};
static devclass_t rdcphy_devclass;
static driver_t rdcphy_driver = {
"rdcphy",
rdcphy_methods,
sizeof(struct rdcphy_softc)
};
DRIVER_MODULE(rdcphy, miibus, rdcphy_driver, rdcphy_devclass, 0, 0);
static int rdcphy_service(struct mii_softc *, struct mii_data *, int);
static void rdcphy_status(struct mii_softc *);
static const struct mii_phydesc rdcphys[] = {
MII_PHY_DESC(RDC, R6040),
MII_PHY_END
};
static const struct mii_phy_funcs rdcphy_funcs = {
rdcphy_service,
rdcphy_status,
mii_phy_reset
};
static int
rdcphy_probe(device_t dev)
{
return (mii_phy_dev_probe(dev, rdcphys, BUS_PROBE_DEFAULT));
}
static int
rdcphy_attach(device_t dev)
{
mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &rdcphy_funcs, 1);
return (0);
}
static int
rdcphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
{
struct rdcphy_softc *rsc;
struct ifmedia_entry *ife;
rsc = (struct rdcphy_softc *)sc;
ife = mii->mii_media.ifm_cur;
switch (cmd) {
case MII_POLLSTAT:
break;
case MII_MEDIACHG:
/*
* If the interface is not up, don't do anything.
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
break;
mii_phy_setmedia(sc);
switch (IFM_SUBTYPE(ife->ifm_media)) {
case IFM_100_TX:
case IFM_10_T:
/*
* Report fake lost link event to parent
* driver. This will stop MAC of parent
* driver and make it possible to reconfigure
* MAC after completion of link establishment.
* Note, the parent MAC seems to require
* restarting MAC when underlying any PHY
* configuration was changed even if the
* resolved speed/duplex was not changed at
* all.
*/
mii->mii_media_status = 0;
mii->mii_media_active = IFM_ETHER | IFM_NONE;
rsc->mii_link_tick = RDCPHY_MANNEG_TICK;
/* Immediately report link down. */
mii_phy_update(sc, MII_MEDIACHG);
return (0);
default:
break;
}
break;
case MII_TICK:
if (mii_phy_tick(sc) == EJUSTRETURN)
return (0);
if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
/*
* It seems the PHY hardware does not correctly
* report link status changes when manual link
* configuration is in progress. It is also
* possible for the PHY to complete establishing
* a link within one second such that mii(4)
* did not notice the link change. To workaround
* the issue, emulate lost link event and wait
* for 3 seconds when manual link configuration
* is in progress. 3 seconds would be long
* enough to absorb transient link flips.
*/
if (rsc->mii_link_tick > 0) {
rsc->mii_link_tick--;
return (0);
}
}
break;
}
/* Update the media status. */
PHY_STATUS(sc);
/* Callback if something changed. */
mii_phy_update(sc, cmd);
return (0);
}
static void
rdcphy_status(struct mii_softc *sc)
{
struct mii_data *mii;
struct ifmedia_entry *ife;
int bmsr, bmcr, physts;
mii = sc->mii_pdata;
ife = mii->mii_media.ifm_cur;
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
physts = PHY_READ(sc, MII_RDCPHY_STATUS);
if ((physts & STATUS_LINK_UP) != 0)
mii->mii_media_status |= IFM_ACTIVE;
bmcr = PHY_READ(sc, MII_BMCR);
if ((bmcr & BMCR_ISO) != 0) {
mii->mii_media_active |= IFM_NONE;
mii->mii_media_status = 0;
return;
}
if ((bmcr & BMCR_LOOP) != 0)
mii->mii_media_active |= IFM_LOOP;
if ((bmcr & BMCR_AUTOEN) != 0) {
if ((bmsr & BMSR_ACOMP) == 0) {
/* Erg, still trying, I guess... */
mii->mii_media_active |= IFM_NONE;
return;
}
}
switch (physts & STATUS_SPEED_MASK) {
case STATUS_SPEED_100:
mii->mii_media_active |= IFM_100_TX;
break;
case STATUS_SPEED_10:
mii->mii_media_active |= IFM_10_T;
break;
default:
mii->mii_media_active |= IFM_NONE;
return;
}
if ((physts & STATUS_FULL_DUPLEX) != 0)
mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
else
mii->mii_media_active |= IFM_HDX;
}
src/add-ons/kernel/drivers/network/rdc/dev/mii/rdcphyreg.h
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@@ -0,0 +1,73 @@
/*-
* Copyright (c) 2010, Pyun YongHyeon <[email protected]>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice unmodified, this list of conditions, and the following
* disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _DEV_MII_RDCPHYREG_H_
#define _DEV_MII_RDCPHYREG_H_
#define MII_RDCPHY_DEBUG 0x11
#define DEBUG_JABBER_DIS 0x0040
#define DEBUG_LOOP_BACK_10MBPS 0x0400
#define MII_RDCPHY_CTRL 0x14
#define CTRL_SQE_ENB 0x0100
#define CTRL_NEG_POLARITY 0x0400
#define CTRL_AUTO_POLARITY 0x0800
#define CTRL_MDIXSEL_RX 0x2000
#define CTRL_MDIXSEL_TX 0x4000
#define CTRL_AUTO_MDIX_DIS 0x8000
#define MII_RDCPHY_CTRL2 0x15
#define CTRL2_LED_DUPLEX 0x0000
#define CTRL2_LED_DUPLEX_COL 0x0008
#define CTRL2_LED_ACT 0x0010
#define CTRL2_LED_SPEED_ACT 0x0018
#define CTRL2_LED_BLK_100MBPS_DIS 0x0020
#define CTRL2_LED_BLK_10MBPS_DIS 0x0040
#define CTRL2_LED_BLK_LINK_ACT_DIS 0x0080
#define CTRL2_SDT_THRESH_MASK 0x3E00
#define CTRL2_TIMING_ERR_SEL 0x4000
#define CTRL2_LED_BLK_80MS 0x8000
#define CTRL2_LED_BLK_160MS 0x0000
#define CTRL2_LED_MASK 0x0018
#define MII_RDCPHY_STATUS 0x16
#define STATUS_AUTO_MDIX_RX 0x0200
#define STATUS_AUTO_MDIX_TX 0x0400
#define STATUS_NEG_POLARITY 0x0800
#define STATUS_FULL_DUPLEX 0x1000
#define STATUS_SPEED_10 0x0000
#define STATUS_SPEED_100 0x2000
#define STATUS_SPEED_MASK 0x6000
#define STATUS_LINK_UP 0x8000
/* Analog test register 2 */
#define MII_RDCPHY_TEST2 0x1A
#define TEST2_PWR_DOWN 0x0200
#endif /* _DEV_MII_RDCPHYREG_H_ */
src/add-ons/kernel/drivers/network/rdc/dev/vte/Jamfile
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SubDir HAIKU_TOP src add-ons kernel drivers network rdc dev vte ;
UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ;
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
UsePrivateHeaders net system ;
UsePrivateKernelHeaders ;
SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
KernelAddon rdc :
if_vte.c
glue.c
: libfreebsd_network.a rdc_mii.a
;
src/add-ons/kernel/drivers/network/rdc/dev/vte/glue.c
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@@ -0,0 +1,35 @@
/*
* Copyright 2007-2008, Axel Dörfler, [email protected].
* Distributed under the terms of the MIT License.
*/
#include <dev/pci/pcivar.h>
#include <sys/bus.h>
#include <sys/malloc.h>
#include <sys/rman.h>
#include <sys/systm.h>
#include <machine/bus.h>
#include <net/if.h>
#include <net/if_media.h>
HAIKU_FBSD_DRIVER_GLUE(rdc, vte, pci);
HAIKU_DRIVER_REQUIREMENTS(FBSD_TASKQUEUES | FBSD_SWI_TASKQUEUE);
NO_HAIKU_CHECK_DISABLE_INTERRUPTS();
NO_HAIKU_REENABLE_INTERRUPTS();
extern driver_t *DRIVER_MODULE_NAME(rdcphy, miibus);
driver_t *
__haiku_select_miibus_driver(device_t dev)
{
driver_t *drivers[] = {
DRIVER_MODULE_NAME(rdcphy, miibus),
NULL
};
return __haiku_probe_miibus(dev, drivers);
}
src/add-ons/kernel/drivers/network/rdc/dev/vte/if_vte.c
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src/add-ons/kernel/drivers/network/rdc/dev/vte/if_vtereg.h
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@@ -0,0 +1,346 @@
/*-
* Copyright (c) 2010, Pyun YongHyeon <yongari@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice unmodified, this list of conditions, and the following
* disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _IF_VTEREG_H
#define _IF_VTEREG_H
/*
* RDC Semiconductor PCI vendor ID
*/
#define VENDORID_RDC 0x17F3
/*
* Vortex86 RDC R6040 FastEthernet device ID
*/
#define DEVICEID_RDC_R6040 0x6040 /* PMX-1000 */
/* MAC control register 0 */
#define VTE_MCR0 0x00
#define MCR0_ACCPT_ERR 0x0001
#define MCR0_RX_ENB 0x0002
#define MCR0_ACCPT_RUNT 0x0004
#define MCR0_ACCPT_LONG_PKT 0x0008
#define MCR0_ACCPT_DRIBBLE 0x0010
#define MCR0_PROMISC 0x0020
#define MCR0_BROADCAST_DIS 0x0040
#define MCR0_RX_EARLY_INTR 0x0080
#define MCR0_MULTICAST 0x0100
#define MCR0_FC_ENB 0x0200
#define MCR0_TX_ENB 0x1000
#define MCR0_TX_EARLY_INTR 0x4000
#define MCR0_FULL_DUPLEX 0x8000
/* MAC control register 1 */
#define VTE_MCR1 0x04
#define MCR1_MAC_RESET 0x0001
#define MCR1_MAC_LOOPBACK 0x0002
#define MCR1_EXCESS_COL_RETRANS_DIS 0x0004
#define MCR1_AUTO_CHG_DUPLEX 0x0008
#define MCR1_PKT_LENGTH_1518 0x0010
#define MCR1_PKT_LENGTH_1522 0x0020
#define MCR1_PKT_LENGTH_1534 0x0030
#define MCR1_PKT_LENGTH_1537 0x0000
#define MCR1_EARLY_INTR_THRESH_1129 0x0000
#define MCR1_EARLY_INTR_THRESH_1257 0x0040
#define MCR1_EARLY_INTR_THRESH_1385 0x0080
#define MCR1_EARLY_INTR_THRESH_1513 0x00C0
#define MCR1_EXCESS_COL_RETRY_16 0x0000
#define MCR1_EXCESS_COL_RETRY_32 0x0100
#define MCR1_FC_ACTIVE 0x0200
#define MCR1_RX_DESC_HASH_IDX 0x4000
#define MCR1_RX_UNICAST_HASH 0x8000
#define MCR1_PKT_LENGTH_MASK 0x0030
#define MCR1_EARLY_INTR_THRESH_MASK 0x00C0
/* MAC bus control register */
#define VTE_MBCR 0x08
#define MBCR_FIFO_XFER_LENGTH_4 0x0000
#define MBCR_FIFO_XFER_LENGTH_8 0x0001
#define MBCR_FIFO_XFER_LENGTH_16 0x0002
#define MBCR_FIFO_XFER_LENGTH_32 0x0003
#define MBCR_TX_FIFO_THRESH_16 0x0000
#define MBCR_TX_FIFO_THRESH_32 0x0004
#define MBCR_TX_FIFO_THRESH_64 0x0008
#define MBCR_TX_FIFO_THRESH_96 0x000C
#define MBCR_RX_FIFO_THRESH_8 0x0000
#define MBCR_RX_FIFO_THRESH_16 0x0010
#define MBCR_RX_FIFO_THRESH_32 0x0020
#define MBCR_RX_FIFO_THRESH_64 0x0030
#define MBCR_SDRAM_BUS_REQ_TIMER_MASK 0x1F00
#define MBCR_SDRAM_BUS_REQ_TIMER_SHIFT 8
#define MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT 0x1F00
/* MAC TX interrupt control register */
#define VTE_MTICR 0x0C
#define MTICR_TX_TIMER_MASK 0x001F
#define MTICR_TX_BUNDLE_MASK 0x0F00
#define VTE_IM_TX_TIMER_DEFAULT 0x7F
#define VTE_IM_TX_BUNDLE_DEFAULT 15
#define VTE_IM_TIMER_MIN 0
#define VTE_IM_TIMER_MAX 82
#define VTE_IM_TIMER_MASK 0x001F
#define VTE_IM_TIMER_SHIFT 0
#define VTE_IM_BUNDLE_MIN 1
#define VTE_IM_BUNDLE_MAX 15
#define VTE_IM_BUNDLE_SHIFT 8
/* MAC RX interrupt control register */
#define VTE_MRICR 0x10
#define MRICR_RX_TIMER_MASK 0x001F
#define MRICR_RX_BUNDLE_MASK 0x0F00
#define VTE_IM_RX_TIMER_DEFAULT 0x7F
#define VTE_IM_RX_BUNDLE_DEFAULT 15
/* MAC TX poll command register */
#define VTE_TX_POLL 0x14
#define TX_POLL_START 0x0001
/* MAC RX buffer size register */
#define VTE_MRBSR 0x18
#define VTE_MRBSR_SIZE_MASK 0x03FF
/* MAC RX descriptor control register */
#define VTE_MRDCR 0x1A
#define VTE_MRDCR_RESIDUE_MASK 0x00FF
#define VTE_MRDCR_RX_PAUSE_THRESH_MASK 0xFF00
#define VTE_MRDCR_RX_PAUSE_THRESH_SHIFT 8
/* MAC Last status register */
#define VTE_MLSR 0x1C
#define MLSR_MULTICAST 0x0001
#define MLSR_BROADCAST 0x0002
#define MLSR_CRC_ERR 0x0004
#define MLSR_RUNT 0x0008
#define MLSR_LONG_PKT 0x0010
#define MLSR_TRUNC 0x0020
#define MLSR_DRIBBLE 0x0040
#define MLSR_PHY_ERR 0x0080
#define MLSR_TX_FIFO_UNDERRUN 0x0200
#define MLSR_RX_DESC_UNAVAIL 0x0400
#define MLSR_TX_EXCESS_COL 0x2000
#define MLSR_TX_LATE_COL 0x4000
#define MLSR_RX_FIFO_OVERRUN 0x8000
/* MAC MDIO control register */
#define VTE_MMDIO 0x20
#define MMDIO_REG_ADDR_MASK 0x001F
#define MMDIO_PHY_ADDR_MASK 0x1F00
#define MMDIO_READ 0x2000
#define MMDIO_WRITE 0x4000
#define MMDIO_REG_ADDR_SHIFT 0
#define MMDIO_PHY_ADDR_SHIFT 8
/* MAC MDIO read data register */
#define VTE_MMRD 0x24
#define MMRD_DATA_MASK 0xFFFF
/* MAC MDIO write data register */
#define VTE_MMWD 0x28
#define MMWD_DATA_MASK 0xFFFF
/* MAC TX descriptor start address 0 */
#define VTE_MTDSA0 0x2C
/* MAC TX descriptor start address 1 */
#define VTE_MTDSA1 0x30
/* MAC RX descriptor start address 0 */
#define VTE_MRDSA0 0x34
/* MAC RX descriptor start address 1 */
#define VTE_MRDSA1 0x38
/* MAC Interrupt status register */
#define VTE_MISR 0x3C
#define MISR_RX_DONE 0x0001
#define MISR_RX_DESC_UNAVAIL 0x0002
#define MISR_RX_FIFO_FULL 0x0004
#define MISR_RX_EARLY_INTR 0x0008
#define MISR_TX_DONE 0x0010
#define MISR_TX_EARLY_INTR 0x0080
#define MISR_EVENT_CNT_OFLOW 0x0100
#define MISR_PHY_MEDIA_CHG 0x0200
/* MAC Interrupt enable register */
#define VTE_MIER 0x40
#define VTE_INTRS \
(MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | MISR_RX_FIFO_FULL | \
MISR_TX_DONE | MISR_EVENT_CNT_OFLOW)
/* MAC Event counter interrupt status register */
#define VTE_MECISR 0x44
#define MECISR_EC_RX_DONE 0x0001
#define MECISR_EC_MULTICAST 0x0002
#define MECISR_EC_BROADCAST 0x0004
#define MECISR_EC_CRC_ERR 0x0008
#define MECISR_EC_RUNT 0x0010
#define MESCIR_EC_LONG_PKT 0x0020
#define MESCIR_EC_RX_DESC_UNAVAIL 0x0080
#define MESCIR_EC_RX_FIFO_FULL 0x0100
#define MESCIR_EC_TX_DONE 0x0200
#define MESCIR_EC_LATE_COL 0x0400
#define MESCIR_EC_TX_UNDERRUN 0x0800
/* MAC Event counter interrupt enable register */
#define VTE_MECIER 0x48
#define VTE_MECIER_INTRS \
(MECISR_EC_RX_DONE | MECISR_EC_MULTICAST | MECISR_EC_BROADCAST | \
MECISR_EC_CRC_ERR | MECISR_EC_RUNT | MESCIR_EC_LONG_PKT | \
MESCIR_EC_RX_DESC_UNAVAIL | MESCIR_EC_RX_FIFO_FULL | \
MESCIR_EC_TX_DONE | MESCIR_EC_LATE_COL | MESCIR_EC_TX_UNDERRUN)
#define VTE_CNT_RX_DONE 0x50
#define VTE_CNT_MECNT0 0x52
#define VTE_CNT_MECNT1 0x54
#define VTE_CNT_MECNT2 0x56
#define VTE_CNT_MECNT3 0x58
#define VTE_CNT_TX_DONE 0x5A
#define VTE_CNT_MECNT4 0x5C
#define VTE_CNT_PAUSE 0x5E
/* MAC Hash table register */
#define VTE_MAR0 0x60
#define VTE_MAR1 0x62
#define VTE_MAR2 0x64
#define VTE_MAR3 0x66
/* MAC station address and multicast address register */
#define VTE_MID0L 0x68
#define VTE_MID0M 0x6A
#define VTE_MID0H 0x6C
#define VTE_MID1L 0x70
#define VTE_MID1M 0x72
#define VTE_MID1H 0x74
#define VTE_MID2L 0x78
#define VTE_MID2M 0x7A
#define VTE_MID2H 0x7C
#define VTE_MID3L 0x80
#define VTE_MID3M 0x82
#define VTE_MID3H 0x84
#define VTE_RXFILTER_PEEFECT_BASE VTE_MID1L
#define VTE_RXFILT_PERFECT_CNT 3
/* MAC PHY status change configuration register */
#define VTE_MPSCCR 0x88
#define MPSCCR_TIMER_DIVIDER_MASK 0x0007
#define MPSCCR_PHY_ADDR_MASK 0x1F00
#define MPSCCR_PHY_STS_CHG_ENB 0x8000
#define MPSCCR_PHY_ADDR_SHIFT 8
/* MAC PHY status register2 */
#define VTE_MPSR 0x8A
#define MPSR_LINK_UP 0x0001
#define MPSR_SPEED_100 0x0002
#define MPSR_FULL_DUPLEX 0x0004
/* MAC Status machine(undocumented). */
#define VTE_MACSM 0xAC
/* MDC Speed control register */
#define VTE_MDCSC 0xB6
#define MDCSC_DEFAULT 0x0030
/* MAC Identifier and revision register */
#define VTE_MACID_REV 0xBC
#define VTE_MACID_REV_MASK 0x00FF
#define VTE_MACID_MASK 0xFF00
#define VTE_MACID_REV_SHIFT 0
#define VTE_MACID_SHIFT 8
/* MAC Identifier register */
#define VTE_MACID 0xBE
/*
* RX descriptor
* - Added one more uint16_t member to align it 4 on bytes boundary.
* This does not affect operation of controller since it includes
* next pointer address.
*/
struct vte_rx_desc {
uint16_t drst;
uint16_t drlen;
uint32_t drbp;
uint32_t drnp;
uint16_t hidx;
uint16_t rsvd2;
uint16_t rsvd3;
uint16_t __pad; /* Not actual descriptor member. */
};
#define VTE_DRST_MID_MASK 0x0003
#define VTE_DRST_MID_HIT 0x0004
#define VTE_DRST_MULTICAST_HIT 0x0008
#define VTE_DRST_MULTICAST 0x0010
#define VTE_DRST_BROADCAST 0x0020
#define VTE_DRST_CRC_ERR 0x0040
#define VTE_DRST_RUNT 0x0080
#define VTE_DRST_LONG 0x0100
#define VTE_DRST_TRUNC 0x0200
#define VTE_DRST_DRIBBLE 0x0400
#define VTE_DRST_PHY_ERR 0x0800
#define VTE_DRST_RX_OK 0x4000
#define VTE_DRST_RX_OWN 0x8000
#define VTE_RX_LEN(x) ((x) & 0x7FF)
#define VTE_RX_HIDX(x) ((x) & 0x3F)
/*
* TX descriptor
* - Added one more uint32_t member to align it on 16 bytes boundary.
*/
struct vte_tx_desc {
uint16_t dtst;
uint16_t dtlen;
uint32_t dtbp;
uint32_t dtnp;
uint32_t __pad; /* Not actual descriptor member. */
};
#define VTE_DTST_EXCESS_COL 0x0010
#define VTE_DTST_LATE_COL 0x0020
#define VTE_DTST_UNDERRUN 0x0040
#define VTE_DTST_NO_CRC 0x2000
#define VTE_DTST_TX_OK 0x4000
#define VTE_DTST_TX_OWN 0x8000
#define VTE_TX_LEN(x) ((x) & 0x7FF)
#endif /* _IF_VTEREG_H */
src/add-ons/kernel/drivers/network/rdc/dev/vte/if_vtevar.h
+163
View File
@@ -0,0 +1,163 @@
/*-
* Copyright (c) 2010, Pyun YongHyeon <yongari@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice unmodified, this list of conditions, and the following
* disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _IF_VTEVAR_H
#define _IF_VTEVAR_H
#define VTE_TX_RING_CNT 64
#define VTE_TX_RING_ALIGN 16
/*
* The TX/RX descriptor format has no limitation for number of
* descriptors in TX/RX ring. However, the maximum number of
* descriptors that could be set as RX descriptor ring residue
* counter is 255. This effectively limits number of RX
* descriptors available to be less than or equal to 255.
*/
#define VTE_RX_RING_CNT 128
#define VTE_RX_RING_ALIGN 16
#define VTE_RX_BUF_ALIGN 4
#define VTE_DESC_INC(x, y) ((x) = ((x) + 1) % (y))
#define VTE_TX_RING_SZ \
(sizeof(struct vte_tx_desc) * VTE_TX_RING_CNT)
#define VTE_RX_RING_SZ \
(sizeof(struct vte_rx_desc) * VTE_RX_RING_CNT)
#define VTE_RX_BUF_SIZE_MAX (MCLBYTES - sizeof(uint32_t))
#define VTE_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
struct vte_rxdesc {
struct mbuf *rx_m;
bus_dmamap_t rx_dmamap;
struct vte_rx_desc *rx_desc;
};
struct vte_txdesc {
struct mbuf *tx_m;
bus_dmamap_t tx_dmamap;
struct vte_tx_desc *tx_desc;
int tx_flags;
#define VTE_TXMBUF 0x0001
};
struct vte_chain_data {
bus_dma_tag_t vte_parent_tag;
bus_dma_tag_t vte_buffer_tag;
bus_dma_tag_t vte_tx_tag;
struct vte_txdesc vte_txdesc[VTE_TX_RING_CNT];
struct mbuf *vte_txmbufs[VTE_TX_RING_CNT];
bus_dma_tag_t vte_rx_tag;
struct vte_rxdesc vte_rxdesc[VTE_RX_RING_CNT];
bus_dma_tag_t vte_tx_ring_tag;
bus_dmamap_t vte_tx_ring_map;
bus_dma_tag_t vte_rx_ring_tag;
bus_dmamap_t vte_rx_ring_map;
bus_dmamap_t vte_rx_sparemap;
struct vte_tx_desc *vte_tx_ring;
bus_addr_t vte_tx_ring_paddr;
struct vte_rx_desc *vte_rx_ring;
bus_addr_t vte_rx_ring_paddr;
int vte_tx_prod;
int vte_tx_cons;
int vte_tx_cnt;
int vte_rx_cons;
};
struct vte_hw_stats {
/* RX stats. */
uint32_t rx_frames;
uint32_t rx_bcast_frames;
uint32_t rx_mcast_frames;
uint32_t rx_runts;
uint32_t rx_crcerrs;
uint32_t rx_long_frames;
uint32_t rx_fifo_full;
uint32_t rx_desc_unavail;
uint32_t rx_pause_frames;
/* TX stats. */
uint32_t tx_frames;
uint32_t tx_underruns;
uint32_t tx_late_colls;
uint32_t tx_pause_frames;
};
struct vte_ident {
uint16_t vendorid;
uint16_t deviceid;
const char *name;
};
/*
* Software state per device.
*/
struct vte_softc {
struct ifnet *vte_ifp;
device_t vte_dev;
device_t vte_miibus;
struct resource *vte_res;
int vte_res_id;
int vte_res_type;
struct resource *vte_irq;
void *vte_intrhand;
const struct vte_ident *vte_ident;
uint8_t vte_eaddr[ETHER_ADDR_LEN];
int vte_flags;
#define VTE_FLAG_LINK 0x8000
struct callout vte_tick_ch;
struct vte_hw_stats vte_stats;
struct vte_chain_data vte_cdata;
int vte_if_flags;
int vte_watchdog_timer;
int vte_int_rx_mod;
int vte_int_tx_mod;
struct mtx vte_mtx;
};
/* Register access macros. */
#define CSR_WRITE_2(_sc, reg, val) \
bus_write_2((_sc)->vte_res, (reg), (val))
#define CSR_READ_2(_sc, reg) \
bus_read_2((_sc)->vte_res, (reg))
#define VTE_LOCK(_sc) mtx_lock(&(_sc)->vte_mtx)
#define VTE_UNLOCK(_sc) mtx_unlock(&(_sc)->vte_mtx)
#define VTE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->vte_mtx, MA_OWNED)
#define VTE_TX_TIMEOUT 5
#define VTE_RESET_TIMEOUT 100
#define VTE_TIMEOUT 1000
#define VTE_PHY_TIMEOUT 1000
#endif /* _IF_VTEVAR_H */