intel_extreme: Fix swapping of p2 values for 9xx cards
This would lead to no valid PLL combination being found, and uninitialized stack memory eventually used to set the PLL. Add a memset and a debugger() call to make this easier to notice. Should fix #14368 Change-Id: Iff307439dc82a8b81bb46c1b73b63c21ee1c8279 Reviewed-on: https://review.haiku-os.org/c/haiku/+/1898 Reviewed-by: Adrien Destugues <[email protected]>
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Adrien Destugues
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@@ -55,19 +55,19 @@ static pll_limits kLimits85x = {
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// and carried on to later cards with just one further change (to the P2 cutoff
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// frequency) in Sandy Bridge.
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//
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// So, it makes no sense to have separa limits and algorithm for 9xx and G45.
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// So, it makes no sense to have separate limits and algorithm for 9xx and G45.
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static pll_limits kLimits9xxSdvo = {
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// p, p1, p2, n, m, m1, m2
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{ 5, 1, 10, 5, 70, 12, 7}, // min
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{ 80, 8, 5, 10, 120, 22, 11}, // max
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{ 5, 1, 5, 5, 70, 12, 7}, // min
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{ 80, 8, 10, 10, 120, 22, 11}, // max
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200000, 1400000, 2800000
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};
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static pll_limits kLimits9xxLvds = {
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// p, p1, p2, n, m, m1, m2
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{ 7, 1, 14, 1, 70, 8, 3}, // min
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{ 98, 8, 7, 6, 120, 18, 7}, // max
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{ 7, 1, 7, 1, 70, 8, 3}, // min
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{ 98, 8, 14, 6, 120, 18, 7}, // max
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112000, 1400000, 2800000
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};
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@@ -406,6 +406,7 @@ compute_dpll_9xx(display_mode* current, pll_divisors* divisors, bool isLVDS)
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float best = requestedPixelClock;
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pll_divisors bestDivisors;
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memset(&bestDivisors, 0, sizeof(bestDivisors));
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for (divisors->m1 = limits.min.m1; divisors->m1 <= limits.max.m1;
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divisors->m1++) {
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@@ -438,9 +439,13 @@ compute_dpll_9xx(display_mode* current, pll_divisors* divisors, bool isLVDS)
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*divisors = bestDivisors;
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TRACE("%s: best MHz: %g (error: %g)\n", __func__,
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((referenceClock * divisors->m) / divisors->n) / divisors->p,
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best);
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if (best == requestedPixelClock)
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debugger("No valid PLL configuration found");
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else {
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TRACE("%s: best MHz: %g (error: %g)\n", __func__,
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((referenceClock * divisors->m) / divisors->n) / divisors->p,
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best);
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}
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}
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