* add lots of missing evergreen defines
* evergreen headers are split due to different header copyrights * detect and set up evergreen memory controler * change the way we manage radeon chipsets to more closely match drm driver as the chipset model numbers aren't in order and change from numbers to names. * check for evergreen when populating frame buffer information. * style cleanup git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@43225 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
@@ -0,0 +1,84 @@
|
||||
/*
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||||
* Copyright 2010 Advanced Micro Devices, Inc.
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||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#ifndef R800D_REG_H
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#define R800D_REG_H
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#define EVERGREEN_MC_ARB_RAMCFG 0x2760
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#define NOOFBANK_SHIFT 0
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#define NOOFBANK_MASK 0x00000003
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#define NOOFRANK_SHIFT 2
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#define NOOFRANK_MASK 0x00000004
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#define NOOFROWS_SHIFT 3
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#define NOOFROWS_MASK 0x00000038
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#define NOOFCOLS_SHIFT 6
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#define NOOFCOLS_MASK 0x000000C0
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#define CHANSIZE_SHIFT 8
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#define CHANSIZE_MASK 0x00000100
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#define BURSTLENGTH_SHIFT 9
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#define BURSTLENGTH_MASK 0x00000200
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#define CHANSIZE_OVERRIDE (1 << 11)
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#define EVERGREEN_FUS_MC_ARB_RAMCFG 0x2768
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#define EVERGREEN_MC_VM_AGP_TOP 0x2028
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#define EVERGREEN_MC_VM_AGP_BOT 0x202C
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#define EVERGREEN_MC_VM_AGP_BASE 0x2030
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#define EVERGREEN_MC_VM_FB_LOCATION 0x2024
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#define EVERGREEN_MC_FUS_VM_FB_OFFSET 0x2898
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#define EVERGREEN_MC_VM_MB_L1_TLB0_CNTL 0x2234
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#define EVERGREEN_MC_VM_MB_L1_TLB1_CNTL 0x2238
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#define EVERGREEN_MC_VM_MB_L1_TLB2_CNTL 0x223C
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#define EVERGREEN_MC_VM_MB_L1_TLB3_CNTL 0x2240
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#define ENABLE_L1_TLB (1 << 0)
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#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
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#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
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#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
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#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
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#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
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#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
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#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
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#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
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#define EVERGREEN_MC_VM_MD_L1_TLB0_CNTL 0x2654
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#define EVERGREEN_MC_VM_MD_L1_TLB1_CNTL 0x2658
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#define EVERGREEN_MC_VM_MD_L1_TLB2_CNTL 0x265C
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#define EVERGREEN_FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C
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#define EVERGREEN_FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660
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#define EVERGREEN_FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664
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#define EVERGREEN_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
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#define EVERGREEN_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
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#define EVERGREEN_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
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#define EVERGREEN_BIOS_0_SCRATCH 0x8500
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#define EVERGREEN_BIOS_1_SCRATCH 0x8504
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#define EVERGREEN_BIOS_2_SCRATCH 0x8508
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#define EVERGREEN_BIOS_3_SCRATCH 0x850C
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#define EVERGREEN_BIOS_4_SCRATCH 0x8510
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#define EVERGREEN_BIOS_5_SCRATCH 0x8514
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#define EVERGREEN_BIOS_6_SCRATCH 0x8518
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#define EVERGREEN_BIOS_7_SCRATCH 0x851C
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#define EVERGREEN_SCRATCH_UMSK 0x8540
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#define EVERGREEN_SCRATCH_ADDR 0x8544
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#endif
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@@ -18,7 +18,8 @@
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#include "r500_reg.h"
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#include "r600_reg.h"
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#include "r700_reg.h"
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#include "r800_reg.h"
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#include "evergreen_reg.h"
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#include "evergreend.h"
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#include <Accelerant.h>
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#include <Drivers.h>
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@@ -28,16 +29,6 @@
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#define VENDOR_ID_ATI 0x1002
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// Card models
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#define RADEON_R520 0x0520 // Fudo
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#define RADEON_R580 0x0580 // Rodin
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#define RADEON_R600 0x0600 // Pele
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#define RADEON_R700 0x0700 // Wekiva
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#define RADEON_R1000 0x1000 // Evergreen
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#define RADEON_R2000 0x2000 // Northern Islands
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#define RADEON_R3000 0x3000 // Southern Islands
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#define RADEON_R4000 0x4000 // Not yet known / used
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// Card chipset flags
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#define CHIP_STD (1 << 0) // Standard chipset
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#define CHIP_IGP (1 << 1) // IGP chipset
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@@ -58,6 +49,47 @@
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#define RHD_POWER_UNKNOWN 3 /* initial state */
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// Radeon Chipsets
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enum radeon_chipset {
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RADEON_R420 = 0, //r400, Radeon X700-X850
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RADEON_RV515,
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RADEON_R520, //r500, Radeon X1300-X1950
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RADEON_RV530,
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RADEON_RV560,
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RADEON_RV570,
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RADEON_R580,
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RADEON_R600, //r600, Radeon HD 2000, 3000
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RADEON_RV610,
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RADEON_RV630,
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RADEON_RV670,
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RADEON_RV620,
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RADEON_RV635,
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RADEON_RS780,
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RADEON_RS880,
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RADEON_RV770, //r700, Radeon HD 4000
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RADEON_RV730,
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RADEON_RV710,
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RADEON_RV740,
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RADEON_CEDAR, //Evergreen, Radeon HD 5000
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RADEON_REDWOOD,
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RADEON_JUNIPER,
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RADEON_CYPRESS,
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RADEON_HEMLOCK,
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RADEON_PALM, //Fusion APU (NI), Radeon HD 6000
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RADEON_SUMO,
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RADEON_SUMO2,
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RADEON_CAICOS, //Nothern Islands, Radeon HD 6000
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RADEON_TURKS,
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RADEON_BARTS,
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RADEON_CAYMAN,
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RADEON_ANTILLES,
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RADEON_LOMBOK, //Southern Islands, Radeon HD 7000
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RADEON_THAMES,
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RADEON_TAHITI,
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RADEON_NEWZEALAND
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};
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struct ring_buffer {
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struct lock lock;
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uint32 register_base;
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@@ -67,7 +67,7 @@ radeon_bios_isposted()
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radeon_shared_info &info = *gInfo->shared_info;
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uint32 reg;
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if (info.device_chipset == (RADEON_R1000 | 0x50)) {
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if (info.device_chipset == RADEON_PALM) {
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// palms
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reg = Read32(OUT, EVERGREEN_CRTC_CONTROL
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+ EVERGREEN_CRTC0_REGISTER_OFFSET)
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@@ -75,7 +75,7 @@ radeon_bios_isposted()
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+ EVERGREEN_CRTC1_REGISTER_OFFSET);
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if ((reg & EVERGREEN_CRTC_MASTER_EN) != 0)
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return true;
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} else if (info.device_chipset >= RADEON_R1000) {
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} else if (info.device_chipset >= RADEON_CEDAR) {
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// evergreen or higher
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reg = Read32(OUT, EVERGREEN_CRTC_CONTROL
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+ EVERGREEN_CRTC0_REGISTER_OFFSET)
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@@ -91,7 +91,7 @@ radeon_bios_isposted()
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+ EVERGREEN_CRTC5_REGISTER_OFFSET);
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if ((reg & EVERGREEN_CRTC_MASTER_EN) != 0)
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return true;
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} else if (info.device_chipset > RADEON_R580) {
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} else if (info.device_chipset >= RADEON_R420) {
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// avivio through r700
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reg = Read32(OUT, AVIVO_D1CRTC_CONTROL) |
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Read32(OUT, AVIVO_D2CRTC_CONTROL);
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@@ -40,7 +40,8 @@ init_registers(register_info* regs, uint8 crtcID)
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radeon_shared_info &info = *gInfo->shared_info;
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if (info.device_chipset >= RADEON_R1000) {
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if (info.device_chipset >= RADEON_CEDAR) {
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// Evergreen
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uint32 offset = 0;
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switch(crtcID) {
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@@ -103,7 +104,8 @@ init_registers(register_info* regs, uint8 crtcID)
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regs->viewportStart = EVERGREEN_VIEWPORT_START + offset;
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regs->viewportSize = EVERGREEN_VIEWPORT_SIZE + offset;
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} else if (info.device_chipset >= RADEON_R700) {
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} else if (info.device_chipset >= RADEON_RV770) {
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// R700 series
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uint32 offset = 0;
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switch(crtcID) {
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@@ -150,6 +152,7 @@ init_registers(register_info* regs, uint8 crtcID)
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regs->viewportSize = AVIVO_D1MODE_VIEWPORT_SIZE + offset;
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} else if (info.device_chipset >= RADEON_R600) {
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// R600 series+
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uint32 offset = 0;
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switch(crtcID) {
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@@ -957,7 +960,7 @@ display_crtc_fb_set(uint8 crtcID, display_mode *mode)
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TRACE("%s: Framebuffer at: 0x%" B_PRIX64 "\n", __func__, fbAddress);
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if (info.device_chipset >= RADEON_R700) {
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if (info.device_chipset >= RADEON_RV770) {
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TRACE("%s: Set SurfaceAddress High: 0x%" B_PRIX32 "\n",
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__func__, (fbAddress >> 32) & 0xf);
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@@ -48,56 +48,56 @@ radeon_gpu_reset()
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ERROR("%s: Timeout waiting for MC to idle!\n", __func__);
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}
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if (info.device_chipset < RADEON_R1000) {
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if (info.device_chipset < RADEON_CEDAR) {
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Write32(OUT, CP_ME_CNTL, CP_ME_HALT);
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// Disable Command Processor parsing / prefetching
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// Register busy masks for early Radeon HD cards
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// GRBM Command Processor Status
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uint32 grbm_busy_mask = VC_BUSY;
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uint32 grbmBusyMask = VC_BUSY;
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// Vertex Cache Busy
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grbm_busy_mask |= VGT_BUSY_NO_DMA | VGT_BUSY;
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grbmBusyMask |= VGT_BUSY_NO_DMA | VGT_BUSY;
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// Vertex Grouper Tessellator Busy
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grbm_busy_mask |= TA03_BUSY;
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grbmBusyMask |= TA03_BUSY;
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// unknown
|
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grbm_busy_mask |= TC_BUSY;
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grbmBusyMask |= TC_BUSY;
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// Texture Cache Busy
|
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grbm_busy_mask |= SX_BUSY;
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grbmBusyMask |= SX_BUSY;
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// Shader Export Busy
|
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grbm_busy_mask |= SH_BUSY;
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grbmBusyMask |= SH_BUSY;
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// Sequencer Instruction Cache Busy
|
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grbm_busy_mask |= SPI_BUSY;
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grbmBusyMask |= SPI_BUSY;
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// Shader Processor Interpolator Busy
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grbm_busy_mask |= SMX_BUSY;
|
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grbmBusyMask |= SMX_BUSY;
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// Shader Memory Exchange
|
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grbm_busy_mask |= SC_BUSY;
|
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grbmBusyMask |= SC_BUSY;
|
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// Scan Converter Busy
|
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grbm_busy_mask |= PA_BUSY;
|
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grbmBusyMask |= PA_BUSY;
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// Primitive Assembler Busy
|
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grbm_busy_mask |= DB_BUSY;
|
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grbmBusyMask |= DB_BUSY;
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// Depth Block Busy
|
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grbm_busy_mask |= CR_BUSY;
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grbmBusyMask |= CR_BUSY;
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// unknown
|
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grbm_busy_mask |= CB_BUSY;
|
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grbmBusyMask |= CB_BUSY;
|
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// Color Block Busy
|
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grbm_busy_mask |= GUI_ACTIVE;
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grbmBusyMask |= GUI_ACTIVE;
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// unknown (graphics pipeline active?)
|
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|
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// GRBM Command Processor Detailed Status
|
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uint32 grbm2_busy_mask = SPI0_BUSY | SPI1_BUSY | SPI2_BUSY | SPI3_BUSY;
|
||||
uint32 grbm2BusyMask = SPI0_BUSY | SPI1_BUSY | SPI2_BUSY | SPI3_BUSY;
|
||||
// Shader Processor Interpolator 0 - 3 Busy
|
||||
grbm2_busy_mask |= TA0_BUSY | TA1_BUSY | TA2_BUSY | TA3_BUSY;
|
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grbm2BusyMask |= TA0_BUSY | TA1_BUSY | TA2_BUSY | TA3_BUSY;
|
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// unknown 0 - 3 Busy
|
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grbm2_busy_mask |= DB0_BUSY | DB1_BUSY | DB2_BUSY | DB3_BUSY;
|
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grbm2BusyMask |= DB0_BUSY | DB1_BUSY | DB2_BUSY | DB3_BUSY;
|
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// Depth Block 0 - 3 Busy
|
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grbm2_busy_mask |= CB0_BUSY | CB1_BUSY | CB2_BUSY | CB3_BUSY;
|
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grbm2BusyMask |= CB0_BUSY | CB1_BUSY | CB2_BUSY | CB3_BUSY;
|
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// Color Block 0 - 3 Busy
|
||||
|
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uint32 tmp;
|
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/* Check if any of the rendering block is busy and reset it */
|
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if ((Read32(OUT, GRBM_STATUS) & grbm_busy_mask) != 0
|
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|| (Read32(OUT, GRBM_STATUS2) & grbm2_busy_mask) != 0) {
|
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if ((Read32(OUT, GRBM_STATUS) & grbmBusyMask) != 0
|
||||
|| (Read32(OUT, GRBM_STATUS2) & grbm2BusyMask) != 0) {
|
||||
tmp = SOFT_RESET_CR
|
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| SOFT_RESET_DB
|
||||
| SOFT_RESET_CB
|
||||
@@ -127,13 +127,13 @@ radeon_gpu_reset()
|
||||
// Let things settle
|
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snooze(1000);
|
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} else {
|
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// Northern Islands and higher
|
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// Evergreen and higher
|
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|
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Write32(OUT, CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
|
||||
// Disable Command Processor parsing / prefetching
|
||||
|
||||
// reset the graphics pipeline components
|
||||
uint32 grbm_reset = (SOFT_RESET_CP
|
||||
uint32 grbmReset = (SOFT_RESET_CP
|
||||
| SOFT_RESET_CB
|
||||
| SOFT_RESET_DB
|
||||
| SOFT_RESET_GDS
|
||||
@@ -147,7 +147,7 @@ radeon_gpu_reset()
|
||||
| SOFT_RESET_VGT
|
||||
| SOFT_RESET_IA);
|
||||
|
||||
Write32(OUT, GRBM_SOFT_RESET, grbm_reset);
|
||||
Write32(OUT, GRBM_SOFT_RESET, grbmReset);
|
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Read32(OUT, GRBM_SOFT_RESET);
|
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|
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snooze(50);
|
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@@ -360,13 +360,93 @@ radeon_gpu_mc_setup_r700()
|
||||
}
|
||||
|
||||
|
||||
static status_t
|
||||
radeon_gpu_mc_setup_evergreen()
|
||||
{
|
||||
// HDP initialization
|
||||
uint32 i;
|
||||
uint32 j;
|
||||
for (i = 0, j = 0; i < 32; i++, j += 0x18) {
|
||||
Write32(OUT, (0x2c14 + j), 0x00000000);
|
||||
Write32(OUT, (0x2c18 + j), 0x00000000);
|
||||
Write32(OUT, (0x2c1c + j), 0x00000000);
|
||||
Write32(OUT, (0x2c20 + j), 0x00000000);
|
||||
Write32(OUT, (0x2c24 + j), 0x00000000);
|
||||
}
|
||||
Write32(OUT, HDP_REG_COHERENCY_FLUSH_CNTL, 0);
|
||||
|
||||
// idle the memory controller
|
||||
struct gpu_state gpuState;
|
||||
radeon_gpu_mc_halt(&gpuState);
|
||||
|
||||
uint32 idleState = radeon_gpu_mc_idlecheck();
|
||||
if (idleState > 0) {
|
||||
ERROR("%s: Cannot modify non-idle MC! idleState: 0x%" B_PRIX32 "\n",
|
||||
__func__, idleState);
|
||||
//return B_ERROR;
|
||||
}
|
||||
|
||||
Write32(OUT, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
|
||||
|
||||
// TODO: Memory Controller AGP
|
||||
Write32(OUT, EVERGREEN_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
|
||||
gInfo->fb.vramStart >> 12);
|
||||
Write32(OUT, EVERGREEN_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
|
||||
gInfo->fb.vramEnd >> 12);
|
||||
|
||||
Write32(OUT, EVERGREEN_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
|
||||
|
||||
radeon_shared_info &info = *gInfo->shared_info;
|
||||
if ((info.chipsetFlags & CHIP_IGP) != 0) {
|
||||
// Evergreen IGP Fusion
|
||||
uint32 tmp = Read32(OUT, EVERGREEN_MC_FUS_VM_FB_OFFSET)
|
||||
& 0x000FFFFF;
|
||||
tmp |= ((gInfo->fb.vramEnd >> 20) & 0xF) << 24;
|
||||
tmp |= ((gInfo->fb.vramStart >> 20) & 0xF) << 20;
|
||||
Write32(OUT, EVERGREEN_MC_FUS_VM_FB_OFFSET, tmp);
|
||||
}
|
||||
|
||||
uint32 tmp = ((gInfo->fb.vramEnd >> 24) & 0xFFFF) << 16;
|
||||
tmp |= ((gInfo->fb.vramStart >> 24) & 0xFFFF);
|
||||
|
||||
Write32(OUT, EVERGREEN_MC_VM_FB_LOCATION, tmp);
|
||||
Write32(OUT, HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));
|
||||
Write32(OUT, HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
|
||||
Write32(OUT, HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
|
||||
|
||||
// is AGP?
|
||||
// Write32(OUT, EVERGREEN_MC_VM_AGP_TOP, gInfo->fb.gartEnd >> 16);
|
||||
// Write32(OUT, EVERGREEN_MC_VM_AGP_BOT, gInfo->fb.gartStart >> 16);
|
||||
// Write32(OUT, EVERGREEN_MC_VM_AGP_BASE, gInfo->fb.agpBase >> 22);
|
||||
// else?
|
||||
Write32(OUT, EVERGREEN_MC_VM_AGP_BASE, 0);
|
||||
Write32(OUT, EVERGREEN_MC_VM_AGP_TOP, 0x0FFFFFFF);
|
||||
Write32(OUT, EVERGREEN_MC_VM_AGP_BOT, 0x0FFFFFFF);
|
||||
|
||||
idleState = radeon_gpu_mc_idlecheck();
|
||||
if (idleState > 0) {
|
||||
ERROR("%s: Cannot modify non-idle MC! idleState: 0x%" B_PRIX32 "\n",
|
||||
__func__, idleState);
|
||||
//return B_ERROR;
|
||||
}
|
||||
radeon_gpu_mc_resume(&gpuState);
|
||||
|
||||
// disable render control
|
||||
Write32(OUT, 0x000300, Read32(OUT, 0x000300) & 0xFFFCFFFF);
|
||||
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
radeon_gpu_mc_init()
|
||||
{
|
||||
radeon_shared_info &info = *gInfo->shared_info;
|
||||
|
||||
uint32 fbVMLocationReg;
|
||||
if (info.device_chipset >= RADEON_R700) {
|
||||
if (info.device_chipset >= RADEON_CEDAR) {
|
||||
fbVMLocationReg = EVERGREEN_MC_VM_FB_LOCATION;
|
||||
} else if (info.device_chipset >= RADEON_RV770) {
|
||||
fbVMLocationReg = R700_MC_VM_FB_LOCATION;
|
||||
} else {
|
||||
fbVMLocationReg = R600_MC_VM_FB_LOCATION;
|
||||
@@ -406,7 +486,9 @@ radeon_gpu_mc_setup()
|
||||
TRACE("%s: vramStart: 0x%" B_PRIX64 ", vramEnd: 0x%" B_PRIX64 "\n",
|
||||
__func__, gInfo->fb.vramStart, gInfo->fb.vramEnd);
|
||||
|
||||
if (info.device_chipset >= RADEON_R700)
|
||||
if (info.device_chipset >= RADEON_CEDAR)
|
||||
return radeon_gpu_mc_setup_evergreen();
|
||||
if (info.device_chipset >= RADEON_RV770)
|
||||
return radeon_gpu_mc_setup_r700();
|
||||
else if (info.device_chipset >= RADEON_R600)
|
||||
return radeon_gpu_mc_setup_r600();
|
||||
@@ -443,7 +525,7 @@ lock_i2c(void* cookie, bool lock)
|
||||
if (lock == true) {
|
||||
// hw_capable and > DCE3
|
||||
if (info->hw_capable == true
|
||||
&& sinfo.device_chipset >= (RADEON_R600 | 0x20)) {
|
||||
&& sinfo.dceMajor >= 3) {
|
||||
// Switch GPIO pads to ddc mode
|
||||
buffer = Read32(OUT, info->mask_scl_reg);
|
||||
buffer &= ~(1 << 16);
|
||||
|
||||
@@ -303,7 +303,7 @@ pll_setup_flags(pll_info *pll, uint8 crtcID)
|
||||
pll->flags |= PLL_PREFER_LOW_REF_DIV;
|
||||
|
||||
|
||||
if (info.device_chipset < RADEON_R700)
|
||||
if (info.device_chipset < RADEON_RV770)
|
||||
pll->flags |= PLL_PREFER_MINM_OVER_MAXP;
|
||||
|
||||
|
||||
@@ -339,7 +339,7 @@ pll_adjust(pll_info *pll, uint8 crtcID)
|
||||
uint32 encoderID = gConnector[connectorIndex]->encoder.objectID;
|
||||
uint32 encoderMode = display_get_encoder_mode(connectorIndex);
|
||||
|
||||
if (info.device_chipset >= (RADEON_R600 | 0x20)) {
|
||||
if (info.dceMajor >= 3) {
|
||||
union adjust_pixel_clock args;
|
||||
|
||||
uint8 tableMajor;
|
||||
|
||||
@@ -50,164 +50,160 @@ const struct supported_device {
|
||||
// R500 Series (Radeon Xxxx) DCE 1.0
|
||||
// R600 series (HD24xx - HD42xx)
|
||||
// Codename: Pele
|
||||
{0x94c7, 2, 0, RADEON_R600 | 0x10, CHIP_STD, "Radeon HD 2350"},
|
||||
{0x94c1, 2, 0, RADEON_R600 | 0x10, CHIP_IGP, "Radeon HD 2400"},
|
||||
{0x94c3, 2, 0, RADEON_R600 | 0x10, CHIP_STD, "Radeon HD 2400"},
|
||||
{0x94cc, 2, 0, RADEON_R600 | 0x10, CHIP_STD, "Radeon HD 2400"},
|
||||
{0x9586, 2, 0, RADEON_R600 | 0x30, CHIP_STD, "Radeon HD 2600"},
|
||||
{0x9588, 2, 0, RADEON_R600 | 0x30, CHIP_STD, "Radeon HD 2600"},
|
||||
{0x958a, 2, 0, RADEON_R600 | 0x30, CHIP_STD, "Radeon HD 2600 X2"},
|
||||
{0x94c7, 2, 0, RADEON_RV610, CHIP_STD, "Radeon HD 2350"},
|
||||
{0x94c1, 2, 0, RADEON_RV610, CHIP_IGP, "Radeon HD 2400"},
|
||||
{0x94c3, 2, 0, RADEON_RV610, CHIP_STD, "Radeon HD 2400"},
|
||||
{0x94cc, 2, 0, RADEON_RV610, CHIP_STD, "Radeon HD 2400"},
|
||||
{0x9586, 2, 0, RADEON_RV630, CHIP_STD, "Radeon HD 2600"},
|
||||
{0x9588, 2, 0, RADEON_RV630, CHIP_STD, "Radeon HD 2600"},
|
||||
{0x958a, 2, 0, RADEON_RV630, CHIP_STD, "Radeon HD 2600 X2"},
|
||||
// Radeon 2700 - RV630
|
||||
{0x9400, 2, 0, RADEON_R600 | 0x00, CHIP_STD, "Radeon HD 2900"},
|
||||
{0x9401, 2, 0, RADEON_R600 | 0x00, CHIP_STD, "Radeon HD 2900"},
|
||||
{0x9402, 2, 0, RADEON_R600 | 0x00, CHIP_STD, "Radeon HD 2900"},
|
||||
{0x9403, 2, 0, RADEON_R600 | 0x00, CHIP_STD, "Radeon HD 2900 Pro"},
|
||||
{0x9405, 2, 0, RADEON_R600 | 0x00, CHIP_STD, "Radeon HD 2900"},
|
||||
{0x940a, 2, 0, RADEON_R600 | 0x00, CHIP_STD, "Radeon FireGL V8650"},
|
||||
{0x940b, 2, 0, RADEON_R600 | 0x00, CHIP_STD, "Radeon FireGL V8600"},
|
||||
{0x940f, 2, 0, RADEON_R600 | 0x00, CHIP_STD, "Radeon FireGL V7600"},
|
||||
{0x9616, 2, 0, RADEON_R600 | 0x10, CHIP_IGP, "Radeon HD 3000"},
|
||||
{0x9611, 3, 0, RADEON_R600 | 0x20, CHIP_IGP, "Radeon HD 3100"},
|
||||
{0x9613, 3, 0, RADEON_R600 | 0x20, CHIP_IGP, "Radeon HD 3100"},
|
||||
{0x9610, 2, 0, RADEON_R600 | 0x10, CHIP_IGP, "Radeon HD 3200"},
|
||||
{0x9612, 2, 0, RADEON_R600 | 0x10, CHIP_IGP, "Radeon HD 3200"},
|
||||
{0x9615, 2, 0, RADEON_R600 | 0x10, CHIP_IGP, "Radeon HD 3200"},
|
||||
{0x9614, 2, 0, RADEON_R600 | 0x10, CHIP_IGP, "Radeon HD 3300"},
|
||||
{0x9400, 2, 0, RADEON_R600, CHIP_STD, "Radeon HD 2900"},
|
||||
{0x9401, 2, 0, RADEON_R600, CHIP_STD, "Radeon HD 2900"},
|
||||
{0x9402, 2, 0, RADEON_R600, CHIP_STD, "Radeon HD 2900"},
|
||||
{0x9403, 2, 0, RADEON_R600, CHIP_STD, "Radeon HD 2900 Pro"},
|
||||
{0x9405, 2, 0, RADEON_R600, CHIP_STD, "Radeon HD 2900"},
|
||||
{0x940a, 2, 0, RADEON_R600, CHIP_STD, "Radeon FireGL V8650"},
|
||||
{0x940b, 2, 0, RADEON_R600, CHIP_STD, "Radeon FireGL V8600"},
|
||||
{0x940f, 2, 0, RADEON_R600, CHIP_STD, "Radeon FireGL V7600"},
|
||||
{0x9616, 2, 0, RADEON_RV610, CHIP_IGP, "Radeon HD 3000"},
|
||||
{0x9611, 3, 0, RADEON_RV620, CHIP_IGP, "Radeon HD 3100"},
|
||||
{0x9613, 3, 0, RADEON_RV620, CHIP_IGP, "Radeon HD 3100"},
|
||||
{0x9610, 2, 0, RADEON_RV610, CHIP_IGP, "Radeon HD 3200"},
|
||||
{0x9612, 2, 0, RADEON_RV610, CHIP_IGP, "Radeon HD 3200"},
|
||||
{0x9615, 2, 0, RADEON_RV610, CHIP_IGP, "Radeon HD 3200"},
|
||||
{0x9614, 2, 0, RADEON_RV610, CHIP_IGP, "Radeon HD 3300"},
|
||||
// Radeon 3430 - RV620
|
||||
{0x95c5, 3, 0, RADEON_R600 | 0x20, CHIP_STD, "Radeon HD 3450"},
|
||||
{0x95c6, 3, 0, RADEON_R600 | 0x20, CHIP_STD, "Radeon HD 3450"},
|
||||
{0x95c7, 3, 0, RADEON_R600 | 0x20, CHIP_STD, "Radeon HD 3450"},
|
||||
{0x95c9, 3, 0, RADEON_R600 | 0x20, CHIP_STD, "Radeon HD 3450"},
|
||||
{0x95c4, 3, 0, RADEON_R600 | 0x20, CHIP_STD, "Radeon HD 3470"},
|
||||
{0x95c0, 3, 0, RADEON_R600 | 0x20, CHIP_STD, "Radeon HD 3550"},
|
||||
{0x9581, 2, 0, RADEON_R600 | 0x30, CHIP_STD, "Radeon HD 3600"},
|
||||
{0x9583, 2, 0, RADEON_R600 | 0x30, CHIP_STD, "Radeon HD 3600"},
|
||||
{0x9598, 2, 0, RADEON_R600 | 0x30, CHIP_STD, "Radeon HD 3600"},
|
||||
{0x9591, 3, 0, RADEON_R600 | 0x35, CHIP_STD, "Radeon HD 3600"},
|
||||
{0x9589, 2, 0, RADEON_R600 | 0x30, CHIP_STD, "Radeon HD 3610"},
|
||||
{0x95c5, 3, 0, RADEON_RV620, CHIP_STD, "Radeon HD 3450"},
|
||||
{0x95c6, 3, 0, RADEON_RV620, CHIP_STD, "Radeon HD 3450"},
|
||||
{0x95c7, 3, 0, RADEON_RV620, CHIP_STD, "Radeon HD 3450"},
|
||||
{0x95c9, 3, 0, RADEON_RV620, CHIP_STD, "Radeon HD 3450"},
|
||||
{0x95c4, 3, 0, RADEON_RV620, CHIP_STD, "Radeon HD 3470"},
|
||||
{0x95c0, 3, 0, RADEON_RV620, CHIP_STD, "Radeon HD 3550"},
|
||||
{0x9581, 2, 0, RADEON_RV630, CHIP_STD, "Radeon HD 3600"},
|
||||
{0x9583, 2, 0, RADEON_RV630, CHIP_STD, "Radeon HD 3600"},
|
||||
{0x9598, 2, 0, RADEON_RV630, CHIP_STD, "Radeon HD 3600"},
|
||||
{0x9591, 3, 0, RADEON_RV635, CHIP_STD, "Radeon HD 3600"},
|
||||
{0x9589, 2, 0, RADEON_RV630, CHIP_STD, "Radeon HD 3610"},
|
||||
// Radeon 3650 - RV635
|
||||
// Radeon 3670 - RV635
|
||||
{0x9507, 2, 0, RADEON_R600 | 0x70, CHIP_STD, "Radeon HD 3830"},
|
||||
{0x9505, 2, 0, RADEON_R600 | 0x70, CHIP_STD, "Radeon HD 3850"},
|
||||
{0x9513, 2, 0, RADEON_R600 | 0x80, CHIP_STD, "Radeon HD 3850 X2"},
|
||||
{0x9501, 2, 0, RADEON_R600 | 0x70, CHIP_STD, "Radeon HD 3870"},
|
||||
{0x950F, 2, 0, RADEON_R600 | 0x80, CHIP_STD, "Radeon HD 3870 X2"},
|
||||
{0x9710, 3, 0, RADEON_R600 | 0x20, CHIP_IGP, "Radeon HD 4200"},
|
||||
{0x9715, 3, 0, RADEON_R600 | 0x20, CHIP_IGP, "Radeon HD 4250"},
|
||||
{0x9712, 3, 0, RADEON_R600 | 0x20, CHIP_IGP, "Radeon HD 4270"},
|
||||
{0x9714, 3, 0, RADEON_R600 | 0x20, CHIP_IGP, "Radeon HD 4290"},
|
||||
{0x9507, 2, 0, RADEON_RV670, CHIP_STD, "Radeon HD 3830"},
|
||||
{0x9505, 2, 0, RADEON_RV670, CHIP_STD, "Radeon HD 3850"},
|
||||
{0x9513, 2, 0, RADEON_RV670, CHIP_STD, "Radeon HD 3850 X2"},
|
||||
{0x9501, 2, 0, RADEON_RV670, CHIP_STD, "Radeon HD 3870"},
|
||||
{0x950F, 2, 0, RADEON_RV670, CHIP_STD, "Radeon HD 3870 X2"},
|
||||
{0x9710, 3, 0, RADEON_RV620, CHIP_IGP, "Radeon HD 4200"},
|
||||
{0x9715, 3, 0, RADEON_RV620, CHIP_IGP, "Radeon HD 4250"},
|
||||
{0x9712, 3, 0, RADEON_RV620, CHIP_IGP, "Radeon HD 4270"},
|
||||
{0x9714, 3, 0, RADEON_RV620, CHIP_IGP, "Radeon HD 4290"},
|
||||
|
||||
// R700 series (HD4330 - HD4890, HD51xx, HD5xxV)
|
||||
// Codename: Wekiva
|
||||
// Radeon 4330 - RV710
|
||||
{0x954f, 3, 2, RADEON_R700 | 0x10, CHIP_IGP, "Radeon HD 4300"},
|
||||
{0x9552, 3, 2, RADEON_R700 | 0x10, CHIP_IGP, "Radeon HD 4300"},
|
||||
{0x9555, 3, 2, RADEON_R700 | 0x10, CHIP_STD, "Radeon HD 4350"},
|
||||
{0x9540, 3, 2, RADEON_R700 | 0x10, CHIP_STD, "Radeon HD 4550"},
|
||||
{0x9480, 3, 2, RADEON_R700 | 0x30, CHIP_STD, "Radeon HD 4650"},
|
||||
{0x9498, 3, 2, RADEON_R700 | 0x30, CHIP_STD, "Radeon HD 4650"},
|
||||
{0x94b4, 3, 2, RADEON_R700 | 0x40, CHIP_STD, "Radeon HD 4700"},
|
||||
{0x9490, 3, 2, RADEON_R700 | 0x30, CHIP_STD, "Radeon HD 4710"},
|
||||
{0x94b3, 3, 2, RADEON_R700 | 0x40, CHIP_STD, "Radeon HD 4770"},
|
||||
{0x94b5, 3, 2, RADEON_R700 | 0x40, CHIP_STD, "Radeon HD 4770"},
|
||||
{0x944a, 3, 1, RADEON_R700 | 0x70, CHIP_MOBILE, "Radeon HD 4850"},
|
||||
{0x944e, 3, 1, RADEON_R700 | 0x70, CHIP_STD, "Radeon HD 4810"},
|
||||
{0x944c, 3, 1, RADEON_R700 | 0x70, CHIP_STD, "Radeon HD 4830"},
|
||||
{0x9442, 3, 1, RADEON_R700 | 0x70, CHIP_STD, "Radeon HD 4850"},
|
||||
{0x9443, 3, 1, RADEON_R700 | 0x70, CHIP_STD, "Radeon HD 4850 X2"},
|
||||
{0x94a1, 3, 1, RADEON_R700 | 0x90, CHIP_IGP, "Radeon HD 4860"},
|
||||
{0x9440, 3, 1, RADEON_R700 | 0x70, CHIP_STD, "Radeon HD 4870"},
|
||||
{0x9441, 3, 1, RADEON_R700 | 0x70, CHIP_STD, "Radeon HD 4870 X2"},
|
||||
{0x9460, 3, 1, RADEON_R700 | 0x90, CHIP_STD, "Radeon HD 4890"},
|
||||
{0x954f, 3, 2, RADEON_RV710, CHIP_IGP, "Radeon HD 4300"},
|
||||
{0x9552, 3, 2, RADEON_RV710, CHIP_IGP, "Radeon HD 4300"},
|
||||
{0x9555, 3, 2, RADEON_RV710, CHIP_STD, "Radeon HD 4350"},
|
||||
{0x9540, 3, 2, RADEON_RV710, CHIP_STD, "Radeon HD 4550"},
|
||||
{0x9480, 3, 2, RADEON_RV730, CHIP_STD, "Radeon HD 4650"},
|
||||
{0x9498, 3, 2, RADEON_RV730, CHIP_STD, "Radeon HD 4650"},
|
||||
{0x94b4, 3, 2, RADEON_RV740, CHIP_STD, "Radeon HD 4700"},
|
||||
{0x9490, 3, 2, RADEON_RV730, CHIP_STD, "Radeon HD 4710"},
|
||||
{0x94b3, 3, 2, RADEON_RV740, CHIP_STD, "Radeon HD 4770"},
|
||||
{0x94b5, 3, 2, RADEON_RV740, CHIP_STD, "Radeon HD 4770"},
|
||||
{0x944a, 3, 1, RADEON_RV770, CHIP_MOBILE, "Radeon HD 4850"},
|
||||
{0x944e, 3, 1, RADEON_RV770, CHIP_STD, "Radeon HD 4810"},
|
||||
{0x944c, 3, 1, RADEON_RV770, CHIP_STD, "Radeon HD 4830"},
|
||||
{0x9442, 3, 1, RADEON_RV770, CHIP_STD, "Radeon HD 4850"},
|
||||
{0x9443, 3, 1, RADEON_RV770, CHIP_STD, "Radeon HD 4850 X2"},
|
||||
{0x94a1, 3, 1, RADEON_RV770, CHIP_IGP, "Radeon HD 4860"},
|
||||
{0x9440, 3, 1, RADEON_RV770, CHIP_STD, "Radeon HD 4870"},
|
||||
{0x9441, 3, 1, RADEON_RV770, CHIP_STD, "Radeon HD 4870 X2"},
|
||||
{0x9460, 3, 1, RADEON_RV770, CHIP_STD, "Radeon HD 4890"},
|
||||
|
||||
// From here on AMD no longer used numeric identifiers
|
||||
|
||||
// R1000 series (HD54xx - HD63xx)
|
||||
// Codename: Evergreen
|
||||
// Cedar
|
||||
{0x68e1, 4, 0, RADEON_R1000 | 0x00, CHIP_STD, "Radeon HD 5430"},
|
||||
{0x68f9, 4, 0, RADEON_R1000 | 0x00, CHIP_STD, "Radeon HD 5450"},
|
||||
{0x68e0, 4, 0, RADEON_R1000 | 0x00, CHIP_IGP, "Radeon HD 5470"},
|
||||
{0x68e1, 4, 0, RADEON_CEDAR, CHIP_STD, "Radeon HD 5430"},
|
||||
{0x68f9, 4, 0, RADEON_CEDAR, CHIP_STD, "Radeon HD 5450"},
|
||||
{0x68e0, 4, 0, RADEON_CEDAR, CHIP_IGP, "Radeon HD 5470"},
|
||||
// Redwood
|
||||
{0x68da, 4, 0, RADEON_R1000 | 0x10, CHIP_STD, "Radeon HD 5500"},
|
||||
{0x68d9, 4, 0, RADEON_R1000 | 0x10, CHIP_STD, "Radeon HD 5570"},
|
||||
{0x68b9, 4, 0, RADEON_R1000 | 0x10, CHIP_STD, "Radeon HD 5600"},
|
||||
{0x68c1, 4, 0, RADEON_R1000 | 0x10, CHIP_STD, "Radeon HD 5650"},
|
||||
{0x68d8, 4, 0, RADEON_R1000 | 0x10, CHIP_STD, "Radeon HD 5670"},
|
||||
{0x68da, 4, 0, RADEON_REDWOOD, CHIP_STD, "Radeon HD 5500"},
|
||||
{0x68d9, 4, 0, RADEON_REDWOOD, CHIP_STD, "Radeon HD 5570"},
|
||||
{0x68b9, 4, 0, RADEON_REDWOOD, CHIP_STD, "Radeon HD 5600"},
|
||||
{0x68c1, 4, 0, RADEON_REDWOOD, CHIP_STD, "Radeon HD 5650"},
|
||||
{0x68d8, 4, 0, RADEON_REDWOOD, CHIP_STD, "Radeon HD 5670"},
|
||||
// Juniper
|
||||
{0x68be, 4, 0, RADEON_R1000 | 0x20, CHIP_STD, "Radeon HD 5700"},
|
||||
{0x68b8, 4, 0, RADEON_R1000 | 0x20, CHIP_STD, "Radeon HD 5770"},
|
||||
{0x68be, 4, 0, RADEON_JUNIPER, CHIP_STD, "Radeon HD 5700"},
|
||||
{0x68b8, 4, 0, RADEON_JUNIPER, CHIP_STD, "Radeon HD 5770"},
|
||||
// Cypress
|
||||
{0x689e, 4, 0, RADEON_R1000 | 0x30, CHIP_STD, "Radeon HD 5800"},
|
||||
{0x6899, 4, 0, RADEON_R1000 | 0x30, CHIP_STD, "Radeon HD 5850"},
|
||||
{0x6898, 4, 0, RADEON_R1000 | 0x30, CHIP_STD, "Radeon HD 5870"},
|
||||
{0x689e, 4, 0, RADEON_CYPRESS, CHIP_STD, "Radeon HD 5800"},
|
||||
{0x6899, 4, 0, RADEON_CYPRESS, CHIP_STD, "Radeon HD 5850"},
|
||||
{0x6898, 4, 0, RADEON_CYPRESS, CHIP_STD, "Radeon HD 5870"},
|
||||
// Hemlock
|
||||
{0x689c, 4, 0, RADEON_R1000 | 0x40, CHIP_STD, "Radeon HD 5900"},
|
||||
{0x689c, 4, 0, RADEON_HEMLOCK, CHIP_STD, "Radeon HD 5900"},
|
||||
// Fusion APUS
|
||||
// Palms
|
||||
{0x9804, 4, 1, RADEON_R1000 | 0x50, CHIP_APU, "Radeon HD 6250"},
|
||||
{0x9805, 4, 1, RADEON_R1000 | 0x50, CHIP_APU, "Radeon HD 6290"},
|
||||
{0x9802, 4, 1, RADEON_R1000 | 0x50, CHIP_APU, "Radeon HD 6310"},
|
||||
{0x9803, 4, 1, RADEON_R1000 | 0x50, CHIP_APU, "Radeon HD 6310"},
|
||||
{0x9804, 4, 1, RADEON_PALM, CHIP_APU, "Radeon HD 6250"},
|
||||
{0x9805, 4, 1, RADEON_PALM, CHIP_APU, "Radeon HD 6290"},
|
||||
{0x9802, 4, 1, RADEON_PALM, CHIP_APU, "Radeon HD 6310"},
|
||||
{0x9803, 4, 1, RADEON_PALM, CHIP_APU, "Radeon HD 6310"},
|
||||
|
||||
// R2000 series (HD64xx - HD69xx)
|
||||
// Codename: Nothern Islands
|
||||
// Caicos
|
||||
{0x6760, 5, 0, RADEON_R2000 | 0x00, CHIP_MOBILE, "Radeon HD 6470M"},
|
||||
{0x6761, 5, 0, RADEON_R2000 | 0x00, CHIP_MOBILE, "Radeon HD 6430M"},
|
||||
{0x6762, 5, 0, RADEON_R2000 | 0x00, CHIP_STD, "Radeon HD CAICOS"},
|
||||
{0x6763, 5, 0, RADEON_R2000 | 0x00, CHIP_DISCREET, "Radeon HD E6460"},
|
||||
{0x6764, 5, 0, RADEON_R2000 | 0x00, CHIP_STD, "Radeon HD CAICOS"},
|
||||
{0x6765, 5, 0, RADEON_R2000 | 0x00, CHIP_STD, "Radeon HD CAICOS"},
|
||||
{0x6766, 5, 0, RADEON_R2000 | 0x00, CHIP_STD, "Radeon HD CAICOS"},
|
||||
{0x6767, 5, 0, RADEON_R2000 | 0x00, CHIP_STD, "Radeon HD CAICOS"},
|
||||
{0x6768, 5, 0, RADEON_R2000 | 0x00, CHIP_STD, "Radeon HD CAICOS"},
|
||||
{0x6770, 5, 0, RADEON_R2000 | 0x00, CHIP_STD, "Radeon HD 6400"},
|
||||
{0x6779, 5, 0, RADEON_R2000 | 0x00, CHIP_STD, "Radeon HD 6450"},
|
||||
{0x6760, 5, 0, RADEON_CAICOS, CHIP_MOBILE, "Radeon HD 6470M"},
|
||||
{0x6761, 5, 0, RADEON_CAICOS, CHIP_MOBILE, "Radeon HD 6430M"},
|
||||
{0x6762, 5, 0, RADEON_CAICOS, CHIP_STD, "Radeon HD CAICOS"},
|
||||
{0x6763, 5, 0, RADEON_CAICOS, CHIP_DISCREET, "Radeon HD E6460"},
|
||||
{0x6764, 5, 0, RADEON_CAICOS, CHIP_STD, "Radeon HD CAICOS"},
|
||||
{0x6765, 5, 0, RADEON_CAICOS, CHIP_STD, "Radeon HD CAICOS"},
|
||||
{0x6766, 5, 0, RADEON_CAICOS, CHIP_STD, "Radeon HD CAICOS"},
|
||||
{0x6767, 5, 0, RADEON_CAICOS, CHIP_STD, "Radeon HD CAICOS"},
|
||||
{0x6768, 5, 0, RADEON_CAICOS, CHIP_STD, "Radeon HD CAICOS"},
|
||||
{0x6770, 5, 0, RADEON_CAICOS, CHIP_STD, "Radeon HD 6400"},
|
||||
{0x6779, 5, 0, RADEON_CAICOS, CHIP_STD, "Radeon HD 6450"},
|
||||
// Turks
|
||||
{0x6740, 5, 0, RADEON_R2000 | 0x10, CHIP_MOBILE, "Radeon HD 6700M"},
|
||||
{0x6741, 5, 0, RADEON_R2000 | 0x10, CHIP_MOBILE, "Radeon HD 6600M"},
|
||||
{0x6742, 5, 0, RADEON_R2000 | 0x10, CHIP_MOBILE, "Radeon HD 6625M"},
|
||||
{0x6743, 5, 0, RADEON_R2000 | 0x10, CHIP_DISCREET, "Radeon HD E6760"},
|
||||
{0x6744, 5, 0, RADEON_R2000 | 0x10, CHIP_MOBILE, "Radeon HD TURKS M"},
|
||||
{0x6745, 5, 0, RADEON_R2000 | 0x10, CHIP_MOBILE, "Radeon HD TURKS M"},
|
||||
{0x6746, 5, 0, RADEON_R2000 | 0x10, CHIP_STD, "Radeon HD TURKS"},
|
||||
{0x6747, 5, 0, RADEON_R2000 | 0x10, CHIP_STD, "Radeon HD TURKS"},
|
||||
{0x6748, 5, 0, RADEON_R2000 | 0x10, CHIP_STD, "Radeon HD TURKS"},
|
||||
{0x6749, 5, 0, RADEON_R2000 | 0x10, CHIP_STD, "FirePro v4900"},
|
||||
{0x6759, 5, 0, RADEON_R2000 | 0x10, CHIP_STD, "Radeon HD 6570"},
|
||||
{0x6740, 5, 0, RADEON_TURKS, CHIP_MOBILE, "Radeon HD 6700M"},
|
||||
{0x6741, 5, 0, RADEON_TURKS, CHIP_MOBILE, "Radeon HD 6600M"},
|
||||
{0x6742, 5, 0, RADEON_TURKS, CHIP_MOBILE, "Radeon HD 6625M"},
|
||||
{0x6743, 5, 0, RADEON_TURKS, CHIP_DISCREET, "Radeon HD E6760"},
|
||||
{0x6744, 5, 0, RADEON_TURKS, CHIP_MOBILE, "Radeon HD TURKS M"},
|
||||
{0x6745, 5, 0, RADEON_TURKS, CHIP_MOBILE, "Radeon HD TURKS M"},
|
||||
{0x6746, 5, 0, RADEON_TURKS, CHIP_STD, "Radeon HD TURKS"},
|
||||
{0x6747, 5, 0, RADEON_TURKS, CHIP_STD, "Radeon HD TURKS"},
|
||||
{0x6748, 5, 0, RADEON_TURKS, CHIP_STD, "Radeon HD TURKS"},
|
||||
{0x6749, 5, 0, RADEON_TURKS, CHIP_STD, "FirePro v4900"},
|
||||
{0x6759, 5, 0, RADEON_TURKS, CHIP_STD, "Radeon HD 6570"},
|
||||
// Barts
|
||||
{0x673e, 5, 0, RADEON_R2000 | 0x20, CHIP_STD, "Radeon HD 6790"},
|
||||
{0x6739, 5, 0, RADEON_R2000 | 0x20, CHIP_STD, "Radeon HD 6850"},
|
||||
{0x6738, 5, 0, RADEON_R2000 | 0x20, CHIP_STD, "Radeon HD 6870"},
|
||||
{0x673e, 5, 0, RADEON_BARTS, CHIP_STD, "Radeon HD 6790"},
|
||||
{0x6739, 5, 0, RADEON_BARTS, CHIP_STD, "Radeon HD 6850"},
|
||||
{0x6738, 5, 0, RADEON_BARTS, CHIP_STD, "Radeon HD 6870"},
|
||||
// Cayman
|
||||
{0x6700, 5, 0, RADEON_R2000 | 0x30, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6701, 5, 0, RADEON_R2000 | 0x30, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6702, 5, 0, RADEON_R2000 | 0x30, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6703, 5, 0, RADEON_R2000 | 0x30, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6704, 5, 0, RADEON_R2000 | 0x30, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6705, 5, 0, RADEON_R2000 | 0x30, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6706, 5, 0, RADEON_R2000 | 0x30, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6707, 5, 0, RADEON_R2000 | 0x30, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6708, 5, 0, RADEON_R2000 | 0x30, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6709, 5, 0, RADEON_R2000 | 0x30, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6718, 5, 0, RADEON_R2000 | 0x30, CHIP_STD, "Radeon HD 6970"},
|
||||
{0x6719, 5, 0, RADEON_R2000 | 0x30, CHIP_STD, "Radeon HD 6950"},
|
||||
{0x671C, 5, 0, RADEON_R2000 | 0x30, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x671F, 5, 0, RADEON_R2000 | 0x30, CHIP_STD, "Radeon HD 6900"},
|
||||
{0x6700, 5, 0, RADEON_CAYMAN, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6701, 5, 0, RADEON_CAYMAN, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6702, 5, 0, RADEON_CAYMAN, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6703, 5, 0, RADEON_CAYMAN, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6704, 5, 0, RADEON_CAYMAN, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6705, 5, 0, RADEON_CAYMAN, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6706, 5, 0, RADEON_CAYMAN, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6707, 5, 0, RADEON_CAYMAN, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6708, 5, 0, RADEON_CAYMAN, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6709, 5, 0, RADEON_CAYMAN, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x6718, 5, 0, RADEON_CAYMAN, CHIP_STD, "Radeon HD 6970"},
|
||||
{0x6719, 5, 0, RADEON_CAYMAN, CHIP_STD, "Radeon HD 6950"},
|
||||
{0x671C, 5, 0, RADEON_CAYMAN, CHIP_STD, "Radeon HD CAYMAN"},
|
||||
{0x671F, 5, 0, RADEON_CAYMAN, CHIP_STD, "Radeon HD 6900"},
|
||||
// Antilles
|
||||
{0x671d, 5, 0, RADEON_R2000 | 0x40, CHIP_STD, "Radeon HD 6990"}
|
||||
{0x671d, 5, 0, RADEON_ANTILLES, CHIP_STD, "Radeon HD 6990"}
|
||||
|
||||
// R3000 series (HD74xx - HD79xx)
|
||||
// Codename: Southern Islands
|
||||
// Lombok
|
||||
// R3000 | 0x00
|
||||
// Thames
|
||||
// R3000 | 0x10
|
||||
// Tahiti
|
||||
// R3000 | 0x20
|
||||
// New Zealand
|
||||
// R3000 | 0x30
|
||||
};
|
||||
|
||||
|
||||
|
||||
@@ -481,7 +481,7 @@ radeon_hd_init(radeon_info &info)
|
||||
mmioMapper.Detach();
|
||||
|
||||
// *** Populate frame buffer information
|
||||
if (info.shared_info->device_chipset >= RADEON_R1000) {
|
||||
if (info.shared_info->device_chipset >= RADEON_CEDAR) {
|
||||
// Evergreen+ has memory stored in MB
|
||||
info.shared_info->graphics_memory_size
|
||||
= read32(info.registers + CONFIG_MEMSIZE) * 1024;
|
||||
@@ -546,12 +546,13 @@ radeon_hd_init(radeon_info &info)
|
||||
|
||||
if (biosStatus != B_OK) {
|
||||
// If the active read fails, we try a disabled read
|
||||
if (info.device_chipset >= (RADEON_R1000 | 0x20))
|
||||
if (info.device_chipset >= RADEON_BARTS)
|
||||
biosStatus = radeon_hd_getbios_ni(info);
|
||||
else if (info.device_chipset >= RADEON_R700)
|
||||
else if (info.device_chipset >= RADEON_RV770)
|
||||
biosStatus = radeon_hd_getbios_r700(info);
|
||||
else if (info.device_chipset >= RADEON_R600)
|
||||
biosStatus = radeon_hd_getbios_r600(info);
|
||||
// else avivo_read_disabled_bios
|
||||
}
|
||||
|
||||
if (biosStatus != B_OK) {
|
||||
|
||||
Reference in New Issue
Block a user