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intel_extreme: added DDI link colordepth detection, may fix ticket #17439

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This commit is contained in:
Rudolf Cornelissen
2021-12-04 23:24:50 +00:00
parent a33640cc6b
commit 77b2dd17df
2 changed files with 29 additions and 2 deletions
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headers/private/graphics/intel_extreme/intel_extreme.h
+7
View File
@@ -755,6 +755,13 @@ struct intel_free_graphics_memory {
#define PIPE_DDI_MODE_DVI 1
#define PIPE_DDI_MODE_DP_SST 2
#define PIPE_DDI_MODE_DP_MST 3
#define PIPE_DDI_COLOR_SHIFT 20
#define PIPE_DDI_BPC(x) ((x) << PIPE_DDI_COLOR_SHIFT)
#define PIPE_DDI_BPC_MASK (7 << PIPE_DDI_COLOR_SHIFT)
#define PIPE_DDI_8BPC 0
#define PIPE_DDI_10BPC 1
#define PIPE_DDI_6BPC 2
#define PIPE_DDI_12BPC 3
#define PIPE_DDI_DP_WIDTH_SHIFT 1
#define PIPE_DDI_DP_WIDTH_SEL(x) ((x) << PIPE_DDI_DP_WIDTH_SHIFT)
#define PIPE_DDI_DP_WIDTH_MASK (7 << PIPE_DDI_DP_WIDTH_SHIFT)
src/add-ons/accelerants/intel_extreme/Ports.cpp
+22 -2
View File
@@ -1443,6 +1443,7 @@ DigitalDisplayInterface::_SetPortLinkGen8(const display_timing& timing)
//uint32 linkBandwidth = gInfo->shared_info->fdi_link_frequency * 1000 / 10; //=270000 khz
//fixme: always so?
uint32 linkBandwidth = 270000; //khz
uint32 fPipeOffset = 0;
switch (fPipe->Index()) {
case INTEL_PIPE_B:
@@ -1463,10 +1464,29 @@ DigitalDisplayInterface::_SetPortLinkGen8(const display_timing& timing)
TRACE("%s: DDI M1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_LINK_M + fPipeOffset));
TRACE("%s: DDI N1 link before: 0x%" B_PRIx32 "\n", __func__, read32(INTEL_DDI_PIPE_A_LINK_N + fPipeOffset));
uint32 bitsPerPixel = 24; //fixme: always so?
uint32 pipeFunc = read32(PIPE_DDI_FUNC_CTL_A + fPipeOffset);
uint32 bitsPerPixel = (pipeFunc & PIPE_DDI_BPC_MASK) >> PIPE_DDI_COLOR_SHIFT;
switch (bitsPerPixel) {
case PIPE_DDI_8BPC:
bitsPerPixel = 24;
break;
case PIPE_DDI_10BPC:
bitsPerPixel = 30;
break;
case PIPE_DDI_6BPC:
bitsPerPixel = 18;
break;
case PIPE_DDI_12BPC:
bitsPerPixel = 36;
break;
default:
ERROR("%s: DDI illegal link colordepth set.\n", __func__);
return B_ERROR;
}
TRACE("%s: DDI Link Colordepth: %" B_PRIu32 "\n", __func__, bitsPerPixel);
uint32 lanes = 4;
// Only DP modes supports less than 4 lanes: read current config
uint32 pipeFunc = read32(PIPE_DDI_FUNC_CTL_A + fPipeOffset);
if (((pipeFunc & PIPE_DDI_MODESEL_MASK) >> PIPE_DDI_MODESEL_SHIFT) >= PIPE_DDI_MODE_DP_SST) {
// On gen 9.5 IceLake 3x mode exists (DSI only), earlier models: reserved value.
lanes = ((pipeFunc & PIPE_DDI_DP_WIDTH_MASK) >> PIPE_DDI_DP_WIDTH_SHIFT) + 1;