boot/platform: Break x86 code away from core EFI code
Change-Id: I88afad6d071e8b577c23da9c60392c60b3726514 Reviewed-on: https://review.haiku-os.org/c/haiku/+/1895 Reviewed-by: Alex von Gluck IV <[email protected]> Reviewed-by: Adrien Destugues <[email protected]>
This commit is contained in:
Alexander von Gluck IV
committed by
Alex von Gluck IV
Alex von Gluck IV
parent
f17664c8b1
commit
7c32619c7f
@@ -0,0 +1,12 @@
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/*
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* Copyright 2013-2019 Haiku, Inc. All rights reserved.
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* Distributed under the terms of the MIT License.
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*/
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#ifndef KERNEL_BOOT_PLATFORM_EFI_ARCH_MMU_H
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#define KERNEL_BOOT_PLATFORM_EFI_ARCH_MMU_H
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void arch_mmu_init();
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#endif /* KERNEL_BOOT_PLATFORM_EFI_ARCH_MMU_H */
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@@ -0,0 +1,18 @@
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/*
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* Copyright 2013-2019 Haiku, Inc. All rights reserved.
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* Distributed under the terms of the MIT License.
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*/
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#ifndef KERNEL_BOOT_PLATFORM_EFI_ARCH_SMP_H
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#define KERNEL_BOOT_PLATFORM_EFI_ARCH_SMP_H
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#include <boot/menu.h>
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int arch_smp_get_current_cpu(void);
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void arch_smp_init_other_cpus(void);
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void arch_smp_boot_other_cpus(uint32 pml4, uint64 kernel_entry);
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void arch_smp_add_safemode_menus(Menu *menu);
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void arch_smp_init(void);
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#endif /* KERNEL_BOOT_PLATFORM_EFI_ARCH_SMP_H */
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@@ -1,6 +1,8 @@
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SubDir HAIKU_TOP src system boot platform efi ;
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UsePrivateHeaders [ FDirName kernel boot ] ;
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UsePrivateHeaders [ FDirName kernel boot platform efi ] ;
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UsePrivateHeaders [ FDirName kernel arch $(TARGET_KERNEL_ARCH) ] ;
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UseBuildFeatureHeaders gnuefi ;
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UseBuildFeatureHeaders gnuefi : headersProtocol ;
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UseBuildFeatureHeaders gnuefi : headersArch ;
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@@ -36,6 +38,8 @@ local platform_src =
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;
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local arch_src =
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arch_mmu.cpp
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arch_smp.cpp
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relocation_func.cpp
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entry.S
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;
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@@ -0,0 +1,44 @@
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/*
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* Copyright 2014-2016 Haiku, Inc. All rights reserved.
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* Copyright 2013-2014, Fredrik Holmqvist, [email protected].
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* Copyright 2014, Henry Harrington, [email protected].
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* All rights reserved.
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* Distributed under the terms of the MIT License.
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*/
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#include <boot/platform.h>
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#include <arch/x86/descriptors.h>
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extern uint64 gLongGDT;
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extern uint64 gLongGDTR;
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segment_descriptor gBootGDT[BOOT_GDT_SEGMENT_COUNT];
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static void
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long_gdt_init()
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{
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clear_segment_descriptor(&gBootGDT[0]);
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// Set up code/data segments (TSS segments set up later in the kernel).
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set_segment_descriptor(&gBootGDT[KERNEL_CODE_SEGMENT], DT_CODE_EXECUTE_ONLY,
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DPL_KERNEL);
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set_segment_descriptor(&gBootGDT[KERNEL_DATA_SEGMENT], DT_DATA_WRITEABLE,
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DPL_KERNEL);
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set_segment_descriptor(&gBootGDT[USER_CODE_SEGMENT], DT_CODE_EXECUTE_ONLY,
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DPL_USER);
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set_segment_descriptor(&gBootGDT[USER_DATA_SEGMENT], DT_DATA_WRITEABLE,
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DPL_USER);
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// Used by long_enter_kernel().
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gLongGDT = (addr_t)gBootGDT + 0xFFFFFF0000000000;
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dprintf("GDT at 0x%lx\n", gLongGDT);
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}
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void
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arch_mmu_init()
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{
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long_gdt_init();
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}
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@@ -0,0 +1,455 @@
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/*
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* Copyright 2008, Dustin Howett, [email protected]. All rights reserved.
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* Copyright 2004-2010, Axel Dörfler, [email protected].
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* Distributed under the terms of the MIT License.
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*
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* Copyright 2001, Travis Geiselbrecht. All rights reserved.
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* Distributed under the terms of the NewOS License.
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*/
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#include "arch_smp.h"
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#include <string.h>
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#include <KernelExport.h>
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#include <kernel.h>
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#include <safemode.h>
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#include <boot/platform.h>
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#include <boot/stage2.h>
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#include <boot/menu.h>
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#include <arch/x86/apic.h>
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#include <arch/x86/arch_acpi.h>
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#include <arch/x86/arch_cpu.h>
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#include <arch/x86/arch_smp.h>
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#include <arch/x86/arch_system_info.h>
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#include <arch/x86/descriptors.h>
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#include "mmu.h"
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#include "acpi.h"
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#define NO_SMP 0
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//#define TRACE_SMP
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#ifdef TRACE_SMP
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# define TRACE(x) dprintf x
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#else
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# define TRACE(x) ;
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#endif
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extern "C" void execute_n_instructions(int count);
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extern "C" void smp_trampoline(void);
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extern "C" void smp_trampoline_args(void);
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extern "C" void smp_trampoline_end(void);
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extern "C" uint64 gLongGDTR;
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struct gdtr {
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uint16 limit;
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uint32 base;
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unsigned char null[8];
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unsigned char code[8];
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unsigned char data[8];
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} __attribute__((packed));
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// Arguments passed to the SMP trampoline.
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struct trampoline_args {
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uint32 trampoline; // Trampoline address
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uint32 gdt32; // 32-bit GDTR
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uint32 pml4; // 64-bit PML4
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uint32 gdt64; // 64-bit GDTR
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uint64 kernel_entry; // Kernel entry point
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uint64 kernel_args; // Kernel arguments
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uint64 current_cpu; // CPU number
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uint64 stack_top; // Kernel stack
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volatile uint64 sentinel; // Sentinel, AP sets to 0 when finished
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// smp_boot_other_cpus puts the GDTR here.
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struct gdtr gdtr;
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};
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static uint32
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apic_read(uint32 offset)
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{
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return *(volatile uint32 *)((addr_t)gKernelArgs.arch_args.apic_phys + offset);
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}
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static void
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apic_write(uint32 offset, uint32 data)
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{
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*(volatile uint32 *)((addr_t)gKernelArgs.arch_args.apic_phys + offset) = data;
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}
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static status_t
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acpi_do_smp_config(void)
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{
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TRACE(("smp: using ACPI to detect MP configuration\n"));
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// reset CPU count
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gKernelArgs.num_cpus = 0;
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acpi_madt *madt = (acpi_madt *)acpi_find_table(ACPI_MADT_SIGNATURE);
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if (madt == NULL) {
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TRACE(("smp: Failed to find MADT!\n"));
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return B_ERROR;
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}
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gKernelArgs.arch_args.apic_phys = madt->local_apic_address;
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TRACE(("smp: local apic address is 0x%" B_PRIx32 "\n", madt->local_apic_address));
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acpi_apic *apic = (acpi_apic *)((uint8 *)madt + sizeof(acpi_madt));
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acpi_apic *end = (acpi_apic *)((uint8 *)madt + madt->header.length);
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while (apic < end) {
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switch (apic->type) {
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case ACPI_MADT_LOCAL_APIC:
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{
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if (gKernelArgs.num_cpus == SMP_MAX_CPUS) {
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TRACE(("smp: already reached maximum CPUs (%d)\n",
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SMP_MAX_CPUS));
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break;
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}
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acpi_local_apic *localApic = (acpi_local_apic *)apic;
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TRACE(("smp: found local APIC with id %u\n",
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localApic->apic_id));
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if ((localApic->flags & ACPI_LOCAL_APIC_ENABLED) == 0) {
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TRACE(("smp: APIC is disabled and will not be used\n"));
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break;
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}
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gKernelArgs.arch_args.cpu_apic_id[gKernelArgs.num_cpus]
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= localApic->apic_id;
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// TODO: how to find out? putting 0x10 in to indicate a local apic
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gKernelArgs.arch_args.cpu_apic_version[gKernelArgs.num_cpus]
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= 0x10;
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gKernelArgs.num_cpus++;
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break;
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}
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case ACPI_MADT_IO_APIC: {
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acpi_io_apic *ioApic = (acpi_io_apic *)apic;
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TRACE(("smp: found io APIC with id %" B_PRIu32 " and address 0x%" B_PRIx32 "\n",
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ioApic->io_apic_id, ioApic->io_apic_address));
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if (gKernelArgs.arch_args.ioapic_phys == 0)
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gKernelArgs.arch_args.ioapic_phys = ioApic->io_apic_address;
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break;
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}
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default:
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break;
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}
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apic = (acpi_apic *)((uint8 *)apic + apic->length);
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}
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return gKernelArgs.num_cpus > 0 ? B_OK : B_ERROR;
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}
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static void
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calculate_apic_timer_conversion_factor(void)
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{
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int64 t1, t2;
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uint32 config;
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uint32 count;
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TRACE(("calculating apic timer conversion factor\n"));
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// setup the timer
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config = apic_read(APIC_LVT_TIMER);
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config = (config & APIC_LVT_TIMER_MASK) + APIC_LVT_MASKED;
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// timer masked, vector 0
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apic_write(APIC_LVT_TIMER, config);
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config = (apic_read(APIC_TIMER_DIVIDE_CONFIG) & ~0x0000000f);
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apic_write(APIC_TIMER_DIVIDE_CONFIG, config | APIC_TIMER_DIVIDE_CONFIG_1);
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// divide clock by one
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t1 = system_time();
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apic_write(APIC_INITIAL_TIMER_COUNT, 0xffffffff); // start the counter
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execute_n_instructions(128 * 20000);
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count = apic_read(APIC_CURRENT_TIMER_COUNT);
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t2 = system_time();
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count = 0xffffffff - count;
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gKernelArgs.arch_args.apic_time_cv_factor
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= (uint32)((1000000.0/(t2 - t1)) * count);
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TRACE(("APIC ticks/sec = %" B_PRId32 "\n",
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gKernelArgs.arch_args.apic_time_cv_factor));
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}
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// #pragma mark -
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int
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arch_smp_get_current_cpu(void)
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{
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if (gKernelArgs.arch_args.apic == NULL)
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return 0;
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uint8 apicID = apic_read(APIC_ID) >> 24;
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for (uint32 i = 0; i < gKernelArgs.num_cpus; i++) {
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if (gKernelArgs.arch_args.cpu_apic_id[i] == apicID)
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return i;
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}
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return 0;
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}
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void
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arch_smp_init_other_cpus(void)
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{
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if (get_safemode_boolean(B_SAFEMODE_DISABLE_SMP, false)) {
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// SMP has been disabled!
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TRACE(("smp disabled per safemode setting\n"));
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gKernelArgs.num_cpus = 1;
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}
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if (get_safemode_boolean(B_SAFEMODE_DISABLE_APIC, false)) {
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TRACE(("local apic disabled per safemode setting, disabling smp\n"));
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gKernelArgs.arch_args.apic_phys = 0;
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gKernelArgs.num_cpus = 1;
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}
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if (gKernelArgs.arch_args.apic_phys == 0)
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return;
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TRACE(("smp: found %" B_PRId32 " cpu%s\n", gKernelArgs.num_cpus,
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gKernelArgs.num_cpus != 1 ? "s" : ""));
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TRACE(("smp: apic_phys = %lx\n", (addr_t)gKernelArgs.arch_args.apic_phys));
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TRACE(("smp: ioapic_phys = %lx\n",
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(addr_t)gKernelArgs.arch_args.ioapic_phys));
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// map in the apic
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gKernelArgs.arch_args.apic = (void *)mmu_map_physical_memory(
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gKernelArgs.arch_args.apic_phys, B_PAGE_SIZE, kDefaultPageFlags);
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TRACE(("smp: apic (mapped) = %lx\n", (addr_t)gKernelArgs.arch_args.apic.Pointer()));
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// calculate how fast the apic timer is
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calculate_apic_timer_conversion_factor();
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if (gKernelArgs.num_cpus < 2)
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return;
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for (uint32 i = 1; i < gKernelArgs.num_cpus; i++) {
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// create a final stack the trampoline code will put the ap processor on
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void * stack = NULL;
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const size_t size = KERNEL_STACK_SIZE + KERNEL_STACK_GUARD_PAGES * B_PAGE_SIZE;
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if (platform_allocate_region(&stack, size, 0, false) != B_OK) {
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panic("Unable to allocate AP stack");
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}
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memset(stack, 0, size);
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gKernelArgs.cpu_kstack[i].start = fix_address((uint64_t)stack);
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gKernelArgs.cpu_kstack[i].size = size;
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}
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}
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void
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arch_smp_boot_other_cpus(uint32 pml4, uint64 kernel_entry)
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{
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TRACE(("trampolining other cpus\n"));
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// allocate a stack and a code area for the smp trampoline
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// (these have to be < 1M physical, 0xa0000-0xfffff is reserved by the BIOS)
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uint64 trampolineCode = 0x9000;
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uint64 trampolineStack = 0x8000;
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// copy the trampoline code over
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TRACE(("copying the trampoline code to %p from %p\n", (char*)trampolineCode, (const void*)&smp_trampoline));
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TRACE(("size of trampoline code = %lu bytes\n", (uint64)&smp_trampoline_end - (uint64)&smp_trampoline));
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memcpy((char *)trampolineCode, (const void*)&smp_trampoline,
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(uint64)&smp_trampoline_end - (uint64)&smp_trampoline);
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// boot the cpus
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TRACE(("we have %d CPUs to boot...\n", gKernelArgs.num_cpus - 1));
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for (uint32 i = 1; i < gKernelArgs.num_cpus; i++) {
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TRACE(("trampolining CPU %d\n", i));
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uint32 config;
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uint64 numStartups;
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uint32 j;
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trampoline_args* args = (trampoline_args *)trampolineStack;
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args->trampoline = trampolineCode;
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args->gdt32 = (uint64) &args->gdtr;
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args->gdtr.limit = 23;
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args->gdtr.base = (uint32)(uint64)args->gdtr.null;
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#define COPY_ARRAY(A, X0, X1, X2, X3, X4, X5, X6, X7) \
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{ A[0] = X0; A[1] = X1; A[2] = X2; A[3] = X3; A[4] = X4; A[5] = X5; A[6] = X6; A[7] = X7; }
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COPY_ARRAY(args->gdtr.null, 0, 0, 0, 0, 0, 0, 0, 0);
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COPY_ARRAY(args->gdtr.code, 0xff, 0xff, 0, 0, 0, 0x9a, 0xcf, 0);
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COPY_ARRAY(args->gdtr.data, 0xff, 0xff, 0, 0, 0, 0x92, 0xcf, 0);
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#undef COPY_ARRAY
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args->gdt64 = (uint32_t)(uint64_t)&gLongGDTR;
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args->pml4 = pml4;
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args->kernel_entry = kernel_entry;
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args->kernel_args = (uint64)&gKernelArgs;
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args->current_cpu = i;
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args->stack_top = gKernelArgs.cpu_kstack[i].start + gKernelArgs.cpu_kstack[i].size;
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args->sentinel = 1;
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// put the args in the right place
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uint32 * args_ptr =
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(uint32 *)(trampolineCode + (uint64)smp_trampoline_args - (uint64)smp_trampoline);
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*args_ptr = (uint32)(uint64)args;
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/* clear apic errors */
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if (gKernelArgs.arch_args.cpu_apic_version[i] & 0xf0) {
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apic_write(APIC_ERROR_STATUS, 0);
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apic_read(APIC_ERROR_STATUS);
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}
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/* send (aka assert) INIT IPI */
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config = (apic_read(APIC_INTR_COMMAND_2) & APIC_INTR_COMMAND_2_MASK)
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| (gKernelArgs.arch_args.cpu_apic_id[i] << 24);
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apic_write(APIC_INTR_COMMAND_2, config); /* set target pe */
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config = (apic_read(APIC_INTR_COMMAND_1) & 0xfff00000)
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| APIC_TRIGGER_MODE_LEVEL | APIC_INTR_COMMAND_1_ASSERT
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| APIC_DELIVERY_MODE_INIT;
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apic_write(APIC_INTR_COMMAND_1, config);
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// wait for pending to end
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while ((apic_read(APIC_INTR_COMMAND_1) & APIC_DELIVERY_STATUS) != 0)
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asm volatile ("pause;");
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/* deassert INIT */
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config = (apic_read(APIC_INTR_COMMAND_2) & APIC_INTR_COMMAND_2_MASK)
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| (gKernelArgs.arch_args.cpu_apic_id[i] << 24);
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apic_write(APIC_INTR_COMMAND_2, config);
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config = (apic_read(APIC_INTR_COMMAND_1) & 0xfff00000)
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| APIC_TRIGGER_MODE_LEVEL | APIC_DELIVERY_MODE_INIT;
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apic_write(APIC_INTR_COMMAND_1, config);
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// wait for pending to end
|
||||
while ((apic_read(APIC_INTR_COMMAND_1) & APIC_DELIVERY_STATUS) != 0)
|
||||
asm volatile ("pause;");
|
||||
|
||||
/* wait 10ms */
|
||||
spin(10000);
|
||||
/* is this a local apic or an 82489dx ? */
|
||||
numStartups = (gKernelArgs.arch_args.cpu_apic_version[i] & 0xf0)
|
||||
? 2 : 0;
|
||||
for (j = 0; j < numStartups; j++) {
|
||||
/* it's a local apic, so send STARTUP IPIs */
|
||||
apic_write(APIC_ERROR_STATUS, 0);
|
||||
|
||||
/* set target pe */
|
||||
config = (apic_read(APIC_INTR_COMMAND_2) & APIC_INTR_COMMAND_2_MASK)
|
||||
| (gKernelArgs.arch_args.cpu_apic_id[i] << 24);
|
||||
apic_write(APIC_INTR_COMMAND_2, config);
|
||||
|
||||
/* send the IPI */
|
||||
config = (apic_read(APIC_INTR_COMMAND_1) & 0xfff0f800)
|
||||
| APIC_DELIVERY_MODE_STARTUP | (trampolineCode >> 12);
|
||||
apic_write(APIC_INTR_COMMAND_1, config);
|
||||
|
||||
/* wait */
|
||||
spin(200);
|
||||
|
||||
while ((apic_read(APIC_INTR_COMMAND_1) & APIC_DELIVERY_STATUS) != 0)
|
||||
asm volatile ("pause;");
|
||||
}
|
||||
|
||||
// Wait for the trampoline code to clear the final stack location.
|
||||
// This serves as a notification for us that it has loaded the address
|
||||
// and it is safe for us to overwrite it to trampoline the next CPU.
|
||||
while (args->sentinel != 0)
|
||||
spin(1000);
|
||||
}
|
||||
|
||||
TRACE(("done trampolining\n"));
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
arch_smp_add_safemode_menus(Menu *menu)
|
||||
{
|
||||
MenuItem *item;
|
||||
|
||||
if (gKernelArgs.arch_args.ioapic_phys != 0) {
|
||||
menu->AddItem(item = new(nothrow) MenuItem("Disable IO-APIC"));
|
||||
item->SetType(MENU_ITEM_MARKABLE);
|
||||
item->SetData(B_SAFEMODE_DISABLE_IOAPIC);
|
||||
item->SetHelpText("Disables using the IO APIC for interrupt routing, "
|
||||
"forcing the use of the legacy PIC instead.");
|
||||
}
|
||||
|
||||
if (gKernelArgs.arch_args.apic_phys != 0) {
|
||||
menu->AddItem(item = new(nothrow) MenuItem("Disable local APIC"));
|
||||
item->SetType(MENU_ITEM_MARKABLE);
|
||||
item->SetData(B_SAFEMODE_DISABLE_APIC);
|
||||
item->SetHelpText("Disables using the local APIC, also disables SMP.");
|
||||
|
||||
cpuid_info info;
|
||||
if (get_current_cpuid(&info, 1, 0) == B_OK
|
||||
&& (info.regs.ecx & IA32_FEATURE_EXT_X2APIC) != 0) {
|
||||
menu->AddItem(item = new(nothrow) MenuItem("Disable X2APIC"));
|
||||
item->SetType(MENU_ITEM_MARKABLE);
|
||||
item->SetData(B_SAFEMODE_DISABLE_X2APIC);
|
||||
item->SetHelpText("Disables using X2APIC.");
|
||||
}
|
||||
|
||||
if (get_current_cpuid(&info, 7, 0) == B_OK
|
||||
&& ((info.regs.ebx & (IA32_FEATURE_SMEP
|
||||
| IA32_FEATURE_SMAP)) != 0)) {
|
||||
menu->AddItem(item = new(nothrow) MenuItem(
|
||||
"Disable SMEP and SMAP"));
|
||||
item->SetType(MENU_ITEM_MARKABLE);
|
||||
item->SetData(B_SAFEMODE_DISABLE_SMEP_SMAP);
|
||||
item->SetHelpText("Disables using SMEP and SMAP.");
|
||||
}
|
||||
}
|
||||
|
||||
if (gKernelArgs.num_cpus < 2)
|
||||
return;
|
||||
|
||||
item = new(nothrow) MenuItem("Disable SMP");
|
||||
menu->AddItem(item);
|
||||
item->SetData(B_SAFEMODE_DISABLE_SMP);
|
||||
item->SetType(MENU_ITEM_MARKABLE);
|
||||
item->SetHelpText("Disables all but one CPU core.");
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
arch_smp_init(void)
|
||||
{
|
||||
cpuid_info info;
|
||||
if (get_current_cpuid(&info, 1, 0) != B_OK)
|
||||
return;
|
||||
|
||||
if ((info.eax_1.features & IA32_FEATURE_APIC) == 0) {
|
||||
// Local APICs aren't present; As they form the basis for all inter CPU
|
||||
// communication and therefore SMP, we don't need to go any further.
|
||||
TRACE(("no local APIC present, not attempting SMP init\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
// first try to find ACPI tables to get MP configuration as it handles
|
||||
// physical as well as logical MP configurations as in multiple cpus,
|
||||
// multiple cores or hyper threading.
|
||||
if (acpi_do_smp_config() == B_OK) {
|
||||
TRACE(("smp init success\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
// Everything failed or we are not running an SMP system, reset anything
|
||||
// that might have been set through an incomplete configuration attempt.
|
||||
gKernelArgs.arch_args.apic_phys = 0;
|
||||
gKernelArgs.arch_args.ioapic_phys = 0;
|
||||
gKernelArgs.num_cpus = 1;
|
||||
}
|
||||
@@ -19,15 +19,8 @@
|
||||
#include <boot/platform.h>
|
||||
#include <boot/stage2.h>
|
||||
#include <boot/menu.h>
|
||||
#include <arch/x86/apic.h>
|
||||
#include <arch/x86/arch_acpi.h>
|
||||
#include <arch/x86/arch_cpu.h>
|
||||
#include <arch/x86/arch_smp.h>
|
||||
#include <arch/x86/arch_system_info.h>
|
||||
#include <arch/x86/descriptors.h>
|
||||
|
||||
#include "mmu.h"
|
||||
#include "acpi.h"
|
||||
#include "arch_smp.h"
|
||||
|
||||
|
||||
#define NO_SMP 0
|
||||
@@ -40,388 +33,34 @@
|
||||
#endif
|
||||
|
||||
|
||||
extern "C" void execute_n_instructions(int count);
|
||||
|
||||
extern "C" void smp_trampoline(void);
|
||||
extern "C" void smp_trampoline_args(void);
|
||||
extern "C" void smp_trampoline_end(void);
|
||||
|
||||
struct gdtr {
|
||||
uint16 limit;
|
||||
uint32 base;
|
||||
unsigned char null[8];
|
||||
unsigned char code[8];
|
||||
unsigned char data[8];
|
||||
} __attribute__((packed));
|
||||
|
||||
// Arguments passed to the SMP trampoline.
|
||||
struct trampoline_args {
|
||||
uint32 trampoline; // Trampoline address
|
||||
uint32 gdt32; // 32-bit GDTR
|
||||
uint32 pml4; // 64-bit PML4
|
||||
uint32 gdt64; // 64-bit GDTR
|
||||
uint64 kernel_entry; // Kernel entry point
|
||||
uint64 kernel_args; // Kernel arguments
|
||||
uint64 current_cpu; // CPU number
|
||||
uint64 stack_top; // Kernel stack
|
||||
volatile uint64 sentinel; // Sentinel, AP sets to 0 when finished
|
||||
|
||||
// smp_boot_other_cpus puts the GDTR here.
|
||||
struct gdtr gdtr;
|
||||
};
|
||||
|
||||
|
||||
static uint32
|
||||
apic_read(uint32 offset)
|
||||
{
|
||||
return *(volatile uint32 *)((addr_t)gKernelArgs.arch_args.apic_phys + offset);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
apic_write(uint32 offset, uint32 data)
|
||||
{
|
||||
*(volatile uint32 *)((addr_t)gKernelArgs.arch_args.apic_phys + offset) = data;
|
||||
}
|
||||
|
||||
|
||||
static status_t
|
||||
smp_do_acpi_config(void)
|
||||
{
|
||||
TRACE(("smp: using ACPI to detect MP configuration\n"));
|
||||
|
||||
// reset CPU count
|
||||
gKernelArgs.num_cpus = 0;
|
||||
|
||||
acpi_madt *madt = (acpi_madt *)acpi_find_table(ACPI_MADT_SIGNATURE);
|
||||
|
||||
if (madt == NULL) {
|
||||
TRACE(("smp: Failed to find MADT!\n"));
|
||||
return B_ERROR;
|
||||
}
|
||||
|
||||
gKernelArgs.arch_args.apic_phys = madt->local_apic_address;
|
||||
TRACE(("smp: local apic address is 0x%" B_PRIx32 "\n", madt->local_apic_address));
|
||||
|
||||
acpi_apic *apic = (acpi_apic *)((uint8 *)madt + sizeof(acpi_madt));
|
||||
acpi_apic *end = (acpi_apic *)((uint8 *)madt + madt->header.length);
|
||||
while (apic < end) {
|
||||
switch (apic->type) {
|
||||
case ACPI_MADT_LOCAL_APIC:
|
||||
{
|
||||
if (gKernelArgs.num_cpus == SMP_MAX_CPUS) {
|
||||
TRACE(("smp: already reached maximum CPUs (%d)\n",
|
||||
SMP_MAX_CPUS));
|
||||
break;
|
||||
}
|
||||
|
||||
acpi_local_apic *localApic = (acpi_local_apic *)apic;
|
||||
TRACE(("smp: found local APIC with id %u\n",
|
||||
localApic->apic_id));
|
||||
if ((localApic->flags & ACPI_LOCAL_APIC_ENABLED) == 0) {
|
||||
TRACE(("smp: APIC is disabled and will not be used\n"));
|
||||
break;
|
||||
}
|
||||
|
||||
gKernelArgs.arch_args.cpu_apic_id[gKernelArgs.num_cpus]
|
||||
= localApic->apic_id;
|
||||
// TODO: how to find out? putting 0x10 in to indicate a local apic
|
||||
gKernelArgs.arch_args.cpu_apic_version[gKernelArgs.num_cpus]
|
||||
= 0x10;
|
||||
gKernelArgs.num_cpus++;
|
||||
break;
|
||||
}
|
||||
|
||||
case ACPI_MADT_IO_APIC: {
|
||||
acpi_io_apic *ioApic = (acpi_io_apic *)apic;
|
||||
TRACE(("smp: found io APIC with id %" B_PRIu32 " and address 0x%" B_PRIx32 "\n",
|
||||
ioApic->io_apic_id, ioApic->io_apic_address));
|
||||
if (gKernelArgs.arch_args.ioapic_phys == 0)
|
||||
gKernelArgs.arch_args.ioapic_phys = ioApic->io_apic_address;
|
||||
break;
|
||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
apic = (acpi_apic *)((uint8 *)apic + apic->length);
|
||||
}
|
||||
|
||||
return gKernelArgs.num_cpus > 0 ? B_OK : B_ERROR;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
calculate_apic_timer_conversion_factor(void)
|
||||
{
|
||||
int64 t1, t2;
|
||||
uint32 config;
|
||||
uint32 count;
|
||||
|
||||
TRACE(("calculating apic timer conversion factor\n"));
|
||||
|
||||
// setup the timer
|
||||
config = apic_read(APIC_LVT_TIMER);
|
||||
config = (config & APIC_LVT_TIMER_MASK) + APIC_LVT_MASKED;
|
||||
// timer masked, vector 0
|
||||
apic_write(APIC_LVT_TIMER, config);
|
||||
|
||||
config = (apic_read(APIC_TIMER_DIVIDE_CONFIG) & ~0x0000000f);
|
||||
apic_write(APIC_TIMER_DIVIDE_CONFIG, config | APIC_TIMER_DIVIDE_CONFIG_1);
|
||||
// divide clock by one
|
||||
|
||||
t1 = system_time();
|
||||
apic_write(APIC_INITIAL_TIMER_COUNT, 0xffffffff); // start the counter
|
||||
|
||||
execute_n_instructions(128 * 20000);
|
||||
|
||||
count = apic_read(APIC_CURRENT_TIMER_COUNT);
|
||||
t2 = system_time();
|
||||
|
||||
count = 0xffffffff - count;
|
||||
|
||||
gKernelArgs.arch_args.apic_time_cv_factor
|
||||
= (uint32)((1000000.0/(t2 - t1)) * count);
|
||||
|
||||
TRACE(("APIC ticks/sec = %" B_PRId32 "\n",
|
||||
gKernelArgs.arch_args.apic_time_cv_factor));
|
||||
}
|
||||
|
||||
|
||||
// #pragma mark -
|
||||
|
||||
|
||||
int
|
||||
smp_get_current_cpu(void)
|
||||
{
|
||||
if (gKernelArgs.arch_args.apic == NULL)
|
||||
return 0;
|
||||
|
||||
uint8 apicID = apic_read(APIC_ID) >> 24;
|
||||
for (uint32 i = 0; i < gKernelArgs.num_cpus; i++) {
|
||||
if (gKernelArgs.arch_args.cpu_apic_id[i] == apicID)
|
||||
return i;
|
||||
}
|
||||
|
||||
return 0;
|
||||
return arch_smp_get_current_cpu();
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
smp_init_other_cpus(void)
|
||||
{
|
||||
if (get_safemode_boolean(B_SAFEMODE_DISABLE_SMP, false)) {
|
||||
// SMP has been disabled!
|
||||
TRACE(("smp disabled per safemode setting\n"));
|
||||
gKernelArgs.num_cpus = 1;
|
||||
}
|
||||
|
||||
if (get_safemode_boolean(B_SAFEMODE_DISABLE_APIC, false)) {
|
||||
TRACE(("local apic disabled per safemode setting, disabling smp\n"));
|
||||
gKernelArgs.arch_args.apic_phys = 0;
|
||||
gKernelArgs.num_cpus = 1;
|
||||
}
|
||||
|
||||
if (gKernelArgs.arch_args.apic_phys == 0)
|
||||
return;
|
||||
|
||||
TRACE(("smp: found %" B_PRId32 " cpu%s\n", gKernelArgs.num_cpus,
|
||||
gKernelArgs.num_cpus != 1 ? "s" : ""));
|
||||
TRACE(("smp: apic_phys = %lx\n", (addr_t)gKernelArgs.arch_args.apic_phys));
|
||||
TRACE(("smp: ioapic_phys = %lx\n",
|
||||
(addr_t)gKernelArgs.arch_args.ioapic_phys));
|
||||
|
||||
// map in the apic
|
||||
gKernelArgs.arch_args.apic = (void *)mmu_map_physical_memory(
|
||||
gKernelArgs.arch_args.apic_phys, B_PAGE_SIZE, kDefaultPageFlags);
|
||||
|
||||
TRACE(("smp: apic (mapped) = %lx\n", (addr_t)gKernelArgs.arch_args.apic.Pointer()));
|
||||
|
||||
// calculate how fast the apic timer is
|
||||
calculate_apic_timer_conversion_factor();
|
||||
|
||||
if (gKernelArgs.num_cpus < 2)
|
||||
return;
|
||||
|
||||
for (uint32 i = 1; i < gKernelArgs.num_cpus; i++) {
|
||||
// create a final stack the trampoline code will put the ap processor on
|
||||
void * stack = NULL;
|
||||
const size_t size = KERNEL_STACK_SIZE + KERNEL_STACK_GUARD_PAGES * B_PAGE_SIZE;
|
||||
if (platform_allocate_region(&stack, size, 0, false) != B_OK) {
|
||||
panic("Unable to allocate AP stack");
|
||||
}
|
||||
memset(stack, 0, size);
|
||||
gKernelArgs.cpu_kstack[i].start = fix_address((uint64_t)stack);
|
||||
gKernelArgs.cpu_kstack[i].size = size;
|
||||
}
|
||||
arch_smp_init_other_cpus();
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
smp_boot_other_cpus(uint32 pml4, uint32 gdtr64, uint64 kernel_entry)
|
||||
smp_boot_other_cpus(uint32 pml4, uint64 kernel_entry)
|
||||
{
|
||||
if (gKernelArgs.num_cpus < 2)
|
||||
return;
|
||||
|
||||
TRACE(("trampolining other cpus\n"));
|
||||
|
||||
// allocate a stack and a code area for the smp trampoline
|
||||
// (these have to be < 1M physical, 0xa0000-0xfffff is reserved by the BIOS)
|
||||
uint64 trampolineCode = 0x9000;
|
||||
uint64 trampolineStack = 0x8000;
|
||||
|
||||
// copy the trampoline code over
|
||||
TRACE(("copying the trampoline code to %p from %p\n", (char*)trampolineCode, (const void*)&smp_trampoline));
|
||||
TRACE(("size of trampoline code = %lu bytes\n", (uint64)&smp_trampoline_end - (uint64)&smp_trampoline));
|
||||
memcpy((char *)trampolineCode, (const void*)&smp_trampoline,
|
||||
(uint64)&smp_trampoline_end - (uint64)&smp_trampoline);
|
||||
|
||||
// boot the cpus
|
||||
TRACE(("we have %d CPUs to boot...\n", gKernelArgs.num_cpus - 1));
|
||||
for (uint32 i = 1; i < gKernelArgs.num_cpus; i++) {
|
||||
TRACE(("trampolining CPU %d\n", i));
|
||||
uint32 config;
|
||||
uint64 numStartups;
|
||||
uint32 j;
|
||||
trampoline_args * args = (trampoline_args *)trampolineStack;
|
||||
args->trampoline = trampolineCode;
|
||||
args->gdt32 = (uint64) &args->gdtr;
|
||||
args->gdtr.limit = 23;
|
||||
args->gdtr.base = (uint32)(uint64)args->gdtr.null;
|
||||
#define COPY_ARRAY(A, X0, X1, X2, X3, X4, X5, X6, X7) \
|
||||
{ A[0] = X0; A[1] = X1; A[2] = X2; A[3] = X3; A[4] = X4; A[5] = X5; A[6] = X6; A[7] = X7; }
|
||||
COPY_ARRAY(args->gdtr.null, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
COPY_ARRAY(args->gdtr.code, 0xff, 0xff, 0, 0, 0, 0x9a, 0xcf, 0);
|
||||
COPY_ARRAY(args->gdtr.data, 0xff, 0xff, 0, 0, 0, 0x92, 0xcf, 0);
|
||||
#undef COPY_ARRAY
|
||||
args->pml4 = pml4;
|
||||
args->gdt64 = gdtr64;
|
||||
args->kernel_entry = kernel_entry;
|
||||
args->kernel_args = (uint64)&gKernelArgs;
|
||||
args->current_cpu = i;
|
||||
args->stack_top = gKernelArgs.cpu_kstack[i].start + gKernelArgs.cpu_kstack[i].size;
|
||||
args->sentinel = 1;
|
||||
|
||||
// put the args in the right place
|
||||
uint32 * args_ptr =
|
||||
(uint32 *)(trampolineCode + (uint64)smp_trampoline_args - (uint64)smp_trampoline);
|
||||
*args_ptr = (uint32)(uint64)args;
|
||||
|
||||
/* clear apic errors */
|
||||
if (gKernelArgs.arch_args.cpu_apic_version[i] & 0xf0) {
|
||||
apic_write(APIC_ERROR_STATUS, 0);
|
||||
apic_read(APIC_ERROR_STATUS);
|
||||
}
|
||||
|
||||
/* send (aka assert) INIT IPI */
|
||||
config = (apic_read(APIC_INTR_COMMAND_2) & APIC_INTR_COMMAND_2_MASK)
|
||||
| (gKernelArgs.arch_args.cpu_apic_id[i] << 24);
|
||||
apic_write(APIC_INTR_COMMAND_2, config); /* set target pe */
|
||||
config = (apic_read(APIC_INTR_COMMAND_1) & 0xfff00000)
|
||||
| APIC_TRIGGER_MODE_LEVEL | APIC_INTR_COMMAND_1_ASSERT
|
||||
| APIC_DELIVERY_MODE_INIT;
|
||||
apic_write(APIC_INTR_COMMAND_1, config);
|
||||
|
||||
// wait for pending to end
|
||||
while ((apic_read(APIC_INTR_COMMAND_1) & APIC_DELIVERY_STATUS) != 0)
|
||||
asm volatile ("pause;");
|
||||
|
||||
/* deassert INIT */
|
||||
config = (apic_read(APIC_INTR_COMMAND_2) & APIC_INTR_COMMAND_2_MASK)
|
||||
| (gKernelArgs.arch_args.cpu_apic_id[i] << 24);
|
||||
apic_write(APIC_INTR_COMMAND_2, config);
|
||||
config = (apic_read(APIC_INTR_COMMAND_1) & 0xfff00000)
|
||||
| APIC_TRIGGER_MODE_LEVEL | APIC_DELIVERY_MODE_INIT;
|
||||
apic_write(APIC_INTR_COMMAND_1, config);
|
||||
|
||||
// wait for pending to end
|
||||
while ((apic_read(APIC_INTR_COMMAND_1) & APIC_DELIVERY_STATUS) != 0)
|
||||
asm volatile ("pause;");
|
||||
|
||||
/* wait 10ms */
|
||||
spin(10000);
|
||||
/* is this a local apic or an 82489dx ? */
|
||||
numStartups = (gKernelArgs.arch_args.cpu_apic_version[i] & 0xf0)
|
||||
? 2 : 0;
|
||||
for (j = 0; j < numStartups; j++) {
|
||||
/* it's a local apic, so send STARTUP IPIs */
|
||||
apic_write(APIC_ERROR_STATUS, 0);
|
||||
|
||||
/* set target pe */
|
||||
config = (apic_read(APIC_INTR_COMMAND_2) & APIC_INTR_COMMAND_2_MASK)
|
||||
| (gKernelArgs.arch_args.cpu_apic_id[i] << 24);
|
||||
apic_write(APIC_INTR_COMMAND_2, config);
|
||||
|
||||
/* send the IPI */
|
||||
config = (apic_read(APIC_INTR_COMMAND_1) & 0xfff0f800)
|
||||
| APIC_DELIVERY_MODE_STARTUP | (trampolineCode >> 12);
|
||||
apic_write(APIC_INTR_COMMAND_1, config);
|
||||
|
||||
/* wait */
|
||||
spin(200);
|
||||
|
||||
while ((apic_read(APIC_INTR_COMMAND_1) & APIC_DELIVERY_STATUS) != 0)
|
||||
asm volatile ("pause;");
|
||||
}
|
||||
|
||||
// Wait for the trampoline code to clear the final stack location.
|
||||
// This serves as a notification for us that it has loaded the address
|
||||
// and it is safe for us to overwrite it to trampoline the next CPU.
|
||||
while (args->sentinel != 0)
|
||||
spin(1000);
|
||||
}
|
||||
|
||||
TRACE(("done trampolining\n"));
|
||||
arch_smp_boot_other_cpus(pml4, kernel_entry);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
smp_add_safemode_menus(Menu *menu)
|
||||
{
|
||||
MenuItem *item;
|
||||
|
||||
if (gKernelArgs.arch_args.ioapic_phys != 0) {
|
||||
menu->AddItem(item = new(nothrow) MenuItem("Disable IO-APIC"));
|
||||
item->SetType(MENU_ITEM_MARKABLE);
|
||||
item->SetData(B_SAFEMODE_DISABLE_IOAPIC);
|
||||
item->SetHelpText("Disables using the IO APIC for interrupt routing, "
|
||||
"forcing the use of the legacy PIC instead.");
|
||||
}
|
||||
|
||||
if (gKernelArgs.arch_args.apic_phys != 0) {
|
||||
menu->AddItem(item = new(nothrow) MenuItem("Disable local APIC"));
|
||||
item->SetType(MENU_ITEM_MARKABLE);
|
||||
item->SetData(B_SAFEMODE_DISABLE_APIC);
|
||||
item->SetHelpText("Disables using the local APIC, also disables SMP.");
|
||||
|
||||
cpuid_info info;
|
||||
if (get_current_cpuid(&info, 1, 0) == B_OK
|
||||
&& (info.regs.ecx & IA32_FEATURE_EXT_X2APIC) != 0) {
|
||||
menu->AddItem(item = new(nothrow) MenuItem("Disable X2APIC"));
|
||||
item->SetType(MENU_ITEM_MARKABLE);
|
||||
item->SetData(B_SAFEMODE_DISABLE_X2APIC);
|
||||
item->SetHelpText("Disables using X2APIC.");
|
||||
}
|
||||
|
||||
if (get_current_cpuid(&info, 7, 0) == B_OK
|
||||
&& ((info.regs.ebx & (IA32_FEATURE_SMEP
|
||||
| IA32_FEATURE_SMAP)) != 0)) {
|
||||
menu->AddItem(item = new(nothrow) MenuItem(
|
||||
"Disable SMEP and SMAP"));
|
||||
item->SetType(MENU_ITEM_MARKABLE);
|
||||
item->SetData(B_SAFEMODE_DISABLE_SMEP_SMAP);
|
||||
item->SetHelpText("Disables using SMEP and SMAP.");
|
||||
}
|
||||
}
|
||||
|
||||
if (gKernelArgs.num_cpus < 2)
|
||||
return;
|
||||
|
||||
item = new(nothrow) MenuItem("Disable SMP");
|
||||
menu->AddItem(item);
|
||||
item->SetData(B_SAFEMODE_DISABLE_SMP);
|
||||
item->SetType(MENU_ITEM_MARKABLE);
|
||||
item->SetHelpText("Disables all but one CPU core.");
|
||||
arch_smp_add_safemode_menus(menu);
|
||||
}
|
||||
|
||||
|
||||
@@ -433,28 +72,5 @@ smp_init(void)
|
||||
return;
|
||||
#endif
|
||||
|
||||
cpuid_info info;
|
||||
if (get_current_cpuid(&info, 1, 0) != B_OK)
|
||||
return;
|
||||
|
||||
if ((info.eax_1.features & IA32_FEATURE_APIC) == 0) {
|
||||
// Local APICs aren't present; As they form the basis for all inter CPU
|
||||
// communication and therefore SMP, we don't need to go any further.
|
||||
TRACE(("no local APIC present, not attempting SMP init\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
// first try to find ACPI tables to get MP configuration as it handles
|
||||
// physical as well as logical MP configurations as in multiple cpus,
|
||||
// multiple cores or hyper threading.
|
||||
if (smp_do_acpi_config() == B_OK) {
|
||||
TRACE(("smp init success\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
// Everything failed or we are not running an SMP system, reset anything
|
||||
// that might have been set through an incomplete configuration attempt.
|
||||
gKernelArgs.arch_args.apic_phys = 0;
|
||||
gKernelArgs.arch_args.ioapic_phys = 0;
|
||||
gKernelArgs.num_cpus = 1;
|
||||
arch_smp_init();
|
||||
}
|
||||
|
||||
@@ -19,12 +19,12 @@ extern "C" {
|
||||
|
||||
extern void smp_init(void);
|
||||
extern void smp_init_other_cpus(void);
|
||||
extern void smp_boot_other_cpus(uint32 pml4, uint32 gdt64, uint64 kernel_entry);
|
||||
|
||||
extern void smp_boot_other_cpus(uint32 pml4, uint64 kernel_entry);
|
||||
extern int smp_get_current_cpu(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* SMP_H */
|
||||
|
||||
@@ -12,13 +12,13 @@
|
||||
#include <KernelExport.h>
|
||||
|
||||
#include <arch/cpu.h>
|
||||
#include <arch/x86/descriptors.h>
|
||||
#include <boot/kernel_args.h>
|
||||
#include <boot/platform.h>
|
||||
#include <boot/stage2.h>
|
||||
#include <boot/stdio.h>
|
||||
#include <kernel.h>
|
||||
|
||||
#include "arch_mmu.h"
|
||||
#include "acpi.h"
|
||||
#include "console.h"
|
||||
#include "efi_platform.h"
|
||||
@@ -41,9 +41,6 @@ EFI_HANDLE kImage;
|
||||
|
||||
static uint32 sBootOptions;
|
||||
static uint64 gLongKernelEntry;
|
||||
extern uint64 gLongGDT;
|
||||
extern uint64 gLongGDTR;
|
||||
segment_descriptor gBootGDT[BOOT_GDT_SEGMENT_COUNT];
|
||||
|
||||
|
||||
extern "C" int main(stage2_args *args);
|
||||
@@ -68,27 +65,6 @@ platform_boot_options()
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
long_gdt_init()
|
||||
{
|
||||
clear_segment_descriptor(&gBootGDT[0]);
|
||||
|
||||
// Set up code/data segments (TSS segments set up later in the kernel).
|
||||
set_segment_descriptor(&gBootGDT[KERNEL_CODE_SEGMENT], DT_CODE_EXECUTE_ONLY,
|
||||
DPL_KERNEL);
|
||||
set_segment_descriptor(&gBootGDT[KERNEL_DATA_SEGMENT], DT_DATA_WRITEABLE,
|
||||
DPL_KERNEL);
|
||||
set_segment_descriptor(&gBootGDT[USER_CODE_SEGMENT], DT_CODE_EXECUTE_ONLY,
|
||||
DPL_USER);
|
||||
set_segment_descriptor(&gBootGDT[USER_DATA_SEGMENT], DT_DATA_WRITEABLE,
|
||||
DPL_USER);
|
||||
|
||||
// Used by long_enter_kernel().
|
||||
gLongGDT = (addr_t)gBootGDT + 0xFFFFFF0000000000;
|
||||
dprintf("GDT at 0x%lx\n", gLongGDT);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
convert_preloaded_image(preloaded_elf64_image* image)
|
||||
{
|
||||
@@ -152,7 +128,7 @@ platform_start_kernel(void)
|
||||
preloaded_elf64_image *image = static_cast<preloaded_elf64_image *>(
|
||||
gKernelArgs.kernel_image.Pointer());
|
||||
|
||||
long_gdt_init();
|
||||
arch_mmu_init();
|
||||
convert_kernel_args();
|
||||
|
||||
// Save the kernel entry point address.
|
||||
@@ -238,7 +214,7 @@ platform_start_kernel(void)
|
||||
// Update EFI, generate final kernel physical memory map, etc.
|
||||
mmu_post_efi_setup(memory_map_size, memory_map, descriptor_size, descriptor_version);
|
||||
|
||||
smp_boot_other_cpus(final_pml4, (uint32_t)(uint64_t)&gLongGDTR, gLongKernelEntry);
|
||||
smp_boot_other_cpus(final_pml4, gLongKernelEntry);
|
||||
|
||||
// Enter the kernel!
|
||||
efi_enter_kernel(final_pml4,
|
||||
|
||||
Reference in New Issue
Block a user