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partial cleanup, starting to disable engine programming..

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@9797 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2004-11-04 16:35:44 +00:00
parent bf1feef864
commit 848b55ddd3
3 changed files with 135 additions and 745 deletions
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src/add-ons/accelerants/skeleton/SetDisplayMode.c
+80 -77
View File
@@ -49,9 +49,9 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
display_mode /*bounds,*/ target;
uint8 colour_depth1 = 32;
status_t result;
// status_t result;
uint32 startadd,startadd_right;
bool display, h, v;
// bool display, h, v;
// bool crt1, crt2, cross;
/* Adjust mode to valid one and fail if invalid */
@@ -81,9 +81,9 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
interrupt_enable(false);
/* find current DPMS state, then turn off screen(s) */
head1_dpms_fetch(&display, &h, &v);
head1_dpms(false, false, false);
if (si->ps.secondary_head) head2_dpms(false, false, false);
// head1_dpms_fetch(&display, &h, &v);
// head1_dpms(false, false, false);
// if (si->ps.secondary_head) head2_dpms(false, false, false);
/*where in framebuffer the screen is (should this be dependant on previous MOVEDISPLAY?)*/
startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;
@@ -102,12 +102,12 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
LOG(1,("SETMODE: setting DUALHEAD mode\n"));
/* validate flags for secondary TVout */
if ((i2c_sec_tv_adapter() != B_OK) && (target2.flags & TV_BITS))
{
target.flags &= ~TV_BITS;//still needed for some routines...
target2.flags &= ~TV_BITS;
LOG(1,("SETMODE: blocking TVout: no TVout cable connected!\n"));
}
// if ((i2c_sec_tv_adapter() != B_OK) && (target2.flags & TV_BITS))
// {
// target.flags &= ~TV_BITS;//still needed for some routines...
// target2.flags &= ~TV_BITS;
// LOG(1,("SETMODE: blocking TVout: no TVout cable connected!\n"));
// }
/* detect which connectors have a CRT connected */
//fixme: 'hot-plugging' for analog monitors removed: remove code as well;
@@ -130,47 +130,47 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
// cross = false;
// }
/* set output connectors assignment if possible */
if ((target.flags & DUALHEAD_BITS) == DUALHEAD_SWITCH)
// if ((target.flags & DUALHEAD_BITS) == DUALHEAD_SWITCH)
/* invert output assignment in switch mode */
eng_general_head_select(true);
else
eng_general_head_select(false);
// eng_general_head_select(true);
// else
// eng_general_head_select(false);
/* set the pixel clock PLL(s) */
LOG(8,("SETMODE: target clock %dkHz\n",target.timing.pixel_clock));
if (head1_set_pix_pll(target) == B_ERROR)
LOG(8,("SETMODE: error setting pixel clock (internal DAC)\n"));
// if (head1_set_pix_pll(target) == B_ERROR)
// LOG(8,("SETMODE: error setting pixel clock (internal DAC)\n"));
/* we do not need to set the pixelclock here for a head that's in TVout mode */
if (!(target2.flags & TV_BITS))
{
LOG(8,("SETMODE: target2 clock %dkHz\n",target2.timing.pixel_clock));
if (head2_set_pix_pll(target2) == B_ERROR)
LOG(8,("SETMODE: error setting pixel clock (DAC2)\n"));
}
// if (!(target2.flags & TV_BITS))
// {
// LOG(8,("SETMODE: target2 clock %dkHz\n",target2.timing.pixel_clock));
// if (head2_set_pix_pll(target2) == B_ERROR)
// LOG(8,("SETMODE: error setting pixel clock (DAC2)\n"));
// }
/*set the colour depth for CRTC1 and the DAC */
switch(target.space)
{
case B_CMAP8:
colour_depth1 = 8;
head1_mode(BPP8, 1.0);
head1_depth(BPP8);
// head1_mode(BPP8, 1.0);
// head1_depth(BPP8);
break;
case B_RGB15_LITTLE:
colour_depth1 = 16;
head1_mode(BPP15, 1.0);
head1_depth(BPP15);
// head1_mode(BPP15, 1.0);
// head1_depth(BPP15);
break;
case B_RGB16_LITTLE:
colour_depth1 = 16;
head1_mode(BPP16, 1.0);
head1_depth(BPP16);
// head1_mode(BPP16, 1.0);
// head1_depth(BPP16);
break;
case B_RGB32_LITTLE:
colour_depth1 = 32;
head1_mode(BPP32, 1.0);
head1_depth(BPP32);
// head1_mode(BPP32, 1.0);
// head1_depth(BPP32);
break;
}
/*set the colour depth for CRTC2 and DAC2 */
@@ -178,23 +178,23 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
{
case B_CMAP8:
colour_depth2 = 8;
head2_mode(BPP8, 1.0);
head2_depth(BPP8);
// head2_mode(BPP8, 1.0);
// head2_depth(BPP8);
break;
case B_RGB15_LITTLE:
colour_depth2 = 16;
head2_mode(BPP15, 1.0);
head2_depth(BPP15);
// head2_mode(BPP15, 1.0);
// head2_depth(BPP15);
break;
case B_RGB16_LITTLE:
colour_depth2 = 16;
head2_mode(BPP16, 1.0);
head2_depth(BPP16);
// head2_mode(BPP16, 1.0);
// head2_depth(BPP16);
break;
case B_RGB32_LITTLE:
colour_depth2 = 32;
head2_mode(BPP32, 1.0);
head2_depth(BPP32);
// head2_mode(BPP32, 1.0);
// head2_depth(BPP32);
break;
}
@@ -204,10 +204,10 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
si->interlaced_tv_mode = true;
*/
/*set the display(s) pitches*/
head1_set_display_pitch ();
// head1_set_display_pitch ();
//fixme: seperate for real dualhead modes:
//we need a secondary si->fbc!
head2_set_display_pitch ();
// head2_set_display_pitch ();
/*work out where the "right" screen starts*/
startadd_right = startadd + (target.timing.h_display * (colour_depth1 >> 3));
@@ -217,22 +217,22 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
{
case DUALHEAD_ON:
case DUALHEAD_SWITCH:
head1_set_display_start(startadd,colour_depth1);
head2_set_display_start(startadd_right,colour_depth2);
// head1_set_display_start(startadd,colour_depth1);
// head2_set_display_start(startadd_right,colour_depth2);
break;
case DUALHEAD_CLONE:
head1_set_display_start(startadd,colour_depth1);
head2_set_display_start(startadd,colour_depth2);
// head1_set_display_start(startadd,colour_depth1);
// head2_set_display_start(startadd,colour_depth2);
break;
}
/* set the timing */
head1_set_timing(target);
// head1_set_timing(target);
/* we do not need to setup CRTC2 here for a head that's in TVout mode */
if (!(target2.flags & TV_BITS)) result = head2_set_timing(target2);
// if (!(target2.flags & TV_BITS)) result = head2_set_timing(target2);
/* TVout support: setup CRTC2 and it's pixelclock */
if (si->ps.tvout && (target2.flags & TV_BITS)) maventv_init(target2);
// if (si->ps.tvout && (target2.flags & TV_BITS)) maventv_init(target2);
}
else /* single head mode */
{
@@ -278,25 +278,26 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
}
/* set the pixel clock PLL */
status = head1_set_pix_pll(target);
// status = head1_set_pix_pll(target);
status = B_OK;
if (status==B_ERROR)
LOG(8,("CRTC: error setting pixel clock (internal DAC)\n"));
/* set the colour depth for CRTC1 and the DAC */
/* first set the colordepth */
head1_depth(colour_mode);
// head1_depth(colour_mode);
/* then(!) program the PAL (<8bit colordepth does not support 8bit PAL) */
head1_mode(colour_mode,1.0);
// head1_mode(colour_mode,1.0);
/* set the display pitch */
head1_set_display_pitch();
// head1_set_display_pitch();
/* tell the card what memory to display */
head1_set_display_start(startadd,colour_depth1);
// head1_set_display_start(startadd,colour_depth1);
/* set the timing */
head1_set_timing(target);
// head1_set_timing(target);
//fixme: shut-off the videoPLL if it exists...
}
@@ -305,14 +306,14 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
si->dm = target;
/* turn screen one on */
head1_dpms(display, h, v);
// head1_dpms(display, h, v);
/* turn screen two on if a dualhead mode is active */
if (target.flags & DUALHEAD_BITS) head2_dpms(display,h,v);
// if (target.flags & DUALHEAD_BITS) head2_dpms(display,h,v);
/* set up acceleration for this mode */
eng_acc_init();
// eng_acc_init();
/* set up overlay unit for this mode */
eng_bes_init();
// eng_bes_init();
LOG(1,("SETMODE: booted since %f mS\n", system_time()/1000.0));
@@ -395,15 +396,15 @@ status_t MOVE_DISPLAY(uint16 h_display_start, uint16 v_display_start) {
{
case DUALHEAD_ON:
case DUALHEAD_SWITCH:
head1_set_display_start(startadd,colour_depth);
head2_set_display_start(startadd_right,colour_depth);
// head1_set_display_start(startadd,colour_depth);
// head2_set_display_start(startadd_right,colour_depth);
break;
case DUALHEAD_OFF:
head1_set_display_start(startadd,colour_depth);
// head1_set_display_start(startadd,colour_depth);
break;
case DUALHEAD_CLONE:
head1_set_display_start(startadd,colour_depth);
head2_set_display_start(startadd,colour_depth);
// head1_set_display_start(startadd,colour_depth);
// head2_set_display_start(startadd,colour_depth);
break;
}
@@ -431,7 +432,7 @@ void SET_INDEXED_COLORS(uint count, uint8 first, uint8 *color_data, uint32 flags
b[i]=*color_data++;
i++;
}
head1_palette(r,g,b);
// head1_palette(r,g,b);
if (si->dm.flags & DUALHEAD_BITS) head2_palette(r,g,b);
}
@@ -446,20 +447,20 @@ status_t SET_DPMS_MODE(uint32 dpms_flags) {
switch(dpms_flags)
{
case B_DPMS_ON: /* H: on, V: on, display on */
head1_dpms(true, true, true);
if (si->ps.secondary_head) head2_dpms(true, true, true);
// head1_dpms(true, true, true);
// if (si->ps.secondary_head) head2_dpms(true, true, true);
break;
case B_DPMS_STAND_BY:
head1_dpms(false, false, true);
if (si->ps.secondary_head) head2_dpms(false, false, true);
// head1_dpms(false, false, true);
// if (si->ps.secondary_head) head2_dpms(false, false, true);
break;
case B_DPMS_SUSPEND:
head1_dpms(false, true, false);
if (si->ps.secondary_head) head2_dpms(false, true, false);
// head1_dpms(false, true, false);
// if (si->ps.secondary_head) head2_dpms(false, true, false);
break;
case B_DPMS_OFF: /* H: off, V: off, display off */
head1_dpms(false, false, false);
if (si->ps.secondary_head) head2_dpms(false, false, false);
// head1_dpms(false, false, false);
// if (si->ps.secondary_head) head2_dpms(false, false, false);
break;
default:
LOG(8,("SET: Invalid DPMS settings (DH) 0x%08x\n", dpms_flags));
@@ -472,16 +473,16 @@ status_t SET_DPMS_MODE(uint32 dpms_flags) {
switch(dpms_flags)
{
case B_DPMS_ON: /* H: on, V: on, display on */
head1_dpms(true, true, true);
// head1_dpms(true, true, true);
break;
case B_DPMS_STAND_BY:
head1_dpms(false, false, true);
// head1_dpms(false, false, true);
break;
case B_DPMS_SUSPEND:
head1_dpms(false, true, false);
// head1_dpms(false, true, false);
break;
case B_DPMS_OFF: /* H: off, V: off, display off */
head1_dpms(false, false, false);
// head1_dpms(false, false, false);
break;
default:
LOG(8,("SET: Invalid DPMS settings (DH) 0x%08x\n", dpms_flags));
@@ -503,7 +504,9 @@ uint32 DPMS_MODE(void) {
bool display, h, v;
interrupt_enable(false);
head1_dpms_fetch(&display, &h, &v);
// head1_dpms_fetch(&display, &h, &v);
display = h = v = true;
interrupt_enable(true);
if (display && h && v)
src/add-ons/accelerants/skeleton/engine/acc.c
+11 -630
View File
@@ -1,8 +1,6 @@
/* NV Acceleration functions */
/* Acceleration functions */
/* Author:
Rudolf Cornelissen 8/2003-9/2004.
This code was possible thanks to the Linux NV driver.
Rudolf Cornelissen 8/2003-11/2004.
*/
#define MODULE_BIT 0x00080000
@@ -21,7 +19,8 @@ blit
status_t eng_acc_wait_idle()
{
/* wait until engine completely idle */
while (ACCR(STATUS))
// while (ACCR(STATUS))
while (0)
{
/* snooze a bit so I do not hammer the bus */
snooze (100);
@@ -34,665 +33,47 @@ status_t eng_acc_wait_idle()
* Engine required init. */
status_t eng_acc_init()
{
uint16 cnt;
/* setup PTIMER: */
//fixme? how about NV28 setup as just after coldstarting? (see eng_info.c)
/* set timer numerator to 8 (in b0-15) */
ACCW(PT_NUMERATOR, 0x00000008);
/* set timer denominator to 3 (in b0-15) */
ACCW(PT_DENOMINATR, 0x00000003);
/* disable timer-alarm INT requests (b0) */
ACCW(PT_INTEN, 0x00000000);
/* reset timer-alarm INT status bit (b0) */
ACCW(PT_INTSTAT, 0xffffffff);
/* enable PRAMIN write access on pre NV10 before programming it! */
if (si->ps.card_arch == NV04A)
{
/* set framebuffer config: type = notiling, PRAMIN write access enabled */
ENG_RG32(RG32_PFB_CONFIG_0) = 0x00001114;
}
/*** PFIFO ***/
/* (setup caches) */
/* disable caches reassign */
ACCW(PF_CACHES, 0x00000000);
/* cache1 push0 access disabled */
ACCW(PF_CACH1_PSH0, 0x00000000);
/* cache1 pull0 access disabled */
ACCW(PF_CACH1_PUL0, 0x00000000);
/* cache1 push1 mode = pio */
ACCW(PF_CACH1_PSH1, 0x00000000);
/* cache1 DMA instance adress = 0 (b0-15) */
ACCW(PF_CACH1_DMAI, 0x00000000);
/* cache0 push0 access disabled */
ACCW(PF_CACH0_PSH0, 0x00000000);
/* cache0 pull0 access disabled */
ACCW(PF_CACH0_PUL0, 0x00000000);
/* RAM HT (hash table(?)) baseadress = $10000 (b4-8), size = 4k,
* search = 128 (byte offset between hash 'sets'(?)) */
/* (note: so(?) HT base is $00710000, last is $00710fff) */
ACCW(PF_RAMHT, 0x03000100);
/* RAM FC baseadress = $11000 (b3-8) (size is fixed to 0.5k(?)) */
/* (note: so(?) FC base is $00711000, last is $007111ff) */
ACCW(PF_RAMFC, 0x00000110);
/* RAM RO baseadress = $11200 (b1-8), size = 0.5k */
/* (note: so(?) RO base is $00711200, last is $007113ff) */
/* (note also:
* This means(?) the PRAMIN CTX registers are accessible from base $00711400) */
ACCW(PF_RAMRO, 0x00000112);
/* PFIFO size: ch0-15 = 512 bytes, ch16-31 = 124 bytes */
ACCW(PF_SIZE, 0x0000ffff);
/* cache1 hash instance = $ffff (b0-15) */
ACCW(PF_CACH1_HASH, 0x0000ffff);
/* disable all PFIFO INTs */
ACCW(PF_INTEN, 0x00000000);
/* reset all PFIFO INT status bits */
ACCW(PF_INTSTAT, 0xffffffff);
/* cache0 pull0 engine = acceleration engine (graphics) */
ACCW(PF_CACH0_PUL1, 0x00000001);
/* cache1 push0 access enabled */
ACCW(PF_CACH1_PSH0, 0x00000001);
/* cache1 pull0 access enabled */
ACCW(PF_CACH1_PUL0, 0x00000001);
/* cache1 pull1 engine = acceleration engine (graphics) */
ACCW(PF_CACH1_PUL1, 0x00000001);
/* enable PFIFO caches reassign */
ACCW(PF_CACHES, 0x00000001);
/*** PRAMIN ***/
/* RAMHT space (hash-table(?)) */
/* (first set) */
ACCW(HT_HANDL_00, 0x80000010); /* 32bit handle */
ACCW(HT_VALUE_00, 0x80011145); /* instance $1145, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_01, 0x80000011); /* 32bit handle */
ACCW(HT_VALUE_01, 0x80011146); /* instance $1146, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_02, 0x80000012); /* 32bit handle */
ACCW(HT_VALUE_02, 0x80011147); /* instance $1147, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_03, 0x80000013); /* 32bit handle */
ACCW(HT_VALUE_03, 0x80011148); /* instance $1148, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_04, 0x80000014); /* 32bit handle */
ACCW(HT_VALUE_04, 0x80011149); /* instance $1149, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_05, 0x80000015); /* 32bit handle */
ACCW(HT_VALUE_05, 0x8001114a); /* instance $114a, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_06, 0x80000016); /* 32bit handle */
if (si->ps.card_arch != NV04A)
ACCW(HT_VALUE_06, 0x80011150); /* instance $1150, engine = acc engine, CHID = $00 */
else
ACCW(HT_VALUE_06, 0x8001114f); /* instance $114f, engine = acc engine, CHID = $00 */
/* (second set) */
ACCW(HT_HANDL_10, 0x80000000); /* 32bit handle */
ACCW(HT_VALUE_10, 0x80011142); /* instance $1142, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_11, 0x80000001); /* 32bit handle */
ACCW(HT_VALUE_11, 0x80011143); /* instance $1143, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_12, 0x80000002); /* 32bit handle */
ACCW(HT_VALUE_12, 0x80011144); /* instance $1144, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_13, 0x80000003); /* 32bit handle */
ACCW(HT_VALUE_13, 0x8001114b); /* instance $114b, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_14, 0x80000004); /* 32bit handle */
ACCW(HT_VALUE_14, 0x8001114c); /* instance $114c, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_15, 0x80000005); /* 32bit handle */
ACCW(HT_VALUE_15, 0x8001114d); /* instance $114d, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_16, 0x80000006); /* 32bit handle */
ACCW(HT_VALUE_16, 0x8001114e); /* instance $114e, engine = acc engine, CHID = $00 */
if (si->ps.card_arch != NV04A)
{
ACCW(HT_HANDL_17, 0x80000007); /* 32bit handle */
ACCW(HT_VALUE_17, 0x8001114f); /* instance $114f, engine = acc engine, CHID = $00 */
}
/* program CTX registers: CTX1 is mostly done later (colorspace dependant) */
/* (setup 'root' set first) */
ACCW(PR_CTX0_R, 0x00003000); /* NVclass = NVroot, chromakey and userclip enabled */
/* fixme: CTX1_R should reflect RAM amount? (no influence on current used functions) */
ACCW(PR_CTX1_R, 0x01ffffff); /* cardmemory mask(?) */
ACCW(PR_CTX2_R, 0x00000002); /* ??? */
ACCW(PR_CTX3_R, 0x00000002); /* ??? */
/* (setup set '0') */
ACCW(PR_CTX0_0, 0x01008043); /* NVclass $043, patchcfg ROP_AND, nv10+: little endian */
ACCW(PR_CTX2_0, 0x00000000); /* DMA0 and DMA1 instance invalid */
ACCW(PR_CTX3_0, 0x00000000); /* method traps disabled */
/* (setup set '1') */
ACCW(PR_CTX0_1, 0x01008019); /* NVclass $019, patchcfg ROP_AND, nv10+: little endian */
ACCW(PR_CTX2_1, 0x00000000); /* DMA0 and DMA1 instance invalid */
ACCW(PR_CTX3_1, 0x00000000); /* method traps disabled */
/* (setup set '2') */
ACCW(PR_CTX0_2, 0x01008018); /* NVclass $018, patchcfg ROP_AND, nv10+: little endian */
ACCW(PR_CTX2_2, 0x00000000); /* DMA0 and DMA1 instance invalid */
ACCW(PR_CTX3_2, 0x00000000); /* method traps disabled */
/* (setup set '3') */
ACCW(PR_CTX0_3, 0x01008021); /* NVclass $021, patchcfg ROP_AND, nv10+: little endian */
ACCW(PR_CTX2_3, 0x00000000); /* DMA0 and DMA1 instance invalid */
ACCW(PR_CTX3_3, 0x00000000); /* method traps disabled */
/* (setup set '4') */
ACCW(PR_CTX0_4, 0x0100805f); /* NVclass $05f, patchcfg ROP_AND, nv10+: little endian */
ACCW(PR_CTX2_4, 0x00000000); /* DMA0 and DMA1 instance invalid */
ACCW(PR_CTX3_4, 0x00000000); /* method traps disabled */
/* (setup set '5') */
ACCW(PR_CTX0_5, 0x0100804b); /* NVclass $04b, patchcfg ROP_AND, nv10+: little endian */
ACCW(PR_CTX2_5, 0x00000000); /* DMA0 and DMA1 instance invalid */
ACCW(PR_CTX3_5, 0x00000000); /* method traps disabled */
/* (setup set '6') */
ACCW(PR_CTX0_6, 0x0100a048); /* NVclass $048, patchcfg ROP_AND, userclip enable,
* nv10+: little endian */
ACCW(PR_CTX1_6, 0x00000d01); /* format is A8RGB24, MSB mono */
ACCW(PR_CTX2_6, 0x11401140); /* DMA0, DMA1 instance = $1140 */
ACCW(PR_CTX3_6, 0x00000000); /* method traps disabled */
/* (setup set '7') */
if (si->ps.card_arch != NV04A)
ACCW(PR_CTX0_7, 0x0300a094); /* NVclass $094, patchcfg ROP_AND, userclip enable,
* context surface0 valid, nv10+: little endian */
else
ACCW(PR_CTX0_7, 0x0300a054); /* NVclass $054, patchcfg ROP_AND, userclip enable,
* context surface0 valid */
ACCW(PR_CTX1_7, 0x00000d01); /* format is A8RGB24, MSB mono */
ACCW(PR_CTX2_7, 0x11401140); /* DMA0, DMA1 instance = $1140 */
ACCW(PR_CTX3_7, 0x00000000); /* method traps disabled */
/* (setup set '8') */
if (si->ps.card_arch != NV04A)
ACCW(PR_CTX0_8, 0x0300a095); /* NVclass $095, patchcfg ROP_AND, userclip enable,
* context surface0 valid, nv10+: little endian */
else
ACCW(PR_CTX0_8, 0x0300a055); /* NVclass $055, patchcfg ROP_AND, userclip enable,
* context surface0 valid */
ACCW(PR_CTX1_8, 0x00000d01); /* format is A8RGB24, MSB mono */
ACCW(PR_CTX2_8, 0x11401140); /* DMA0, DMA1 instance = $1140 */
ACCW(PR_CTX3_8, 0x00000000); /* method traps disabled */
/* (setup set '9') */
ACCW(PR_CTX0_9, 0x00000058); /* NVclass $058, nv10+: little endian */
ACCW(PR_CTX2_9, 0x11401140); /* DMA0, DMA1 instance = $1140 */
ACCW(PR_CTX3_9, 0x00000000); /* method traps disabled */
/* (setup set 'A') */
ACCW(PR_CTX0_A, 0x00000059); /* NVclass $059, nv10+: little endian */
ACCW(PR_CTX2_A, 0x11401140); /* DMA0, DMA1 instance = $1140 */
ACCW(PR_CTX3_A, 0x00000000); /* method traps disabled */
/* (setup set 'B') */
ACCW(PR_CTX0_B, 0x0000005a); /* NVclass $05a, nv10+: little endian */
ACCW(PR_CTX2_B, 0x11401140); /* DMA0, DMA1 instance = $1140 */
ACCW(PR_CTX3_B, 0x00000000); /* method traps disabled */
/* (setup set 'C') */
ACCW(PR_CTX0_C, 0x0000005b); /* NVclass $05b, nv10+: little endian */
ACCW(PR_CTX2_C, 0x11401140); /* DMA0, DMA1 instance = $1140 */
ACCW(PR_CTX3_C, 0x00000000); /* method traps disabled */
/* (setup set 'D') */
if (si->ps.card_arch != NV04A)
ACCW(PR_CTX0_D, 0x00000093); /* NVclass $093, nv10+: little endian */
else
ACCW(PR_CTX0_D, 0x0300a01c); /* NVclass $01c, patchcfg ROP_AND, userclip enable,
* context surface0 valid */
ACCW(PR_CTX2_D, 0x11401140); /* DMA0, DMA1 instance = $1140 */
ACCW(PR_CTX3_D, 0x00000000); /* method traps disabled */
/* (setup set 'E' if needed) */
if (si->ps.card_arch != NV04A)
{
ACCW(PR_CTX0_E, 0x0300a01c); /* NVclass $01c, patchcfg ROP_AND, userclip enable,
* context surface0 valid, nv10+: little endian */
ACCW(PR_CTX2_E, 0x11401140); /* DMA0, DMA1 instance = $1140 */
ACCW(PR_CTX3_E, 0x00000000); /* method traps disabled */
}
/*** PGRAPH ***/
if (si->ps.card_arch != NV04A)
{
/* set resetstate for most function blocks */
ACCW(DEBUG0, 0x0003ffff);
/* init some function blocks */
ACCW(DEBUG1, 0x00118701);
ACCW(DEBUG2, 0x24f82ad9);
ACCW(DEBUG3, 0x55de0030);
/* end resetstate for the function blocks */
ACCW(DEBUG0, 0x00000000);
/* disable specific functions */
ACCW(NV10_DEBUG4, 0);
}
else
{
/* init some function blocks */
ACCW(DEBUG0, 0x1231c001);
ACCW(DEBUG1, 0x72111101);
ACCW(DEBUG2, 0x11d5f071);
ACCW(DEBUG3, 0x10d4ff31);
}
/* reset all cache sets */
ACCW(CACHE1_1, 0);
ACCW(CACHE1_2, 0);
ACCW(CACHE1_3, 0);
ACCW(CACHE1_4, 0);
ACCW(CACHE1_5, 0);
ACCW(CACHE2_1, 0);
ACCW(CACHE2_2, 0);
ACCW(CACHE2_3, 0);
ACCW(CACHE2_4, 0);
ACCW(CACHE2_5, 0);
ACCW(CACHE3_1, 0);
ACCW(CACHE3_2, 0);
ACCW(CACHE3_3, 0);
ACCW(CACHE3_4, 0);
ACCW(CACHE3_5, 0);
ACCW(CACHE4_1, 0);
ACCW(CACHE4_2, 0);
ACCW(CACHE4_3, 0);
ACCW(CACHE4_4, 0);
ACCW(CACHE4_5, 0);
if (si->ps.card_arch != NV04A)
ACCW(NV10_CACHE5_1, 0);
ACCW(CACHE5_2, 0);
ACCW(CACHE5_3, 0);
ACCW(CACHE5_4, 0);
ACCW(CACHE5_5, 0);
if (si->ps.card_arch != NV04A)
ACCW(NV10_CACHE6_1, 0);
ACCW(CACHE6_2, 0);
ACCW(CACHE6_3, 0);
ACCW(CACHE6_4, 0);
ACCW(CACHE6_5, 0);
if (si->ps.card_arch != NV04A)
ACCW(NV10_CACHE7_1, 0);
ACCW(CACHE7_2, 0);
ACCW(CACHE7_3, 0);
ACCW(CACHE7_4, 0);
ACCW(CACHE7_5, 0);
if (si->ps.card_arch != NV04A)
ACCW(NV10_CACHE8_1, 0);
ACCW(CACHE8_2, 0);
ACCW(CACHE8_3, 0);
ACCW(CACHE8_4, 0);
ACCW(CACHE8_5, 0);
if (si->ps.card_arch != NV04A)
{
/* reset (disable) context switch stuff */
ACCW(NV10_CTX_SW1, 0);
ACCW(NV10_CTX_SW2, 0);
ACCW(NV10_CTX_SW3, 0);
ACCW(NV10_CTX_SW4, 0);
ACCW(NV10_CTX_SW5, 0);
}
/* setup accesible card memory range for acc engine */
ACCW(BBASE0, 0x00000000);
ACCW(BBASE1, 0x00000000);
ACCW(BBASE2, 0x00000000);
ACCW(BBASE3, 0x00000000);
ACCW(BLIMIT0, (si->ps.memory_size - 1));
ACCW(BLIMIT1, (si->ps.memory_size - 1));
ACCW(BLIMIT2, (si->ps.memory_size - 1));
ACCW(BLIMIT3, (si->ps.memory_size - 1));
if (si->ps.card_arch >= NV10A)
{
ACCW(NV10_BBASE4, 0x00000000);
ACCW(NV10_BBASE5, 0x00000000);
ACCW(NV10_BLIMIT4, (si->ps.memory_size - 1));
ACCW(NV10_BLIMIT5, (si->ps.memory_size - 1));
}
if (si->ps.card_arch >= NV20A)
{
/* fixme(?): assuming more BLIMIT registers here: Then how about BBASE6-9?
* (linux fixed value 'BLIMIT6-9' 0x01ffffff) */
ACCW(NV20_BLIMIT6, (si->ps.memory_size - 1));
ACCW(NV20_BLIMIT7, (si->ps.memory_size - 1));
ACCW(NV20_BLIMIT8, (si->ps.memory_size - 1));
ACCW(NV20_BLIMIT9, (si->ps.memory_size - 1));
}
/* disable all acceleration engine INT reguests */
ACCW(ACC_INTE, 0x00000000);
/* reset all acceration engine INT status bits */
ACCW(ACC_INTS, 0xffffffff);
if (si->ps.card_arch != NV04A)
{
/* context control enabled */
ACCW(NV10_CTX_CTRL, 0x10010100);
/* all acceleration buffers, pitches and colors are valid */
ACCW(NV10_ACC_STAT, 0xffffffff);
}
else
{
/* context control enabled */
ACCW(NV04_CTX_CTRL, 0x10010100);
/* all acceleration buffers, pitches and colors are valid */
ACCW(NV04_ACC_STAT, 0xffffffff);
}
/* enable acceleration engine command FIFO */
ACCW(FIFO_EN, 0x00000001);
/* pattern shape value = 8x8, 2 color */
ACCW(PAT_SHP, 0x00000000);
if (si->ps.card_arch != NV04A)
{
/* surface type is non-swizzle */
ACCW(NV10_SURF_TYP, 0x00000001);
}
else
{
/* surface type is non-swizzle */
ACCW(NV04_SURF_TYP, 0x00000001);
}
/*** Set pixel width and format ***/
switch(si->dm.space)
{
case B_CMAP8:
/* acc engine */
ACCW(FORMATS, 0x00001010);
if (si->ps.card_arch < NV30A)
ACCW(BPIXEL, 0x00111111); /* set depth 0-5: 4 bits per color */
else
ACCW(BPIXEL, 0x00000021); /* set depth 0-1: 5 bits per color */
ACCW(STRD_FMT, 0x03020202);
/* PRAMIN */
ACCW(PR_CTX1_0, 0x00000302); /* format is X24Y8, LSB mono */
ACCW(PR_CTX1_1, 0x00000302); /* format is X24Y8, LSB mono */
ACCW(PR_CTX1_2, 0x00000202); /* format is X16A8Y8, LSB mono */
ACCW(PR_CTX1_3, 0x00000302); /* format is X24Y8, LSB mono */
ACCW(PR_CTX1_4, 0x00000302); /* format is X24Y8, LSB mono */
ACCW(PR_CTX1_5, 0x00000302); /* format is X24Y8, LSB mono */
ACCW(PR_CTX1_9, 0x00000302); /* format is X24Y8, LSB mono */
ACCW(PR_CTX2_9, 0x00000302); /* dma_instance 0 valid, instance 1 invalid */
ACCW(PR_CTX1_B, 0x00000000); /* format is invalid */
ACCW(PR_CTX1_C, 0x00000000); /* format is invalid */
if (si->ps.card_arch == NV04A)
{
ACCW(PR_CTX1_D, 0x00000302); /* format is X24Y8, LSB mono */
}
else
{
ACCW(PR_CTX1_D, 0x00000000); /* format is invalid */
ACCW(PR_CTX1_E, 0x00000302); /* format is X24Y8, LSB mono */
}
break;
case B_RGB15_LITTLE:
/* acc engine */
ACCW(FORMATS, 0x00002071);
if (si->ps.card_arch < NV30A)
ACCW(BPIXEL, 0x00226222); /* set depth 0-5: 4 bits per color */
else
ACCW(BPIXEL, 0x00000042); /* set depth 0-1: 5 bits per color */
ACCW(STRD_FMT, 0x09080808);
/* PRAMIN */
ACCW(PR_CTX1_0, 0x00000902); /* format is X17RGB15, LSB mono */
ACCW(PR_CTX1_1, 0x00000902); /* format is X17RGB15, LSB mono */
ACCW(PR_CTX1_2, 0x00000802); /* format is X16A1RGB15, LSB mono */
ACCW(PR_CTX1_3, 0x00000902); /* format is X17RGB15, LSB mono */
ACCW(PR_CTX1_4, 0x00000902); /* format is X17RGB15, LSB mono */
ACCW(PR_CTX1_5, 0x00000902); /* format is X17RGB15, LSB mono */
ACCW(PR_CTX1_9, 0x00000902); /* format is X17RGB15, LSB mono */
ACCW(PR_CTX2_9, 0x00000902); /* dma_instance 0 valid, instance 1 invalid */
if (si->ps.card_arch == NV04A)
{
ACCW(PR_CTX1_B, 0x00000702); /* format is X1RGB15, LSB mono */
ACCW(PR_CTX1_C, 0x00000702); /* format is X1RGB15, LSB mono */
}
else
{
ACCW(PR_CTX1_B, 0x00000902); /* format is X17RGB15, LSB mono */
ACCW(PR_CTX1_C, 0x00000902); /* format is X17RGB15, LSB mono */
ACCW(PR_CTX1_E, 0x00000902); /* format is X17RGB15, LSB mono */
}
ACCW(PR_CTX1_D, 0x00000902); /* format is X17RGB15, LSB mono */
break;
case B_RGB16_LITTLE:
/* acc engine */
ACCW(FORMATS, 0x000050C2);
if (si->ps.card_arch < NV30A)
ACCW(BPIXEL, 0x00556555); /* set depth 0-5: 4 bits per color */
else
ACCW(BPIXEL, 0x000000a5); /* set depth 0-1: 5 bits per color */
if (si->ps.card_arch == NV04A)
ACCW(STRD_FMT, 0x0c0b0b0b);
else
ACCW(STRD_FMT, 0x000b0b0c);
/* PRAMIN */
ACCW(PR_CTX1_0, 0x00000c02); /* format is X16RGB16, LSB mono */
ACCW(PR_CTX1_1, 0x00000c02); /* format is X16RGB16, LSB mono */
ACCW(PR_CTX1_2, 0x00000b02); /* format is A16RGB16, LSB mono */
ACCW(PR_CTX1_3, 0x00000c02); /* format is X16RGB16, LSB mono */
ACCW(PR_CTX1_4, 0x00000c02); /* format is X16RGB16, LSB mono */
ACCW(PR_CTX1_5, 0x00000c02); /* format is X16RGB16, LSB mono */
ACCW(PR_CTX1_9, 0x00000c02); /* format is X16RGB16, LSB mono */
ACCW(PR_CTX2_9, 0x00000c02); /* dma_instance 0 valid, instance 1 invalid */
if (si->ps.card_arch == NV04A)
{
ACCW(PR_CTX1_B, 0x00000702); /* format is X1RGB15, LSB mono */
ACCW(PR_CTX1_C, 0x00000702); /* format is X1RGB15, LSB mono */
}
else
{
ACCW(PR_CTX1_B, 0x00000c02); /* format is X16RGB16, LSB mono */
ACCW(PR_CTX1_C, 0x00000c02); /* format is X16RGB16, LSB mono */
ACCW(PR_CTX1_E, 0x00000c02); /* format is X16RGB16, LSB mono */
}
ACCW(PR_CTX1_D, 0x00000c02); /* format is X16RGB16, LSB mono */
break;
case B_RGB32_LITTLE:case B_RGBA32_LITTLE:
/* acc engine */
ACCW(FORMATS, 0x000070e5);
if (si->ps.card_arch < NV30A)
ACCW(BPIXEL, 0x0077d777); /* set depth 0-5: 4 bits per color */
else
ACCW(BPIXEL, 0x000000e7); /* set depth 0-1: 5 bits per color */
ACCW(STRD_FMT, 0x0e0d0d0d);
/* PRAMIN */
ACCW(PR_CTX1_0, 0x00000e02); /* format is X8RGB24, LSB mono */
ACCW(PR_CTX1_1, 0x00000e02); /* format is X8RGB24, LSB mono */
ACCW(PR_CTX1_2, 0x00000d02); /* format is A8RGB24, LSB mono */
ACCW(PR_CTX1_3, 0x00000e02); /* format is X8RGB24, LSB mono */
ACCW(PR_CTX1_4, 0x00000e02); /* format is X8RGB24, LSB mono */
ACCW(PR_CTX1_5, 0x00000e02); /* format is X8RGB24, LSB mono */
ACCW(PR_CTX1_9, 0x00000e02); /* format is X8RGB24, LSB mono */
ACCW(PR_CTX2_9, 0x00000e02); /* dma_instance 0 valid, instance 1 invalid */
ACCW(PR_CTX1_B, 0x00000e02); /* format is X8RGB24, LSB mono */
ACCW(PR_CTX1_C, 0x00000e02); /* format is X8RGB24, LSB mono */
ACCW(PR_CTX1_D, 0x00000e02); /* format is X8RGB24, LSB mono */
if (si->ps.card_arch >= NV10A)
ACCW(PR_CTX1_E, 0x00000e02); /* format is X8RGB24, LSB mono */
break;
default:
LOG(8,("ACC: init, invalid bit depth\n"));
return B_ERROR;
}
/* setup some extra stuff for NV30A and later */
if (si->ps.card_arch >= NV30A)
{
/*
fixme: Does not belong here (and not needed?)
if(!chip->flatPanel)
{
chip->PRAMDAC0[0x0578/4] = state->vpllB; //0x00680578 = ??? never modified!
chip->PRAMDAC0[0x057C/4] = state->vpll2B; //0x0068057c = ??? never modified!
}
*/
/* activate Zcullflush(?) */
ACCW(DEBUG3, (ACCR(DEBUG3) | 0x00000001));
/* unknown */
ACCW(NV30_WHAT, (ACCR(NV30_WHAT) | 0x00040000));
}
/*** setup screen location and pitch ***/
switch (si->ps.card_arch)
{
case NV04A:
case NV10A:
default:
/* location of active screen in framebuffer */
ACCW(OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
ACCW(OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
ACCW(OFFSET2, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
ACCW(OFFSET3, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
ACCW(OFFSET4, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
ACCW(OFFSET5, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
// ACCW(OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
/* setup buffer pitch */
ACCW(PITCH0, (si->fbc.bytes_per_row & 0x0000ffff));
ACCW(PITCH1, (si->fbc.bytes_per_row & 0x0000ffff));
ACCW(PITCH2, (si->fbc.bytes_per_row & 0x0000ffff));
ACCW(PITCH3, (si->fbc.bytes_per_row & 0x0000ffff));
ACCW(PITCH4, (si->fbc.bytes_per_row & 0x0000ffff));
break;
case NV20A:
case NV30A:
case NV40A:
/* location of active screen in framebuffer */
ACCW(NV20_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
ACCW(NV20_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
ACCW(NV20_OFFSET2, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
ACCW(NV20_OFFSET3, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
/* setup buffer pitch */
ACCW(NV20_PITCH0, (si->fbc.bytes_per_row & 0x0000ffff));
ACCW(NV20_PITCH1, (si->fbc.bytes_per_row & 0x0000ffff));
ACCW(NV20_PITCH2, (si->fbc.bytes_per_row & 0x0000ffff));
ACCW(NV20_PITCH3, (si->fbc.bytes_per_row & 0x0000ffff));
// ACCW(PITCH0, (si->fbc.bytes_per_row & 0x0000ffff));
break;
}
/*** setup tile and pipe stuff ***/
if (si->ps.card_arch >= NV10A)
{
/*
fixme: setup elsewhere (does not belong here):
chip->PRAMDAC[0x00000404/4] |= (1 << 25);//0x00680404 = ???
*/
/* setup acc engine tile stuff: */
/* reset tile adresses */
ACCW(NV10_FBTIL0AD, 0);
ACCW(NV10_FBTIL1AD, 0);
ACCW(NV10_FBTIL2AD, 0);
ACCW(NV10_FBTIL3AD, 0);
ACCW(NV10_FBTIL4AD, 0);
ACCW(NV10_FBTIL5AD, 0);
ACCW(NV10_FBTIL6AD, 0);
ACCW(NV10_FBTIL7AD, 0);
/* copy tile setup stuff from 'source' to acc engine */
if (si->ps.card_arch >= NV20A)
{
/* unknown: */
ACCW(NV20_WHAT0, ACCR(NV20_FBWHAT0));
ACCW(NV20_WHAT1, ACCR(NV20_FBWHAT1));
}
/* tile 0: */
/* tile invalid, tile adress = $00000 (18bit) */
ACCW(NV10_TIL0AD, ACCR(NV10_FBTIL0AD));
/* set tile end adress (18bit) */
ACCW(NV10_TIL0ED, ACCR(NV10_FBTIL0ED));
/* set tile size pitch (8bit: b8-15) */
ACCW(NV10_TIL0PT, ACCR(NV10_FBTIL0PT));
/* set tile status */
ACCW(NV10_TIL0ST, ACCR(NV10_FBTIL0ST));
/* tile 1: */
ACCW(NV10_TIL1AD, ACCR(NV10_FBTIL1AD));
ACCW(NV10_TIL1ED, ACCR(NV10_FBTIL1ED));
ACCW(NV10_TIL1PT, ACCR(NV10_FBTIL1PT));
ACCW(NV10_TIL1ST, ACCR(NV10_FBTIL1ST));
/* tile 2: */
ACCW(NV10_TIL2AD, ACCR(NV10_FBTIL2AD));
ACCW(NV10_TIL2ED, ACCR(NV10_FBTIL2ED));
ACCW(NV10_TIL2PT, ACCR(NV10_FBTIL2PT));
ACCW(NV10_TIL2ST, ACCR(NV10_FBTIL2ST));
/* tile 3: */
ACCW(NV10_TIL3AD, ACCR(NV10_FBTIL3AD));
ACCW(NV10_TIL3ED, ACCR(NV10_FBTIL3ED));
ACCW(NV10_TIL3PT, ACCR(NV10_FBTIL3PT));
ACCW(NV10_TIL3ST, ACCR(NV10_FBTIL3ST));
/* tile 4: */
ACCW(NV10_TIL4AD, ACCR(NV10_FBTIL4AD));
ACCW(NV10_TIL4ED, ACCR(NV10_FBTIL4ED));
ACCW(NV10_TIL4PT, ACCR(NV10_FBTIL4PT));
ACCW(NV10_TIL4ST, ACCR(NV10_FBTIL4ST));
/* tile 5: */
ACCW(NV10_TIL5AD, ACCR(NV10_FBTIL5AD));
ACCW(NV10_TIL5ED, ACCR(NV10_FBTIL5ED));
ACCW(NV10_TIL5PT, ACCR(NV10_FBTIL5PT));
ACCW(NV10_TIL5ST, ACCR(NV10_FBTIL5ST));
/* tile 6: */
ACCW(NV10_TIL6AD, ACCR(NV10_FBTIL6AD));
ACCW(NV10_TIL6ED, ACCR(NV10_FBTIL6ED));
ACCW(NV10_TIL6PT, ACCR(NV10_FBTIL6PT));
ACCW(NV10_TIL6ST, ACCR(NV10_FBTIL6ST));
/* tile 7: */
ACCW(NV10_TIL7AD, ACCR(NV10_FBTIL7AD));
ACCW(NV10_TIL7ED, ACCR(NV10_FBTIL7ED));
ACCW(NV10_TIL7PT, ACCR(NV10_FBTIL7PT));
ACCW(NV10_TIL7ST, ACCR(NV10_FBTIL7ST));
/* setup pipe */
/* set eyetype to local, lightning is off */
ACCW(NV10_XFMOD0, 0x10000000);
/* disable all lights */
ACCW(NV10_XFMOD1, 0x00000000);
ACCW(NV10_PIPEADR, 0x00000040);
ACCW(NV10_PIPEDAT, 0x00000008);
ACCW(NV10_PIPEADR, 0x00000200);
for (cnt = 0; cnt < (3 * 16); cnt++) ACCW(NV10_PIPEDAT, 0x00000000);
ACCW(NV10_PIPEADR, 0x00000040);
ACCW(NV10_PIPEDAT, 0x00000000);
ACCW(NV10_PIPEADR, 0x00000800);
for (cnt = 0; cnt < (16 * 16); cnt++) ACCW(NV10_PIPEDAT, 0x00000000);
/* turn lightning on */
ACCW(NV10_XFMOD0, 0x30000000);
/* set light 1 to infinite type, other lights remain off */
ACCW(NV10_XFMOD1, 0x00000004);
ACCW(NV10_PIPEADR, 0x00006400);
for (cnt = 0; cnt < (59 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000);
ACCW(NV10_PIPEADR, 0x00006800);
for (cnt = 0; cnt < (47 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000);
ACCW(NV10_PIPEADR, 0x00006c00);
for (cnt = 0; cnt < (3 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000);
ACCW(NV10_PIPEADR, 0x00007000);
for (cnt = 0; cnt < (19 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000);
ACCW(NV10_PIPEADR, 0x00007400);
for (cnt = 0; cnt < (12 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000);
ACCW(NV10_PIPEADR, 0x00007800);
for (cnt = 0; cnt < (12 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000);
ACCW(NV10_PIPEADR, 0x00004400);
for (cnt = 0; cnt < (8 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000);
ACCW(NV10_PIPEADR, 0x00000000);
for (cnt = 0; cnt < 16; cnt++) ACCW(NV10_PIPEDAT, 0x00000000);
ACCW(NV10_PIPEADR, 0x00000040);
for (cnt = 0; cnt < 4; cnt++) ACCW(NV10_PIPEDAT, 0x00000000);
}
/*** setup acceleration engine command shortcuts (so via fifo) ***/
/* (b31 = 1 selects 'config' function?) */
ACCW(FIFO_00800000, 0x80000000); /* Raster OPeration */
ACCW(FIFO_00802000, 0x80000001); /* Clip */
ACCW(FIFO_00804000, 0x80000002); /* Pattern */
ACCW(FIFO_00806000, 0x80000010); /* Pixmap (not used) */
ACCW(FIFO_00808000, 0x80000011); /* Blit */
ACCW(FIFO_0080a000, 0x80000012); /* Bitmap */
ACCW(FIFO_0080c000, 0x80000016); /* Line (not used) */
ACCW(FIFO_0080e000, 0x80000014); /* ??? (not used) */
/* do first actual acceleration engine command:
* setup clipping region (workspace size) to 32768 x 32768 pixels:
* wait for room in fifo for clipping cmd if needed.
* (fifo holds 256 32bit words: count those, not bytes) */
while (((ENG_REG16(RG16_CLP_FIFOFREE)) >> 2) < 2)
// while (((ENG_REG16(RG16_CLP_FIFOFREE)) >> 2) < 2)
while (0)
{
/* snooze a bit so I do not hammer the bus */
snooze (10);
}
/* now setup clipping (writing 2 32bit words) */
ACCW(CLP_TOPLEFT, 0x00000000);
ACCW(CLP_WIDHEIGHT, 0x80008000);
// ACCW(CLP_TOPLEFT, 0x00000000);
// ACCW(CLP_WIDHEIGHT, 0x80008000);
return B_OK;
}
src/add-ons/accelerants/skeleton/engine/general.c
+44 -38
View File
@@ -9,7 +9,7 @@
#include "std.h"
static status_t test_ram(void);
static status_t nvxx_general_powerup (void);
static status_t engxx_general_powerup (void);
static status_t eng_general_bios_to_powergraphics(void);
static void eng_dump_configuration_space (void)
@@ -93,7 +93,7 @@ status_t eng_general_powerup()
si->ps.card_type = NV04;
si->ps.card_arch = NV04A;
LOG(4,("POWERUP: Detected Nvidia TNT1 (NV04)\n"));
status = nvxx_general_powerup();
status = engxx_general_powerup();
break;
default:
LOG(8,("POWERUP: Failed to detect valid card 0x%08x\n",CFGR(DEVID)));
@@ -283,9 +283,9 @@ void set_crtc_owner(bool head)
}
}
static status_t nvxx_general_powerup()
static status_t engxx_general_powerup()
{
LOG(4, ("INIT: NV powerup\n"));
LOG(4, ("INIT: card powerup\n"));
/* setup cardspecs */
/* note:
@@ -303,7 +303,7 @@ static status_t nvxx_general_powerup()
/* update the cardspecs in the shared_info PINS struct according to reported
* specs as much as is possible;
* this also coldstarts the card if possible (executes BIOS CMD script(s)) */
parse_pins();
// parse_pins();
}
else
{
@@ -311,7 +311,7 @@ static status_t nvxx_general_powerup()
}
/* get RAM size and fake panel startup (panel init code is still missing) */
fake_panel_start();
// fake_panel_start();
/* log the final card specifications */
dump_pins();
@@ -406,7 +406,7 @@ status_t eng_general_head_select(bool cross)
static status_t eng_general_bios_to_powergraphics()
{
/* let acc engine make power off/power on cycle to start 'fresh' */
ENG_RG32(RG32_PWRUPCTRL) = 0x13110011;
// ENG_RG32(RG32_PWRUPCTRL) = 0x13110011;
snooze(1000);
/* power-up all hardware function blocks */
@@ -419,17 +419,18 @@ static status_t eng_general_bios_to_powergraphics()
* bit 8: PFIFO,
* bit 4: PMEDIA,
* bit 0: TVOUT. (> NV04A) */
ENG_RG32(RG32_PWRUPCTRL) = 0x13111111;
// ENG_RG32(RG32_PWRUPCTRL) = 0x13111111;
/* select colormode CRTC registers base adresses */
ENG_REG8(RG8_MISCW) = 0xcb;
// ENG_REG8(RG8_MISCW) = 0xcb;
/* enable access to primary head */
set_crtc_owner(0);
// set_crtc_owner(0);
/* unlock head's registers for R/W access */
CRTCW(LOCK, 0x57);
CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
if (si->ps.secondary_head)
// CRTCW(LOCK, 0x57);
// CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
// if (si->ps.secondary_head)
if (0)
{
/* enable access to secondary head */
set_crtc_owner(1);
@@ -439,15 +440,17 @@ static status_t eng_general_bios_to_powergraphics()
}
/* turn off both displays and the hardcursors (also disables transfers) */
head1_dpms(false, false, false);
head1_cursor_hide();
if (si->ps.secondary_head)
// head1_dpms(false, false, false);
// head1_cursor_hide();
// if (si->ps.secondary_head)
if (0)
{
head2_dpms(false, false, false);
head2_cursor_hide();
// head2_dpms(false, false, false);
// head2_cursor_hide();
}
if (si->ps.secondary_head)
// if (si->ps.secondary_head)
if (0)
{
/* switch overlay engine to CRTC1 */
/* bit 17: GPU FP port #1 (confirmed NV25, NV28, confirmed not on NV34),
@@ -463,7 +466,7 @@ static status_t eng_general_bios_to_powergraphics()
/* enable 'enhanced' mode on primary head: */
/* enable access to primary head */
set_crtc_owner(0);
// set_crtc_owner(0);
/* note: 'BUFFER' is a non-standard register in behaviour(!) on most
* NV11's like the GeForce2 MX200, while the MX400 and non-NV11 cards
* behave normally.
@@ -471,28 +474,29 @@ static status_t eng_general_bios_to_powergraphics()
*
* Double-write action needed on those strange NV11 cards: */
/* RESET: don't doublebuffer CRTC access: set programmed values immediately... */
CRTCW(BUFFER, 0xff);
// CRTCW(BUFFER, 0xff);
/* ... and use fine pitched CRTC granularity on > NV4 cards (b2 = 0) */
/* note: this has no effect on possible bandwidth issues. */
CRTCW(BUFFER, 0xfb);
// CRTCW(BUFFER, 0xfb);
/* select VGA mode (old VGA register) */
CRTCW(MODECTL, 0xc3);
// CRTCW(MODECTL, 0xc3);
/* select graphics mode (old VGA register) */
SEQW(MEMMODE, 0x0e);
// SEQW(MEMMODE, 0x0e);
/* select 8 dots character clocks (old VGA register) */
SEQW(CLKMODE, 0x21);
// SEQW(CLKMODE, 0x21);
/* select VGA mode (old VGA register) */
GRPHW(MODE, 0x00);
// GRPHW(MODE, 0x00);
/* select graphics mode (old VGA register) */
GRPHW(MISC, 0x01);
// GRPHW(MISC, 0x01);
/* select graphics mode (old VGA register) */
ATBW(MODECTL, 0x01);
// ATBW(MODECTL, 0x01);
/* enable 'enhanced mode', enable Vsync & Hsync,
* set DAC palette to 8-bit width, disable large screen */
CRTCW(REPAINT1, 0x04);
// CRTCW(REPAINT1, 0x04);
/* enable 'enhanced' mode on secondary head: */
if (si->ps.secondary_head)
// if (si->ps.secondary_head)
if (0)
{
/* enable access to secondary head */
set_crtc_owner(1);
@@ -527,20 +531,20 @@ static status_t eng_general_bios_to_powergraphics()
}
/* enable palettes */
DACW(GENCTRL, 0x00100100);
if (si->ps.secondary_head) DAC2W(GENCTRL, 0x00100100);
// DACW(GENCTRL, 0x00100100);
// if (si->ps.secondary_head) DAC2W(GENCTRL, 0x00100100);
/* enable programmable PLLs */
DACW(PLLSEL, 0x10000700);
if (si->ps.secondary_head) DACW(PLLSEL, (DACR(PLLSEL) | 0x20000800));
// DACW(PLLSEL, 0x10000700);
// if (si->ps.secondary_head) DACW(PLLSEL, (DACR(PLLSEL) | 0x20000800));
/* turn on DAC and make sure detection testsignal routing is disabled
* (b16 = disable DAC,
* b12 = enable testsignal output */
DACW(TSTCTRL, (DACR(TSTCTRL) & 0xfffeefff));
// DACW(TSTCTRL, (DACR(TSTCTRL) & 0xfffeefff));
/* turn on DAC2 if it exists
* (NOTE: testsignal function block resides in DAC1 only (!)) */
if (si->ps.secondary_head) DAC2W(TSTCTRL, (DAC2R(TSTCTRL) & 0xfffeefff));
// if (si->ps.secondary_head) DAC2W(TSTCTRL, (DAC2R(TSTCTRL) & 0xfffeefff));
/* setup AGP:
* Note:
@@ -549,7 +553,7 @@ static status_t eng_general_bios_to_powergraphics()
eng_agp_setup();
/* turn screen one on */
head1_dpms(true, true, true);
// head1_dpms(true, true, true);
return B_OK;
}
@@ -758,7 +762,9 @@ status_t eng_general_validate_pic_size (display_mode *target, uint32 *bytes_per_
if (max_acc_width <= max_crtc_width)
{
/* check if we can setup this mode with acceleration */
*acc_mode = true;
// *acc_mode = true;
//blocking acc totally:
*acc_mode = false;
/* virtual_width */
if (target->virtual_width > max_acc_width) *acc_mode = false;
/* virtual_height */