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First of a set of patches by Euan Kirkhope:

Browse Source 
* Headers updated
 * PLL errata workarounds
 * Radeon asic type overhaul (consolidated)
 * Device IDs Updated.
 * support for X-series devices with legacy bios type
 * minor tidy ups / compiler warnings (casts)


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@20271 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
2007-03-01 09:00:49 +00:00
parent 3bf72bcb7c
commit 8841d8bcd1
32 changed files with 695 additions and 367 deletions
Download Patch File Download Diff File Expand all files Collapse all files
headers/private/graphics/radeon/2d_regs.h
+1 -1
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@@ -183,7 +183,7 @@
#define RADEON_DST_LINE_START 0x1600
#define RADEON_DST_LINE_END 0x1604
#define RADEON_DST_LINE_PATCOUNT 0x1608
# define RADEON_BRES_CNTL_SHIFT 8
#define RADEON_DEFAULT_OFFSET 0x16e0
#define RADEON_DEFAULT_PITCH 0x16e4
headers/private/graphics/radeon/buscntrl_regs.h
+1 -1
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@@ -56,6 +56,6 @@
#define RADEON_HOST_PATH_CNTL 0x0130
# define RADEON_HDP_SOFT_RESET (1 << 26)
# define RADEON_HDP_APER_CNTL (1 << 23)
#endif
headers/private/graphics/radeon/config_regs.h
+9 -2
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@@ -11,9 +11,16 @@
#define _CONFIG_REGS_H
// mmio registers
#define RADEON_CONFIG_APER_0_BASE 0x0100
#define RADEON_CONFIG_APER_1_BASE 0x0104
#define RADEON_CONFIG_APER_SIZE 0x0108
#define RADEON_CONFIG_CNTL 0x00e0
#define RADEON_CFG_ATI_REV_ID_SHIFT 16
#define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)
# define RADEON_CFG_ATI_REV_A11 (0 << 16)
# define RADEON_CFG_ATI_REV_A12 (1 << 16)
# define RADEON_CFG_ATI_REV_A13 (2 << 16)
# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)
#define RADEON_CFG_ATI_REV_ID_SHIFT 16
#define RADEON_CONFIG_MEMSIZE 0x00f8
# define RADEON_CONFIG_MEMSIZE_MASK 0x1ff00000
headers/private/graphics/radeon/fp_regs.h
+8
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@@ -108,5 +108,13 @@
#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8
#define RADEON_BIOS_0_SCRATCH 0x0010
#define RADEON_BIOS_1_SCRATCH 0x0014
#define RADEON_BIOS_2_SCRATCH 0x0018
#define RADEON_BIOS_3_SCRATCH 0x001c
#define RADEON_BIOS_4_SCRATCH 0x0020
#define RADEON_BIOS_5_SCRATCH 0x0024
#define RADEON_BIOS_6_SCRATCH 0x0028
#define RADEON_BIOS_7_SCRATCH 0x002c
#endif
headers/private/graphics/radeon/memcntrl_regs.h
+6 -2
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@@ -12,7 +12,11 @@
#define RADEON_AGP_BASE 0x0170
#define RADEON_MEM_CNTL 0x0140
# define RADEON_MEM_NUM_CHANNELS_MASK 0x01
# define RADEON_MEM_USE_B_CH_ONLY (1<<1)
# define RV100_HALF_MODE (1<<3)
# define R300_MEM_NUM_CHANNELS_MASK 0x03
# define R300_MEM_USE_CD_CH_ONLY (1<<2)
#define RADEON_MC_AGP_LOCATION 0x014c
#define RADEON_MC_FB_LOCATION 0x0148
#define RADEON_MEM_INIT_LAT_TIMER 0x0154
@@ -20,7 +24,7 @@
# define RADEON_MEM_CFG_TYPE_MASK (1 << 30)
# define RADEON_MEM_CFG_SDR (0 << 30)
# define RADEON_MEM_CFG_DDR (1 << 30)
#define RADEON_GC_NB_TOM 0x015c
#define RADEON_NB_TOM 0x015c
#define RADEON_DISPLAY_BASE_ADDRESS 0x023c
#define RADEON_CRTC2_DISPLAY_BASE_ADDRESS 0x033c
#define RADEON_OV0_BASE_ADDRESS 0x043c
headers/private/graphics/radeon/overlay_regs.h
+2 -2
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@@ -40,14 +40,14 @@
# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L
# define R200_SCALER_TEMPORAL_DEINT 0x00002000L
# define RADEON_SCALER_CRTC_SEL 0x00004000L
//# define RADEON_SCALER_SMART_SWITCH 0x00008000L
# define RADEON_SCALER_SMART_SWITCH 0x00008000L
# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L
# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L
# define RADEON_SCALER_DIS_LIMIT 0x08000000L
# define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L
# define RADEON_SCALER_INT_EMU 0x20000000L
# define RADEON_SCALER_ENABLE 0x40000000L
# define RADEON_SCALER_SOFT_RESET 0x80000000L
# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L
#define RADEON_OV0_V_INC 0x0424
#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428
# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L
headers/private/graphics/radeon/pll_access.h
+7 -2
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@@ -13,10 +13,15 @@
#include "mmio.h"
// r300: to be called after each CLOCK_CNTL_INDEX access;
// to be called after each CLOCK_CNTL_INDEX access;
// all functions declared in this header take care of that
// (hardware bug fix suggested by XFree86)
void R300_PLLFix( vuint8 *regs, radeon_type asic );
void RADEONPllErrataAfterIndex( vuint8 *regs, radeon_type asic );
// to be called after each CLOCK_CNTL_DATA access;
// all functions declared in this header take care of that
// (hardware bug fix suggested by XFree86)
void RADEONPllErrataAfterData( vuint8 *regs, radeon_type asic );
// in general:
// - the PLL is connected via special port
headers/private/graphics/radeon/pll_regs.h
+69 -2
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@@ -19,7 +19,18 @@
# define RADEON_PLL_DIV_SEL_DIV1 (1 << 8)
# define RADEON_PLL_DIV_SEL_DIV2 (2 << 8)
# define RADEON_PLL_DIV_SEL_DIV3 (3 << 8)
#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */
# define RADEON_SCLK_DYN_START_CNTL (1 << 15)
// PLL Power management registers
#define RADEON_CLK_PWRMGT_CNTL 0x0014
# define RADEON_ENGIN_DYNCLK_MODE (1 << 12)
# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13)
# define RADEON_ACTIVE_HILO_LAT_SHIFT 13
# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)
# define RADEON_DYN_STOP_MODE_MASK (7 << 21)
#define RADEON_PLL_PWRMGT_CNTL 0x0015
# define RADEON_TCL_BYPASS_DISABLE (1 << 20)
// indirect PLL registers
#define RADEON_CLK_PIN_CNTL 0x0001
@@ -55,12 +66,46 @@
# define RADEON_ECP_DIV_VCLK_2 (1 << 8)
# define RADEON_VCLK_ECP_CNTL_BYTE_CLK_POST_DIV_SHIFT 16
# define RADEON_VCLK_ECP_CNTL_BYTE_CLK_POST_DIV_MASK (3 << 16)
# define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
#define RADEON_HTOTAL_CNTL 0x0009
#define RADEON_SCLK_CNTL 0x000d
#define RADEON_SCLK_CNTL 0x000d /* PLL */
# define RADEON_SCLK_SRC_SEL_MASK 0x0007
# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8
# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008
# define RADEON_SCLK_FORCEON_MASK 0xffff8000
#define RADEON_SCLK_MORE_CNTL 0x0035
# define RADEON_SCLK_FORCE_DISP2 (1<<15)
# define RADEON_SCLK_FORCE_CP (1<<16)
# define RADEON_SCLK_FORCE_HDP (1<<17)
# define RADEON_SCLK_FORCE_DISP1 (1<<18)
# define RADEON_SCLK_FORCE_TOP (1<<19)
# define RADEON_SCLK_FORCE_E2 (1<<20)
# define RADEON_SCLK_FORCE_SE (1<<21)
# define RADEON_SCLK_FORCE_IDCT (1<<22)
# define RADEON_SCLK_FORCE_VIP (1<<23)
# define RADEON_SCLK_FORCE_RE (1<<24)
# define RADEON_SCLK_FORCE_PB (1<<25)
# define RADEON_SCLK_FORCE_TAM (1<<26)
# define RADEON_SCLK_FORCE_TDM (1<<27)
# define RADEON_SCLK_FORCE_RB (1<<28)
# define RADEON_SCLK_FORCE_TV_SCLK (1<<29)
# define RADEON_SCLK_FORCE_SUBPIC (1<<30)
# define RADEON_SCLK_FORCE_OV0 (1<<31)
# define R300_SCLK_FORCE_VAP (1<<21)
# define R300_SCLK_FORCE_SR (1<<25)
# define R300_SCLK_FORCE_PX (1<<26)
# define R300_SCLK_FORCE_TX (1<<27)
# define R300_SCLK_FORCE_US (1<<28)
# define R300_SCLK_FORCE_SU (1<<30)
#define R300_SCLK_CNTL2 0x1e /* PLL */
# define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10)
# define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11)
# define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12)
# define R300_SCLK_FORCE_TCL (1<<13)
# define R300_SCLK_FORCE_CBA (1<<14)
# define R300_SCLK_FORCE_GA (1<<15)
#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */
# define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007
# define RADEON_SCLK_MORE_FORCEON 0x0700
#define RADEON_MCLK_CNTL 0x0012
# define RADEON_FORCEON_MCLKA (1 << 16)
@@ -69,6 +114,13 @@
# define RADEON_FORCEON_YCLKB (1 << 19)
# define RADEON_FORCEON_MC (1 << 20)
# define RADEON_FORCEON_AIC (1 << 21)
# define R300_DISABLE_MC_MCLKA (1 << 21)
# define R300_DISABLE_MC_MCLKB (1 << 21)
#define RADEON_MCLK_MISC 0x001f /* PLL */
# define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1<<12)
# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1<<13)
# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14)
# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15)
#define RADEON_P2PLL_CNTL 0x002a
# define RADEON_P2PLL_RESET (1 << 0)
# define RADEON_P2PLL_SLEEP (1 << 1)
@@ -90,8 +142,23 @@
# define RADEON_PIXCLK_TV_SRC_SEL_MASK (1 << 8)
# define RADEON_PIXCLK_TV_SRC_SEL_PIXCLK (0 << 8)
# define RADEON_PIXCLK_TV_SRC_SEL_PIX2CLK (1 << 8)
# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02
# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6)
# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7)
# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8)
# define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)
# define R300_DVOCLK_ALWAYS_ONb (1 << 10)
# define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11)
# define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12)
# define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13)
# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)
# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)
# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)
# define R300_P2G2CLK_ALWAYS_ONb (1 << 18)
# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)
# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
#define RADEON_HTOTAL2_CNTL 0x002e
headers/private/graphics/radeon/radeon_interface.h
+46 -28
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@@ -17,7 +17,7 @@
#include <OS.h>
#include "video_overlay.h"
#include "benaphore.h"
#include "ddc.h"
// magic code for ioctls
#define RADEON_PRIVATE_DATA_MAGIC 'TKRA'
@@ -94,31 +94,46 @@ typedef enum {
// type of ASIC
typedef enum {
rt_r100, // original Radeon
rt_ve, // original VE version
rt_m6, // original mobile Radeon
rt_rv100, // original VE version
rt_rs100, // IGP 320M
rt_rv200, // Radeon 7500
rt_m7, // mobile Radeon 7500
rt_rs200, // IGP 330M/340M/350M
rt_r200, // Radeon 8500/9100
rt_rv250, // Radeon 9000
rt_m9, // mobile Radeon 9000
rt_rv280, // Radeon 9200
rt_m9plus, // mobile Radeon 9200
// from here on, r300 and up must be located as ATI modified the PLL
// with r300 and the code only tests for >= rt_r300
rt_rs300, // IGP rs300
rt_rv280, // Radeon 9200
// from here on, r300 and up must be located as ATI modified the
// PLL design and the PLL code only tests for >= rt_r300
rt_r300, // Radeon 9700
rt_r300_4p, // Radeon 9500
rt_rv350, // Radeon 9600
rt_m10, // mobile Radeon 9600
rt_rv360, // Radeon 9600
rt_r350, // Radeon 9800
rt_r360, // Radeon 9800
rt_m11 // Radeon 9700 Mobility
rt_rv350, // Radeon 9600
rt_rv380, // X600
rt_r420 // X800
} radeon_type;
#define IS_RV100_VARIANT ( \
(ai->si->asic == rt_rv100) || \
(ai->si->asic == rt_rv200) || \
(ai->si->asic == rt_rs100) || \
(ai->si->asic == rt_rs200) || \
(ai->si->asic == rt_rv250) || \
(ai->si->asic == rt_rv280) || \
(ai->si->asic == rt_rs300))
#define IS_DI_R300_VARIANT ( \
(di->asic == rt_r300) || \
(di->asic == rt_r350) || \
(di->asic == rt_rv350) || \
(di->asic == rt_rv380) || \
(di->asic == rt_r420))
#define IS_R300_VARIANT ( \
(ai->si->asic == rt_r300) || \
(ai->si->asic == rt_r350) || \
(ai->si->asic == rt_rv350) || \
(ai->si->asic == rt_rv380) || \
(ai->si->asic == rt_r420))
// TV standard
typedef enum {
ts_off,
@@ -390,22 +405,25 @@ typedef struct {
benaphore lock; // engine lock
} engine;
uint16 vendor_id; // PCI vendor id
uint16 device_id; // PCI device id
uint8 revision; // PCI device revision
uint16 vendor_id; // PCI vendor id
uint16 device_id; // PCI device id
uint8 revision; // PCI device revision
//bool has_crtc2; // has second CRTC
radeon_type asic; // ASIC version
bool is_mobility; // mobility version
tv_chip_type tv_chip; // type of TV-Out encoder
bool new_pll; // r300 style PLL
uint8 theatre_channel; // VIP channel of Rage Theatre (if applicable)
//bool has_crtc2; // has second CRTC
radeon_type asic; // ASIC version
bool is_mobility; // mobility version
bool is_igp; // might need to know if it's an integrated chip
bool is_atombios;
tv_chip_type tv_chip; // type of TV-Out encoder
bool new_pll; // r300 style PLL
bool has_no_i2c; // I2C is broken
uint16 panel_pwr_delay;// delay for LCD backlight to stabilise
uint8 theatre_channel;// VIP channel of Rage Theatre (if applicable)
general_pll_info pll;
area_id regs_area; // area of memory mapped registers
area_id ROM_area; // area of ROM
area_id regs_area; // area of memory mapped registers
area_id ROM_area; // area of ROM
//area_id fb_area; // area of frame buffer
void *framebuffer_pci; // physical address of frame buffer (aka local memory)
// this is a hack needed by BeOS
headers/private/graphics/radeon/version.h
+1 -1
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@@ -8,4 +8,4 @@
*/
// current version
#define RADEON_DRIVER_VERSION "Version: 5.1.0.1"
#define RADEON_DRIVER_VERSION "Version: 5.1.1.1"