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Debugger: Fix some handling in DisassemblerX8664.

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Take into account the operand and offset size as needed, otherwise
we'd potentially use the wrong value for our calculations.

Gets return values somewhat working on x86-64, though in some cases
looking up a PLT slot's destination fails, for as yet undetermined
reasons.
This commit is contained in:
Rene Gollent
2013-07-27 22:58:13 -04:00
parent 4dcab59fe7
commit 8add07a8e1
1 changed files with 25 additions and 3 deletions
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src/apps/debugger/arch/x86_64/disasm/DisassemblerX8664.cpp
+25 -3
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@@ -209,19 +209,41 @@ DisassemblerX8664::GetInstructionTargetAddress(CpuState* state) const
targetAddress += x64State->IntRegisterValue(
RegisterNumberFromUdisIndex(fUdisData->operand[0].index))
* fUdisData->operand[0].scale;
off_t offset = 0;
switch (fUdisData->operand[0].offset) {
case 8:
offset = fUdisData->operand[0].lval.sbyte;
break;
case 16:
offset = fUdisData->operand[0].lval.sword;
break;
case 32:
offset = fUdisData->operand[0].lval.sdword;
break;
case 64:
offset = fUdisData->operand[0].lval.sqword;
break;
}
targetAddress += offset;
}
break;
case UD_OP_JIMM:
{
targetAddress = ud_insn_off(fUdisData)
+ fUdisData->operand[0].lval.sdword + ud_insn_len(fUdisData);
targetAddress = ud_insn_off(fUdisData) + ud_insn_len(fUdisData);
if (fUdisData->operand[0].size == 32)
targetAddress += fUdisData->operand[0].lval.sdword;
else
targetAddress += fUdisData->operand[0].lval.sqword;
}
break;
case UD_OP_IMM:
case UD_OP_CONST:
{
targetAddress = fUdisData->operand[0].lval.udword;
if (fUdisData->operand[0].size == 32)
targetAddress = fUdisData->operand[0].lval.udword;
else if (fUdisData->operand[0].size == 64)
targetAddress = fUdisData->operand[0].lval.uqword;
}
break;