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Partially revert "XHCI: Set the TRB_3_ENT_BIT on the final Link TRB, also."

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This reverts commit 63895cb5f2.

This does go against the specification, and on a very small set of
XHCI hardware, seems to break booting (#15137). So, let's revert it;
the buggy hardware it potentially helped will just have to deal with
it.
This commit is contained in:
waddlesplash
2019-07-03 20:51:05 -04:00
parent b11f8cb28c
commit 8b19fb0f55
1 changed files with 4 additions and 7 deletions
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src/add-ons/kernel/busses/usb/xhci.cpp
+4 -7
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@@ -1760,15 +1760,12 @@ XHCI::_LinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint)
descriptor->trbs[descriptor->trb_used].address = addr;
descriptor->trbs[descriptor->trb_used].status = TRB_2_IRQ(0);
descriptor->trbs[descriptor->trb_used].flags = TRB_3_TYPE(TRB_TYPE_LINK)
| TRB_3_CHAIN_BIT | TRB_3_ENT_BIT | TRB_3_CYCLE_BIT;
| TRB_3_CHAIN_BIT | TRB_3_CYCLE_BIT;
// It is specified that (XHCI 1.2 § 4.12.3 Note 2 p251) if the TRB
// following one with the ENT bit set is a Link TRB, the Link TRB
// shall be evaluated *and* the subsequent TRB shall be. Thus, the
// TRB_3_ENT_BIT here *should* be unnecessary, as the last TRB in
// this TD proper should already have the ENT bit set. But at least
// some hardware, it seems, does not necessarily obey the note, so
// we add the ENT bit on the Link TRB, too.
// shall be evaluated *and* the subsequent TRB shall be. Thus a
// TRB_3_ENT_BIT is unnecessary here; and from testing seems to
// break all transfers on a (very) small number of controllers.
#if !B_HOST_IS_LENDIAN
// Convert endianness.