Upgrade to version 4.1 of radeon driver.
Includes some common routines which may be used by other drivers. git-svn-id: file:///srv/svn/repos/haiku/trunk/current@8405 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
shadow303
+1
-1
@@ -18,7 +18,7 @@ typedef struct {
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} benaphore;
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#define INIT_BEN(prefix, x) x.sem = create_sem(0, #prefix " benaphore"); x.ben = 0;
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#define INIT_BEN(x, prefix) ( (x).ben = 0, (x).sem = create_sem(0, #prefix " benaphore"), (x).sem )
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#define ACQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem);
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#define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem);
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#define DELETE_BEN(x) delete_sem(x.sem);
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@@ -0,0 +1,21 @@
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/*
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Copyright (c) 2003, Thomas Kurschel
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Part of DDC driver
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Main DDC communication
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*/
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#ifndef _DDC_H
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#define _DDC_H
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#include "i2c.h"
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#include "edid.h"
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// read EDID and VDIF from monitor via ddc2
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// (currently, *vdif and *vdif_len is always set to null)
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status_t ddc2_read_edid1( const i2c_bus *bus, edid1_info *edid,
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void **vdif, size_t *vdif_len );
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#endif
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@@ -0,0 +1,146 @@
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/*
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Copyright (c) 2003, Thomas Kurschel
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Part of DDC driver
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EDID handling, including decoded EDID data block definitin.
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*/
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#ifndef _EDID_H
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#define _EDID_H
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#include "edid_raw.h"
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// vendor info
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typedef struct {
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char manufacturer[4];
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uint16 prod_id;
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uint32 serial;
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uint8 week;
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uint16 year;
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} edid1_vendor;
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// version info
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typedef struct {
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uint8 version;
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uint8 revision;
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} edid1_version;
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// display info
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typedef struct {
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BBITFIELD8_7 (
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input_type : 1, // 1 : digital
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input_voltage : 2, // 0=0.7V/0.3V, 1=0.714V/0.286,
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// 2=1V/0.4V, 3=0.7V/0V
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setup : 1, // true if voltage configurable
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sep_sync : 1,
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comp_sync : 1,
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sync_on_green : 1,
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sync_serr : 1
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);
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uint8 h_size;
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uint8 v_size;
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uint8 gamma; // (x+100)/100
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BBITFIELD8_7 (
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dpms_standby : 1,
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dpms_suspend : 1,
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dpms_off : 1,
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display_type : 2, // 0=mono, 1=rgb, 2=multicolour
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// since EDID version 1.1
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std_colour_space : 1,
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preferred_timing_mode : 1,
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gtf_supported : 1
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);
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uint16 red_x; // all colours are 0.10 fixed point
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uint16 red_y;
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uint16 green_x;
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uint16 green_y;
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uint16 blue_x;
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uint16 blue_y;
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uint16 white_x;
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uint16 white_y;
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} edid1_display;
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// standard timing data
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typedef struct {
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uint16 h_size;
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uint16 v_size;
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uint16 id;
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uint8 ratio;
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uint8 refresh;
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} edid1_std_timing;
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// additional whitepoint
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typedef struct {
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uint8 index;
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uint16 white_x;
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uint16 white_y;
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uint8 gamma; // (x+100)/100
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} edid1_whitepoint;
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// detailed timing description
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typedef struct {
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uint16 pixel_clock; // in 10 kHz
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uint16 h_active;
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uint16 h_blank;
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uint16 v_active;
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uint16 v_blank;
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uint16 h_sync_off;
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uint16 h_sync_width;
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uint16 v_sync_off;
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uint16 v_sync_width;
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uint16 h_size;
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uint16 v_size;
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uint16 h_border;
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uint16 v_border;
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BBITFIELD8_4 (
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interlaced : 1,
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stereo : 2, // upper bit set - left on sync
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// lower bit set - right on sync
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sync : 2,
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misc : 2
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);
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} edid1_detailed_timing;
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// detailed monitor description
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typedef struct {
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uint8 monitor_desc_type;
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union {
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char serial_number[EDID1_EXTRA_STRING_LEN];
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char ascii_data[EDID1_EXTRA_STRING_LEN];
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edid1_monitor_range monitor_range;
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char monitor_name[EDID1_EXTRA_STRING_LEN];
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edid1_whitepoint whitepoint[EDID1_NUM_EXTRA_WHITEPOINTS];
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edid1_std_timing std_timing[EDID1_NUM_EXTRA_STD_TIMING];
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edid1_detailed_timing detailed_timing;
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} data;
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} edid1_detailed_monitor;
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// EDID data block
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typedef struct{
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edid1_vendor vendor;
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edid1_version version;
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edid1_display display;
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edid1_established_timing established_timing;
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edid1_std_timing std_timing[EDID1_NUM_STD_TIMING];
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// since EDID version 1.2
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edid1_detailed_monitor detailed_monitor[EDID1_NUM_DETAILED_MONITOR_DESC];
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uint8 num_sections;
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} edid1_info;
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// decode raw EDID info into usuable EDID info
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void edid_decode( edid1_info *edid, const edid1_raw *raw );
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// dump EDID info to syslog
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void edid_dump( edid1_info *edid );
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#endif
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@@ -0,0 +1,278 @@
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/*
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Copyright (c) 2003, Thomas Kurschel
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Part of DDC driver
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Raw EDID data block.
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Raw data are packed in a really weird way. Never even
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think about using it directly, instead translate it via decode_edidpixel_clock
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first. I did my best to make the code endian-independant, but
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I cannot guarantee that I haven't missed something.
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*/
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#ifndef _EDID_RAW_H
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#define _EDID_RAW_H
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#include "bendian_bitfield.h"
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#define EDID1_NUM_DETAILED_MONITOR_DESC 4
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#define EDID1_NUM_STD_TIMING 8
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#define EDID1_NUM_EXTRA_STD_TIMING 6
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#define EDID1_EXTRA_STRING_LEN 13
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#define EDID1_NUM_EXTRA_WHITEPOINTS 2
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// header
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typedef struct _PACKED {
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int8 pad[8]; // contains 0, -1, -1, -1, -1, -1, -1, 0
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} edid1_header_raw;
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// vendor info
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typedef struct _PACKED {
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BBITFIELD8_3 ( // manufacturer
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pad : 1,
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c1 : 5, // add '@' to get ascii
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c2_high : 2
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);
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BBITFIELD8_2 (
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c2_low : 3,
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c3 : 5
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);
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uint16 prod_id;
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uint32 serial;
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uint8 week;
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uint8 year; // x+1990
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} edid1_vendor_raw;
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// version info
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typedef struct _PACKED {
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uint8 version;
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uint8 revision;
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} edid1_version_raw;
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// display info
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typedef struct _PACKED {
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BBITFIELD8_7 (
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input_type : 1, // 1 : digital
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input_voltage : 2, // 0=0.7V/0.3V, 1=0.714V/0.286,
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// 2=1V/0.4V, 3=0.7V/0V
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setup : 1, // true if voltage configurable
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sep_sync : 1,
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comp_sync : 1,
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sync_on_green : 1,
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sync_serr : 1
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);
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uint8 h_size;
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uint8 v_size;
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uint8 gamma; // (x+100)/100
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BBITFIELD8_7 (
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dpms_standby : 1,
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dpms_suspend : 1,
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dpms_off : 1,
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display_type : 2, // 0=mono, 1=rgb, 2=multicolour
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// since EDID version 1.1
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std_colour_space : 1,
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preferred_timing_mode : 1,
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gtf_supported : 1
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);
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BBITFIELD8_4 ( // low bits of red_x etc.
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red_x_low : 2,
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red_y_low : 2,
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green_x_low : 2,
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green_y_low : 2
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);
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BBITFIELD8_4 (
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blue_x_low : 2,
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blue_y_low : 2,
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white_x_low : 2,
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white_y_low : 2
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);
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uint8 red_x; // all colours are 0.10 fixed point
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uint8 red_y;
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uint8 green_x;
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uint8 green_y;
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uint8 blue_x;
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uint8 blue_y;
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uint8 white_x;
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uint8 white_y;
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} edid1_display_raw;
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// raw standard timing data
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typedef union _PACKED {
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struct _PACKED {
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uint8 h_size; // (x+31)*8
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BBITFIELD8_2 (
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ratio : 2, // 0=1:1, 1=3/4, 2=4/5, 3=9/16
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refresh : 6 // (x+60)
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);
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} timing;
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uint16 id;
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} edid1_std_timing_raw;
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// list of supported fixed timings
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typedef struct _PACKED {
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BBITFIELD8_8 (
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res_720x400x70 : 1,
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res_720x400x88 : 1,
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res_640x480x60 : 1,
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res_640x480x67 : 1,
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res_640x480x72 : 1,
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res_640x480x75 : 1,
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res_800x600x56 : 1,
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res_800x600x60 : 1
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);
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BBITFIELD8_8 (
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res_800x600x72 : 1,
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res_800x600x75 : 1,
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res_832x624x75 : 1,
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res_1024x768x87i : 1,
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res_1024x768x60 : 1,
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res_1024x768x70 : 1,
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res_1024x768x75 : 1,
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res_1280x1024x75 : 1
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);
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BBITFIELD8_2 (
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res_1152x870x75 : 1,
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pad : 7
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);
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} edid1_established_timing;
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// types of detailed monitor description
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enum {
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edid1_serial_number = 0xff,
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edid1_ascii_data = 0xfe,
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edid1_monitor_ranges = 0xfd,
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edid1_monitor_name = 0xfc,
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edid1_add_colour_pointer = 0xfb,
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edid1_add_std_timing = 0xfa,
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edid1_is_detailed_timing = 1
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};
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// monitor frequency range
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typedef struct _PACKED {
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uint8 min_v;
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uint8 max_v;
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uint8 min_h;
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uint8 max_h;
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uint8 max_clock; // in 10 MHz (!)
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} edid1_monitor_range;
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// additional whitepoint
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typedef struct _PACKED {
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uint8 index1;
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BBITFIELD8_3 (
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pad1 : 4,
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white_x1_low : 2,
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white_y1_low : 2
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);
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uint8 white_x1;
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uint8 white_y1;
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uint8 gamma1; // (x+100)/100
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uint8 index2;
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BBITFIELD8_3 (
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pad2 : 4,
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white_x2_low : 2,
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white_y2_low : 2
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);
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uint8 white_x2;
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uint8 white_y2;
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uint8 gamma2; // (x+100)/100
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} edid1_whitepoint_raw;
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// detailed timing description
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typedef struct _PACKED {
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uint16 pixel_clock; // in 10 kHz (!)
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uint8 h_active;
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uint8 h_blank;
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BBITFIELD8_2 (
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h_active_high : 4,
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h_blank_high : 4
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);
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uint8 v_active;
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uint8 v_blank;
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BBITFIELD8_2 (
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v_active_high : 4,
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v_blank_high : 4
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);
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uint8 h_sync_off;
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uint8 h_sync_width;
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BBITFIELD8_2 (
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v_sync_off : 4,
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v_sync_width : 4
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);
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BBITFIELD8_4 (
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h_sync_off_high : 2,
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h_sync_width_high : 2,
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v_sync_off_high : 2,
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v_sync_width_high : 2
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);
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uint8 h_size;
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uint8 v_size;
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BBITFIELD8_2 (
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h_size_high : 4,
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v_size_high : 4
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);
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uint8 h_border;
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uint8 v_border;
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BBITFIELD8_4 (
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interlaced : 1,
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stereo : 2, // upper bit set - left on sync
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// lower bit set - right on sync
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sync : 2,
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misc : 2
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);
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} edid1_detailed_timing_raw;
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// detailed monitor description
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typedef union _PACKED {
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edid1_detailed_timing_raw detailed_timing;
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struct _PACKED {
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uint8 zero_0[3];
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uint8 monitor_desc_type;
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uint8 zero_4;
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union _PACKED {
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uint8 serial_number[EDID1_EXTRA_STRING_LEN];
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uint8 ascii_data[EDID1_EXTRA_STRING_LEN];
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uint8 monitor_name[EDID1_EXTRA_STRING_LEN];
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edid1_monitor_range monitor_range;
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edid1_whitepoint_raw whitepoint;
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edid1_std_timing_raw std_timing[EDID1_NUM_EXTRA_STD_TIMING];
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} data;
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} extra;
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} edid1_detailed_monitor_raw;
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// raw EDID data
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// everything is packed data, mixture of little endian and big endian
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// and a bit brain dead overall - nothing your dad would be proud of
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typedef struct _PACKED {
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edid1_header_raw header; // 8 bytes
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edid1_vendor_raw vendor; // 10 bytes
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edid1_version_raw version; // 2 bytes
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edid1_display_raw display; // 15 bytes
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edid1_established_timing established_timing; // 3 bytes
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edid1_std_timing_raw std_timing[EDID1_NUM_STD_TIMING];
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// 8 a 2 bytes -> 16 bytes
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// since EDID version 1.2
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edid1_detailed_monitor_raw detailed_monitor[EDID1_NUM_DETAILED_MONITOR_DESC];
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// 4 a 18 bytes -> 72 bytes
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uint8 num_sections; // 1 byte
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uint8 check_sum; // 1 byte
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} edid1_raw; // total: 128 bytes
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#endif
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@@ -0,0 +1,69 @@
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/*
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Copyright (c) 2003, Thomas Kurschel
|
||||
|
||||
|
||||
Part of DDC driver
|
||||
|
||||
I2C protocoll
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||||
*/
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#ifndef _I2C_H
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#define _I2C_H
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#include <OS.h>
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// timing for i2c bus
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||||
typedef struct i2c_timing {
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// general timing as defined by standard
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||||
// (in microseconds for 100kHz/400kHz mode)
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int buf; // bus free between start and stop (4.7/1.3)
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int hd_sta; // hold time start condition (4.0/0.6)
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int low; // low period of clock (4.7/1.3)
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int high; // high period of clock (4.0/0.6)
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int su_sta; // setup time of repeated start condition (4.7/0.6)
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int hd_dat; // hold time data (5.0/- for CBUS, 0/0 for I2C)
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int su_dat; // setup time data (0.250/0.100)
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int r; // maximum raise time of clock and data signal (1.0/0.3)
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int f; // maximum fall time of clock and data signal (0.3/0.3)
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int su_sto; // setup time for stop condition (4.0/0.6)
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||||
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// clock stretching limits, not part of i2c standard
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int start_timeout; // max. delay of start condition
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int byte_timeout; // max. delay of first bit of byte
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||||
int bit_timeout; // max. delay of one bit within a byte transmission
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||||
int ack_start_timeout; // max. delay of acknowledge start
|
||||
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||||
// other timeouts, not part of i2c standard
|
||||
int ack_timeout; // timeout of waiting for acknowledge
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||||
} i2c_timing;
|
||||
|
||||
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||||
// set signals on bus
|
||||
typedef status_t (*i2c_set_signals)( void *cookie, int scl, int sda );
|
||||
// read signals from bus
|
||||
typedef status_t (*i2c_get_signals)( void *cookie, int *scl, int *sda );
|
||||
|
||||
|
||||
// i2c bus definition
|
||||
typedef struct i2c_bus {
|
||||
void *cookie; // user-defined cookie
|
||||
i2c_set_signals set_signals; // callback to set signals
|
||||
i2c_get_signals get_signals; // callback to detect signals
|
||||
} i2c_bus;
|
||||
|
||||
|
||||
// send and receive data via i2c bus
|
||||
status_t i2c_send_receive( const i2c_bus *bus, const i2c_timing *timing,
|
||||
int slave_address,
|
||||
const uint8 *write_buffer, size_t write_len,
|
||||
uint8 *read_buffer, size_t read_len );
|
||||
|
||||
|
||||
// fill <timing> with standard 100kHz bus timing
|
||||
void i2c_get100k_timing( i2c_timing *timing );
|
||||
|
||||
// fill <timing> with standard 400kHz bus timing
|
||||
// (as timing resolution is 1 microsecond, we cannot reach full speed!)
|
||||
void i2c_get400k_timing( i2c_timing *timing );
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,95 @@
|
||||
#ifndef LENDIAN_BITFIELD_H
|
||||
#define LENDIAN_BITFIELD_H
|
||||
|
||||
#include <ByteOrder.h>
|
||||
|
||||
#if B_HOST_IS_BENDIAN
|
||||
|
||||
#define LBITFIELD8_2(b1,b2) uint8 b2,b1
|
||||
#define LBITFIELD8_3(b1,b2,b3) uint8 b3,b2,b1
|
||||
#define LBITFIELD8_4(b1,b2,b3,b4) uint8 b4,b3,b2,b1
|
||||
#define LBITFIELD8_5(b1,b2,b3,b4,b5) uint8 b5,b4,b3,b2,b1
|
||||
#define LBITFIELD8_6(b1,b2,b3,b4,b5,b6) uint8 b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD8_7(b1,b2,b3,b4,b5,b6,b7) uint8 b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD8_8(b1,b2,b3,b4,b5,b6,b7,b8) uint8 b8,b7,b6,b5,b4,b3,b2,b1
|
||||
|
||||
|
||||
#define LBITFIELD2(b1,b2) uint16 b2,b1
|
||||
#define LBITFIELD3(b1,b2,b3) uint16 b3,b2,b1
|
||||
#define LBITFIELD4(b1,b2,b3,b4) uint16 b4,b3,b2,b1
|
||||
#define LBITFIELD5(b1,b2,b3,b4,b5) uint16 b5,b4,b3,b2,b1
|
||||
#define LBITFIELD6(b1,b2,b3,b4,b5,b6) uint16 b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD7(b1,b2,b3,b4,b5,b6,b7) uint16 b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD8(b1,b2,b3,b4,b5,b6,b7,b8) uint16 b8,b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD9(b1,b2,b3,b4,b5,b6,b7,b8,b9) uint16 b9,b8,b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD10(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10) uint16 b10,b9,b8,b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD11(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11) uint16 b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD12(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12) uint16 b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD13(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13) uint16 b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD14(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14) uint16 b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD15(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15) uint16 b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD16(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15,b16) uint16 b16,b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1
|
||||
|
||||
#define LBITFIELD32_2(b1,b2) uint32 b2,b1
|
||||
#define LBITFIELD32_3(b1,b2,b3) uint32 b3,b2,b1
|
||||
#define LBITFIELD32_4(b1,b2,b3,b4) uint32 b4,b3,b2,b1
|
||||
#define LBITFIELD32_5(b1,b2,b3,b4,b5) uint32 b5,b4,b3,b2,b1
|
||||
#define LBITFIELD32_6(b1,b2,b3,b4,b5,b6) uint32 b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD32_7(b1,b2,b3,b4,b5,b6,b7) uint32 b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD32_8(b1,b2,b3,b4,b5,b6,b7,b8) uint32 b8,b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD32_9(b1,b2,b3,b4,b5,b6,b7,b8,b9) uint32 b9,b8,b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD32_10(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10) uint32 b10,b9,b8,b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD32_11(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11) uint32 b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD32_12(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12) uint32 b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD32_13(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13) uint32 b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD32_14(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14) uint32 b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD32_15(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15) uint32 b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1
|
||||
#define LBITFIELD32_16(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15,b16) uint32 b16,b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1
|
||||
|
||||
#elif B_HOST_IS_LENDIAN
|
||||
|
||||
#define LBITFIELD8_2(b1,b2) uint8 b1,b2
|
||||
#define LBITFIELD8_3(b1,b2,b3) uint8 b1,b2,b3
|
||||
#define LBITFIELD8_4(b1,b2,b3,b4) uint8 b1,b2,b3,b4
|
||||
#define LBITFIELD8_5(b1,b2,b3,b4,b5) uint8 b1,b2,b3,b4,b5
|
||||
#define LBITFIELD8_6(b1,b2,b3,b4,b5,b6) uint8 b1,b2,b3,b4,b5,b6
|
||||
#define LBITFIELD8_7(b1,b2,b3,b4,b5,b6,b7) uint8 b1,b2,b3,b4,b5,b6,b7
|
||||
#define LBITFIELD8_8(b1,b2,b3,b4,b5,b6,b7,b8) uint8 b1,b2,b3,b4,b5,b6,b7,b8
|
||||
|
||||
#define LBITFIELD2(b1,b2) uint16 b1,b2
|
||||
#define LBITFIELD3(b1,b2,b3) uint16 b1,b2,b3
|
||||
#define LBITFIELD4(b1,b2,b3,b4) uint16 b1,b2,b3,b4
|
||||
#define LBITFIELD5(b1,b2,b3,b4,b5) uint16 b1,b2,b3,b4,b5
|
||||
#define LBITFIELD6(b1,b2,b3,b4,b5,b6) uint16 b1,b2,b3,b4,b5,b6
|
||||
#define LBITFIELD7(b1,b2,b3,b4,b5,b6,b7) uint16 b1,b2,b3,b4,b5,b6,b7
|
||||
#define LBITFIELD8(b1,b2,b3,b4,b5,b6,b7,b8) uint16 b1,b2,b3,b4,b5,b6,b7,b8
|
||||
#define LBITFIELD9(b1,b2,b3,b4,b5,b6,b7,b8,b9) uint16 b1,b2,b3,b4,b5,b6,b7,b8,b9
|
||||
#define LBITFIELD10(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10) uint16 b1,b2,b3,b4,b5,b6,b7,b8,b9,b10
|
||||
#define LBITFIELD11(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11) uint16 b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11
|
||||
#define LBITFIELD12(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12) uint16 b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12
|
||||
#define LBITFIELD13(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13) uint16 b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13
|
||||
#define LBITFIELD14(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14) uint16 b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14
|
||||
#define LBITFIELD15(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15) uint16 b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15
|
||||
#define LBITFIELD16(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15,b16) uint16 b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15,b16
|
||||
|
||||
#define LBITFIELD32_2(b1,b2) uint32 b1,b2
|
||||
#define LBITFIELD32_3(b1,b2,b3) uint32 b1,b2,b3
|
||||
#define LBITFIELD32_4(b1,b2,b3,b4) uint32 b1,b2,b3,b4
|
||||
#define LBITFIELD32_5(b1,b2,b3,b4,b5) uint32 b1,b2,b3,b4,b5
|
||||
#define LBITFIELD32_6(b1,b2,b3,b4,b5,b6) uint32 b1,b2,b3,b4,b5,b6
|
||||
#define LBITFIELD32_7(b1,b2,b3,b4,b5,b6,b7) uint32 b1,b2,b3,b4,b5,b6,b7
|
||||
#define LBITFIELD32_8(b1,b2,b3,b4,b5,b6,b7,b8) uint32 b1,b2,b3,b4,b5,b6,b7,b8
|
||||
#define LBITFIELD32_9(b1,b2,b3,b4,b5,b6,b7,b8,b9) uint32 b1,b2,b3,b4,b5,b6,b7,b8,b9
|
||||
#define LBITFIELD32_10(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10) uint32 b1,b2,b3,b4,b5,b6,b7,b8,b9,b10
|
||||
#define LBITFIELD32_11(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11) uint32 b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11
|
||||
#define LBITFIELD32_12(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12) uint32 b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12
|
||||
#define LBITFIELD32_13(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13) uint32 b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13
|
||||
#define LBITFIELD32_14(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14) uint32 b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14
|
||||
#define LBITFIELD32_15(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15) uint32 b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15
|
||||
#define LBITFIELD32_16(b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15,b16) uint32 b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15,b16
|
||||
|
||||
#else
|
||||
#error "Unknown host endianness"
|
||||
#endif
|
||||
|
||||
#endif /* LENDIAN_BITFIELD_H */
|
||||
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
Copyright (c) 2002, Thomas Kurschel
|
||||
|
||||
|
||||
Part of Radeon driver
|
||||
|
||||
Fast logger
|
||||
|
||||
As syslog is very slow and tends to loose
|
||||
data if its buffer overflows (which occurs much
|
||||
too often), this module provides a fast (and memory-
|
||||
wasting) logging mechanism. You need a seperate
|
||||
application to retrieve the log.
|
||||
|
||||
Everything is thread-safe.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __LOG_COLL_H__
|
||||
#define __LOG_COLL_H__
|
||||
|
||||
#include <SupportDefs.h>
|
||||
|
||||
// by undefining this flag, all logging functions
|
||||
// are resolved to empty space, so don't add
|
||||
// extra tests in your code
|
||||
#undef ENABLE_LOGGING
|
||||
//#define ENABLE_LOGGING
|
||||
|
||||
|
||||
// add log entry with 0..3 (uint32) data
|
||||
#define LOG( li, what ) log( li, what, 0 )
|
||||
#define LOG1( li, what, arg1 ) log( li, what, 1, arg1 );
|
||||
#define LOG2( li, what, arg1, arg2 ) log( li, what, 2, arg1, arg2 );
|
||||
#define LOG3( li, what, arg1, arg2, arg3 ) log( li, what, 3, arg1, arg2, arg3 );
|
||||
|
||||
|
||||
// one log entry
|
||||
typedef struct log_entry_t {
|
||||
uint64 tsc;
|
||||
uint16 what;
|
||||
uint8 num_args;
|
||||
uint32 args[1];
|
||||
} log_entry;
|
||||
|
||||
struct log_info_t;
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef ENABLE_LOGGING
|
||||
void log( struct log_info_t *li, uint16 what, const uint8 num_args, ... );
|
||||
#else
|
||||
#define log( a, b, c... )
|
||||
#endif
|
||||
|
||||
|
||||
// define LOG_INCLUDE_STARTUP in your device driver
|
||||
#ifdef LOG_INCLUDE_STARTUP
|
||||
|
||||
uint32 log_getsize( struct log_info_t *li );
|
||||
void log_getcopy( struct log_info_t *li, void *dest, uint32 max_size );
|
||||
|
||||
#ifdef ENABLE_LOGGING
|
||||
|
||||
struct log_info_t *log_init( uint32 size );
|
||||
void log_exit( struct log_info_t *li );
|
||||
|
||||
#else
|
||||
|
||||
#define log_init( a ) NULL
|
||||
#define log_exit( a )
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
Copyright (c) 2002, Thomas Kurschel
|
||||
|
||||
|
||||
Part of Radeon kernel driver
|
||||
|
||||
Memory manager used for graphics mem
|
||||
*/
|
||||
|
||||
#ifndef _MEMMGR_H
|
||||
#define _MEMMGR_H
|
||||
|
||||
#include <OS.h>
|
||||
|
||||
|
||||
// allocated memory block
|
||||
typedef struct mem_block {
|
||||
struct mem_block *prev, *next;
|
||||
uint32 base;
|
||||
uint32 size;
|
||||
void *tag;
|
||||
bool alloced;
|
||||
} mem_block;
|
||||
|
||||
|
||||
// memory heap
|
||||
typedef struct mem_info {
|
||||
mem_block *first;
|
||||
uint32 block_size;
|
||||
sem_id lock;
|
||||
mem_block *heap;
|
||||
mem_block *unused;
|
||||
uint32 heap_entries;
|
||||
} mem_info;
|
||||
|
||||
|
||||
mem_info *mem_init( uint32 start, uint32 len, uint32 block_size, uint32 heap_entries );
|
||||
void mem_destroy( mem_info *mem );
|
||||
status_t mem_alloc( mem_info *mem, uint32 size, void *tag, uint32 *block, uint32 *offset );
|
||||
status_t mem_free( mem_info *mem, uint32 block_id, void *tag );
|
||||
void mem_freetag( mem_info *mem, void *tag );
|
||||
|
||||
#endif
|
||||
@@ -1,42 +0,0 @@
|
||||
/*
|
||||
Copyright (c) 2002, Thomas Kurschel
|
||||
|
||||
|
||||
Part of Radeon accelerant
|
||||
|
||||
additional accelerant interface definitions
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _ACCELERANT_EXT_H
|
||||
#define _ACCELERANT_EXT_H
|
||||
|
||||
|
||||
// additional timing flags for GetMode/SetMode
|
||||
enum {
|
||||
RADEON_MODE_STANDARD = 0 << 16,
|
||||
RADEON_MODE_MIRROR = 1 << 16,
|
||||
RADEON_MODE_CLONE = 2 << 16,
|
||||
RADEON_MODE_COMBINE = 3 << 16,
|
||||
|
||||
RADEON_MODE_MASK = 7 << 16,
|
||||
|
||||
RADEON_MODE_DISPLAYS_SWAPPED = 1 << 20,
|
||||
|
||||
// used internally
|
||||
RADEON_MODE_POSITION_HORIZONTAL = 0 << 21,
|
||||
RADEON_MODE_POSITION_VERTICAL = 1 << 21,
|
||||
RADEON_MODE_POSITION_MASK = 1 << 21,
|
||||
|
||||
RADEON_MODE_MULTIMON_REQUEST = 1 << 25,
|
||||
RADEON_MODE_MULTIMON_REPLY = 1 << 26
|
||||
};
|
||||
|
||||
// operation codes tunneled via ProposeDisplayMode
|
||||
enum {
|
||||
ms_swap,
|
||||
ms_overlay_port
|
||||
} multi_mon_settings;
|
||||
|
||||
|
||||
#endif
|
||||
@@ -19,8 +19,9 @@
|
||||
#define RADEON_BIOS_6_SCRATCH 0x0028
|
||||
#define RADEON_BIOS_7_SCRATCH 0x002c
|
||||
|
||||
#define RADEON_TEST_DEBUG_CNTL 0x0120
|
||||
#define RADEON_TEST_DEBUG_MUX 0x0124
|
||||
#define RADEON_TEST_DEBUG_OUT 0x012c
|
||||
#define RADEON_TEST_DEBUG_CNTL 0x0120
|
||||
# define RADEON_TEST_DEBUG_CNTL_OUT_EN (1 << 0)
|
||||
#define RADEON_TEST_DEBUG_MUX 0x0124
|
||||
#define RADEON_TEST_DEBUG_OUT 0x012c
|
||||
|
||||
#endif
|
||||
|
||||
@@ -12,6 +12,8 @@
|
||||
|
||||
// mmio registers
|
||||
#define RADEON_CONFIG_CNTL 0x00e0
|
||||
#define RADEON_CFG_ATI_REV_ID_SHIFT 16
|
||||
#define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)
|
||||
#define RADEON_CONFIG_MEMSIZE 0x00f8
|
||||
# define RADEON_CONFIG_MEMSIZE_MASK 0x1ff00000
|
||||
|
||||
|
||||
@@ -43,6 +43,7 @@
|
||||
# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
|
||||
# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
|
||||
# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
|
||||
#define RADEON_CP_STAT 0x07c0
|
||||
#define RADEON_CP_CSQ_STAT 0x07f8
|
||||
# define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0)
|
||||
# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8)
|
||||
@@ -96,8 +97,6 @@
|
||||
#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00
|
||||
|
||||
|
||||
#define RADEON_SCRATCH_REG_OFFSET 32
|
||||
|
||||
#define RADEON_ISYNC_CNTL 0x1724
|
||||
# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
|
||||
# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
|
||||
@@ -108,7 +107,7 @@
|
||||
|
||||
|
||||
#define CP_PACKET0( reg, n ) \
|
||||
(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
|
||||
(RADEON_CP_PACKET0 | (((n) - 1) << 16) | ((reg) >> 2))
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -42,6 +42,8 @@
|
||||
# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)
|
||||
# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)
|
||||
# define RADEON_CRTC2_CRT2_ON (1 << 7)
|
||||
# define RADEON_CRTC2_PIX_WIDTH_SHIFT 8
|
||||
# define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8)
|
||||
# define RADEON_CRTC2_ICON_EN (1 << 15)
|
||||
# define RADEON_CRTC2_CUR_EN (1 << 16)
|
||||
# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20)
|
||||
@@ -51,6 +53,13 @@
|
||||
# define RADEON_CRTC2_HSYNC_DIS (1 << 28)
|
||||
# define RADEON_CRTC2_VSYNC_DIS (1 << 29)
|
||||
#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218
|
||||
#define RADEON_CRTC_MORE_CNTL 0x27C
|
||||
# define RADEON_CRTC_HORZ_BLANK_MODE_SEL (1 << 0)
|
||||
# define RADEON_CRTC_VERT_BLANK_MODE_SEL (1 << 1)
|
||||
# define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1 << 2)
|
||||
# define RADEON_CRTC_AUTO_VERT_CENTER_EN (1 << 3)
|
||||
# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1 << 4)
|
||||
# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1 << 5)
|
||||
#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204
|
||||
# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)
|
||||
# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)
|
||||
@@ -128,4 +137,27 @@
|
||||
#define RADEON_CUR2_OFFSET 0x0360
|
||||
# define RADEON_CUR2_LOCK (1 << 31)
|
||||
|
||||
#define RADEON_GRPH_BUFFER_CNTL 0x02f0
|
||||
# define RADEON_GRPH_START_REQ_MASK (0x7f)
|
||||
# define RADEON_GRPH_START_REQ_SHIFT 0
|
||||
# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)
|
||||
# define RADEON_GRPH_STOP_REQ_SHIFT 8
|
||||
# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)
|
||||
# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16
|
||||
# define RADEON_GRPH_CRITICAL_CNTL (1<<28)
|
||||
# define RADEON_GRPH_BUFFER_SIZE (1<<29)
|
||||
# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)
|
||||
# define RADEON_GRPH_STOP_CNTL (1<<31)
|
||||
#define RADEON_GRPH2_BUFFER_CNTL 0x03f0
|
||||
# define RADEON_GRPH2_START_REQ_MASK (0x7f)
|
||||
# define RADEON_GRPH2_START_REQ_SHIFT 0
|
||||
# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)
|
||||
# define RADEON_GRPH2_STOP_REQ_SHIFT 8
|
||||
# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)
|
||||
# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16
|
||||
# define RADEON_GRPH2_CRITICAL_CNTL (1<<28)
|
||||
# define RADEON_GRPH2_BUFFER_SIZE (1<<29)
|
||||
# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)
|
||||
# define RADEON_GRPH2_STOP_CNTL (1<<31)
|
||||
|
||||
#endif
|
||||
|
||||
@@ -11,23 +11,46 @@
|
||||
#define _DAC_REGS_H
|
||||
|
||||
#define RADEON_DAC_CNTL 0x0058
|
||||
# define RADEON_DAC_RANGE_CNTL (3 << 0)
|
||||
# define RADEON_DAC_RANGE_CNTL_MASK (3 << 0)
|
||||
# define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0)
|
||||
# define RADEON_DAC_BLANKING (1 << 2)
|
||||
# define RADEON_DAC_CMP_EN (1 << 3)
|
||||
# define RADEON_DAC_CMP_OUTPUT (1 << 7)
|
||||
# define RADEON_DAC_8BIT_EN (1 << 8)
|
||||
# define RADEON_DAC_VGA_ADR_EN (1 << 13)
|
||||
# define RADEON_DAC_PDWN (1 << 15)
|
||||
# define RADEON_DAC_MASK_ALL (0xff << 24)
|
||||
#define RADEON_DAC_CNTL2 0x007c
|
||||
# define RADEON_DAC_CLK_SEL (1 << 0)
|
||||
# define RADEON_DAC_CLK_SEL_MASK (1 << 0)
|
||||
# define RADEON_DAC_CLK_SEL_CRTC (0 << 0)
|
||||
# define RADEON_DAC_CLK_SEL_CRTC2 (1 << 0)
|
||||
# define RADEON_DAC2_CLK_SEL (1 << 1)
|
||||
# define RADEON_DAC2_CLK_SEL_MASK (1 << 1)
|
||||
# define RADEON_DAC2_CLK_SEL_TV (0 << 1)
|
||||
# define RADEON_DAC2_CLK_SEL_CRT (1 << 1)
|
||||
# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)
|
||||
# define RADEON_DAC2_CMP_EN (1 << 7)
|
||||
# define RADEON_DAC2_CMP_OUT_R (1 << 8)
|
||||
# define RADEON_DAC2_CMP_OUT_G (1 << 9)
|
||||
# define RADEON_DAC2_CMP_OUT_B (1 << 10)
|
||||
# define RADEON_DAC2_CMP_OUTPUT (1 << 11)
|
||||
#define RADEON_PALETTE_INDEX 0x00b0
|
||||
#define RADEON_PALETTE_DATA 0x00b4
|
||||
#define RADEON_PALETTE_30_DATA 0x00b8
|
||||
|
||||
#define RADEON_DAC_EXT_CNTL 0x0280
|
||||
# define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)
|
||||
# define RADEON_DAC2_FORCE_DATA_EN (1 << 1)
|
||||
# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)
|
||||
# define RADEON_DAC_FORCE_DATA_EN (1 << 5)
|
||||
# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)
|
||||
# define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6)
|
||||
# define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6)
|
||||
# define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6)
|
||||
# define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6)
|
||||
# define RADEON_DAC_FORCE_DATA_SHIFT 8
|
||||
# define RADEON_DAC_FORCE_DATA_MASK (0x3ff << 8)
|
||||
#define RADEON_DAC_CRC_SIG 0x02cc
|
||||
|
||||
#define RADEON_DAC_DATA 0x03c9 /* VGA */
|
||||
#define RADEON_DAC_MASK 0x03c6 /* VGA */
|
||||
#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */
|
||||
@@ -35,7 +58,14 @@
|
||||
|
||||
#define RADEON_DISP_OUTPUT_CNTL 0x0d64
|
||||
# define RADEON_DISP_DAC_SOURCE_MASK 0x03
|
||||
# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
|
||||
# define RADEON_DISP_DAC_SOURCE_CRTC1 0x00
|
||||
# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
|
||||
# define RADEON_DISP_DAC_SOURCE_RMX 0x02
|
||||
# define RADEON_DISP_TVDAC_SOURCE_MASK 0x0c
|
||||
# define RADEON_DISP_TVDAC_SOURCE_CRTC2 0x04
|
||||
|
||||
#define RADEON_DISP_HW_DEBUG 0x0d14
|
||||
# define RADEON_CRT2_DISP1_SEL (1 << 5)
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
Copyright (c) 2002, Thomas Kurschel
|
||||
|
||||
|
||||
Part of Radeon driver
|
||||
|
||||
DMA registers
|
||||
*/
|
||||
|
||||
#ifndef _DMA_REGS_H
|
||||
#define _DMA_REGS_H
|
||||
|
||||
typedef struct DMA_descriptor {
|
||||
uint32 src_address;
|
||||
uint32 dest_address;
|
||||
uint32 command;
|
||||
uint32 res;
|
||||
} DMA_descriptor;
|
||||
|
||||
#define RADEON_DMA_COMMAND_EOL (1 << 31)
|
||||
#define RADEON_DMA_COMMAND_INTDIS (1 << 30)
|
||||
#define RADEON_DMA_COMMAND_DAIC (1 << 29)
|
||||
#define RADEON_DMA_COMMAND_SAIC (1 << 28)
|
||||
#define RADEON_DMA_COMMAND_DAS (1 << 27)
|
||||
#define RADEON_DMA_COMMAND_SAS (1 << 26)
|
||||
#define RADEON_DMA_COMMAND_DST_SWAP_SHIFT 24
|
||||
#define RADEON_DMA_COMMAND_SRC_SWAP_SHIFT 24
|
||||
#define RADEON_DMA_COMMAND_BYTE_COUNT_SHIFT 0
|
||||
|
||||
#define RADEON_DMA_DESC_MAX_SIZE 0x1fffff
|
||||
|
||||
#define RADEON_DMA_GUI_TABLE_ADDR 0x0780
|
||||
#define RADEON_DMA_GUI_STATUS 0x0790
|
||||
#define RADEON_DMA_STATUS_ACTIVE (1 << 21)
|
||||
|
||||
#define RADEON_DMA_VID_TABLE_ADDR 0x07a0
|
||||
#define RADEON_DMA_VID_STATUS 0x07b0
|
||||
|
||||
#endif
|
||||
@@ -30,11 +30,13 @@
|
||||
# define RADEON_FP_USE_SHADOW_EN (1 << 24)
|
||||
# define RADEON_FP_CRT_SYNC_ALT (1 << 26)
|
||||
#define RADEON_FP2_GEN_CNTL 0x0288
|
||||
# define RADEON_FP2_FPON (1 << 0)
|
||||
# define RADEON_FP2_TMDS_EN (1 << 2)
|
||||
# define RADEON_FP2_EN_TMDS (1 << 7)
|
||||
# define RADEON_FP2_DETECT_SENSE (1 << 8)
|
||||
# define RADEON_FP2_SEL_CRTC2 (1 << 13)
|
||||
# define RADEON_FP2_BLANK_EN (1 << 1)
|
||||
# define RADEON_FP2_FPON (1 << 2)
|
||||
# define RADEON_FP2_PANEL_FORMAT (1 << 3)
|
||||
# define RADEON_FP2_SOURCE_SEL_MASK (3 << 10)
|
||||
# define RADEON_FP2_SOURCE_SEL_CRTC2 (1 << 10)
|
||||
# define RADEON_FP2_SRC_SEL_MASK (3 << 13)
|
||||
# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)
|
||||
# define RADEON_FP2_FP_POL (1 << 16)
|
||||
# define RADEON_FP2_LP_POL (1 << 17)
|
||||
# define RADEON_FP2_SCK_POL (1 << 18)
|
||||
@@ -42,11 +44,13 @@
|
||||
# define RADEON_FP2_PAD_FLOP_EN (1 << 22)
|
||||
# define RADEON_FP2_CRC_EN (1 << 23)
|
||||
# define RADEON_FP2_CRC_READ_EN (1 << 24)
|
||||
# define RADEON_FP2_DV0_EN (1 << 25)
|
||||
# define RADEON_FP2_DV0_RATE_SEL_SDR (1 << 26)
|
||||
#define RADEON_FP_HORZ_STRETCH 0x028c
|
||||
# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff
|
||||
# define RADEON_HORZ_STRETCH_RATIO_MAX 4096
|
||||
# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16)
|
||||
# define RADEON_HORZ_PANEL_SHIFT 16
|
||||
# define RADEON_HORZ_PANEL_SIZE_SHIFT 16
|
||||
# define RADEON_HORZ_STRETCH_PIXREP (0 << 25)
|
||||
# define RADEON_HORZ_STRETCH_BLEND (1 << 26)
|
||||
# define RADEON_HORZ_STRETCH_ENABLE (1 << 25)
|
||||
@@ -55,7 +59,7 @@
|
||||
# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31)
|
||||
#define RADEON_FP_VERT_STRETCH 0x0290
|
||||
# define RADEON_VERT_PANEL_SIZE (0xfff << 12)
|
||||
# define RADEON_VERT_PANEL_SHIFT 12
|
||||
# define RADEON_VERT_PANEL_SIZE_SHIFT 12
|
||||
# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff
|
||||
# define RADEON_VERT_STRETCH_RATIO_SHIFT 0
|
||||
# define RADEON_VERT_STRETCH_RATIO_MAX 4096
|
||||
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
Copyright (c) 2002, Thomas Kurschel
|
||||
|
||||
|
||||
Part of Radeon driver
|
||||
|
||||
General Purpose I/O control registers
|
||||
*/
|
||||
|
||||
#ifndef _GPIOPAD_REGS_H
|
||||
#define _GPIOPAD_REGS_H
|
||||
|
||||
#define RADEON_GPIOPAD_MASK 0x0198
|
||||
#define RADEON_GPIOPAD_A 0x019c
|
||||
#define RADEON_GPIOPAD_EN 0x01a0
|
||||
#define RADEON_GPIOPAD_Y 0x01a4
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
Copyright (c) 2002, Thomas Kurschel
|
||||
|
||||
|
||||
Part of Radeon driver
|
||||
|
||||
Fast logger - event codes
|
||||
*/
|
||||
|
||||
enum {
|
||||
_Radeon_FlushPixelCache,
|
||||
_Radeon_WaitForFifo,
|
||||
_Radeon_WaitForIdle,
|
||||
_Radeon_WriteRegFifo,
|
||||
_GetAvailRingBufferQueue,
|
||||
_Radeon_Finish,
|
||||
_Radeon_SendCP,
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
Copyright (c) 2002, Thomas Kurschel
|
||||
|
||||
|
||||
Part of Radeon driver
|
||||
|
||||
Fast logger - event names
|
||||
*/
|
||||
|
||||
char *log_names[] = {
|
||||
"_Radeon_FlushPixelCache",
|
||||
"_Radeon_WaitForFifo",
|
||||
"_Radeon_WaitForIdle",
|
||||
"_Radeon_WriteRegFifo",
|
||||
"_GetAvailRingBufferQueue",
|
||||
"_Radeon_Finish",
|
||||
"_Radeon_SendCP",
|
||||
};
|
||||
@@ -20,5 +20,9 @@
|
||||
# define RADEON_MEM_CFG_TYPE_MASK (1 << 30)
|
||||
# define RADEON_MEM_CFG_SDR (0 << 30)
|
||||
# define RADEON_MEM_CFG_DDR (1 << 30)
|
||||
#define RADEON_GC_NB_TOM 0x015c
|
||||
#define RADEON_DISPLAY_BASE_ADDRESS 0x023c
|
||||
#define RADEON_CRTC2_DISPLAY_BASE_ADDRESS 0x033c
|
||||
#define RADEON_OV0_BASE_ADDRESS 0x043c
|
||||
|
||||
#endif
|
||||
|
||||
@@ -23,7 +23,7 @@
|
||||
do { \
|
||||
uint32 tmp = INREG( (regs), (addr) ); \
|
||||
tmp &= (mask); \
|
||||
tmp |= (val); \
|
||||
tmp |= (val) & ~(mask); \
|
||||
OUTREG( (regs), (addr), tmp ); \
|
||||
} while (0)
|
||||
|
||||
|
||||
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
Copyright (c) 2002, Thomas Kurschel
|
||||
|
||||
|
||||
Part of Radeon driver
|
||||
|
||||
Basic PLL registers access
|
||||
*/
|
||||
|
||||
#ifndef _PLL_ACCESS_H
|
||||
#define _PLL_ACCESS_H
|
||||
|
||||
#include "mmio.h"
|
||||
|
||||
|
||||
// r300: to be called after each CLOCK_CNTL_INDEX access;
|
||||
// all functions declared in this header take care of that
|
||||
// (hardware bug fix suggested by XFree86)
|
||||
void R300_PLLFix( vuint8 *regs, radeon_type asic );
|
||||
|
||||
// in general:
|
||||
// - the PLL is connected via special port
|
||||
// - you need first to choose the PLL register and then write/read its value
|
||||
//
|
||||
// if atomic updates are not safe we:
|
||||
// - verify each time whether the right register is chosen
|
||||
// - verify all values written to PLL-registers
|
||||
|
||||
|
||||
// read value "val" from PLL-register "addr"
|
||||
uint32 Radeon_INPLL( vuint8 *regs, radeon_type asic, int addr );
|
||||
|
||||
// write value "val" to PLL-register "addr"
|
||||
void Radeon_OUTPLL( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val );
|
||||
|
||||
// write "val" to PLL-register "addr" keeping bits "mask"
|
||||
void Radeon_OUTPLLP( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val, uint32 mask );
|
||||
|
||||
#endif
|
||||
@@ -4,20 +4,12 @@
|
||||
|
||||
Part of Radeon driver
|
||||
|
||||
PLL registers and access macros
|
||||
PLL registers
|
||||
*/
|
||||
|
||||
#ifndef _PLL_REG_H
|
||||
#define _PLL_REG_H
|
||||
|
||||
#include "mmio.h"
|
||||
|
||||
// atomic updates of PLL clock don't seem to always work and stick, thus
|
||||
// the bit never resets. Here - we use our own check by reading back the
|
||||
// register we've just wrote to make sure it's got the right value
|
||||
#define RADEON_ATOMIC_UPDATE 0 // Use PLL Atomic updates (seems broken)
|
||||
|
||||
|
||||
// mmio registers
|
||||
#define RADEON_CLOCK_CNTL_DATA 0x000c
|
||||
#define RADEON_CLOCK_CNTL_INDEX 0x0008
|
||||
@@ -41,6 +33,8 @@
|
||||
# define RADEON_PPLL_REF_DIV_MASK 0x03ff
|
||||
# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
|
||||
# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
|
||||
# define RADEON_PPLL_REF_DIV_ACC_SHIFT 18
|
||||
# define RADEON_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
|
||||
#define RADEON_PPLL_DIV_0 0x0004
|
||||
#define RADEON_PPLL_DIV_1 0x0005
|
||||
#define RADEON_PPLL_DIV_2 0x0006
|
||||
@@ -57,6 +51,8 @@
|
||||
# define RADEON_ECP_DIV_MASK (3 << 8)
|
||||
# define RADEON_ECP_DIV_VCLK (0 << 8)
|
||||
# define RADEON_ECP_DIV_VCLK_2 (1 << 8)
|
||||
# define RADEON_PIXCLK_ALWAYS_ONb (1 << 6) // negated
|
||||
# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1 << 7) // negated
|
||||
#define RADEON_HTOTAL_CNTL 0x0009
|
||||
#define RADEON_SCLK_CNTL 0x000d
|
||||
# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8
|
||||
@@ -92,29 +88,9 @@
|
||||
# define RADEON_PIXCLK_TV_SRC_SEL_MASK (1 << 8)
|
||||
# define RADEON_PIXCLK_TV_SRC_SEL_PIXCLK (0 << 8)
|
||||
# define RADEON_PIXCLK_TV_SRC_SEL_PIX2CLK (1 << 8)
|
||||
# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
|
||||
# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
|
||||
#define RADEON_HTOTAL2_CNTL 0x002e
|
||||
|
||||
// r300: to be called after each CLOCK_CNTL_INDEX access;
|
||||
// all functions declared in this header take care of that
|
||||
// (hardware bug fix suggested by XFree86)
|
||||
void R300_PLLFix( accelerator_info *ai );
|
||||
|
||||
// in general:
|
||||
// - the PLL is connected via special port
|
||||
// - you need first to choose the PLL register and then write/read its value
|
||||
//
|
||||
// if atomic updates are not safe we:
|
||||
// - verify each time whether the right register is chosen
|
||||
// - verify all values written to PLL-registers
|
||||
|
||||
|
||||
// read value "val" from PLL-register "addr"
|
||||
uint32 Radeon_INPLL( accelerator_info *ai, int addr );
|
||||
|
||||
// write value "val" to PLL-register "addr"
|
||||
void Radeon_OUTPLL( accelerator_info *ai, uint8 addr, uint32 val );
|
||||
|
||||
// write "val" to PLL-register "addr" keeping bits "mask"
|
||||
void Radeon_OUTPLLP( accelerator_info *ai, uint8 addr, uint32 val, uint32 mask );
|
||||
|
||||
#endif
|
||||
|
||||
@@ -31,37 +31,64 @@ enum {
|
||||
RADEON_DEVICE_NAME,
|
||||
RADEON_GET_LOG_SIZE,
|
||||
RADEON_GET_LOG_DATA,
|
||||
RADEON_ALLOC_LOCAL_MEM,
|
||||
RADEON_FREE_LOCAL_MEM,
|
||||
RADEON_ALLOC_MEM,
|
||||
RADEON_FREE_MEM,
|
||||
|
||||
RADEON_SET_I2C_SIGNALS,
|
||||
RADEON_GET_I2C_SIGNALS
|
||||
RADEON_WAITFORIDLE,
|
||||
RADEON_RESETENGINE,
|
||||
RADEON_VIPREAD,
|
||||
RADEON_VIPWRITE,
|
||||
RADEON_FINDVIPDEVICE,
|
||||
|
||||
RADEON_WAIT_FOR_CAP_IRQ,
|
||||
RADEON_DMACOPY,
|
||||
};
|
||||
|
||||
|
||||
// number of indirect buffers
|
||||
// see CP.c for this magic number
|
||||
#define NUM_INDIRECT_BUFFERS 253
|
||||
// size of an indirect buffer in dwords;
|
||||
// as hardware wants buffers to be 4k aligned and as we store all
|
||||
// buffers in one chunk, the size per buffer in bytes must be a multiple of 4k
|
||||
#define INDIRECT_BUFFER_SIZE (4096/4)
|
||||
|
||||
|
||||
// type of memory
|
||||
typedef enum {
|
||||
mt_local, // local graphics memory
|
||||
mt_PCI, // PCI memory (read: fully cachable)
|
||||
mt_AGP, // AGP memory (read: not cachable; currently not supported)
|
||||
mt_nonlocal, // non-local graphics memory (alias to one of the
|
||||
// previously defined types, see si->nonlocal_type)
|
||||
|
||||
mt_last = mt_nonlocal
|
||||
} memory_type_e;
|
||||
|
||||
// list of multi-monitor modes
|
||||
typedef enum {
|
||||
mm_none, // use one display only
|
||||
mm_combine, // combine displays to larger workspace
|
||||
mm_clone, // clone workspace, all displays show the
|
||||
// same but have independant timing
|
||||
mm_mirror // mirror ports (as used by Laptop) - not implemented yet
|
||||
mm_mirror // mirror heads (as used by Laptop) - not implemented yet
|
||||
} multi_mode_e;
|
||||
|
||||
|
||||
// type of monitor connected
|
||||
// displays devices;
|
||||
// this must be a bit field as multiple devices may be connected to one CRTC
|
||||
typedef enum {
|
||||
dt_none,
|
||||
dt_crt_1, // CRT on primary port (i.e. via DVI2CRT adapter)
|
||||
dt_crt_2, // CRT on secondary port (i.e. standard CRT connector)
|
||||
dt_lvds, // laptop flap panel
|
||||
dt_dvi_1, // DVI on primary port (i.e. standard DVI connector)
|
||||
dd_none = 0,
|
||||
dd_tv_crt = 1, // CRT on TV-DAC, i.e. on DVI port
|
||||
dd_crt = 2, // CRT on CRT-DAC, i.e. VGA port
|
||||
dd_lvds = 4, // laptop flap panel
|
||||
dd_dvi = 8, // DVI on primary port (i.e. standard DVI connector)
|
||||
dd_ctv = 16, // composite TV on TV-DAC
|
||||
dd_stv = 32, // S-Video out on TV-DAC
|
||||
|
||||
// the following connectors/devices are not supported
|
||||
dt_dvi_2, // DVI on secondary port (only provided by few models)
|
||||
dt_ctv, // composite TV
|
||||
dt_stv // S-Video out
|
||||
} display_type_e;
|
||||
dd_dvi_ext = 64 // external DVI (only provided by few models)
|
||||
} display_device_e;
|
||||
|
||||
|
||||
// type of ASIC
|
||||
@@ -69,12 +96,17 @@ typedef enum {
|
||||
rt_r100, // original Radeon
|
||||
rt_ve, // original VE version
|
||||
rt_m6, // original mobile Radeon
|
||||
rt_rs100, // IGP 320M
|
||||
rt_rv200, // Radeon 7500
|
||||
rt_m7, // mobile Radeon 7500
|
||||
rt_rs200, // IGP 330M/340M/350M
|
||||
rt_r200, // Radeon 8500/9100
|
||||
rt_rv250, // Radeon 9000
|
||||
rt_rv280, // Radeon 9200
|
||||
rt_m9, // mobile Radeon 9000
|
||||
|
||||
// from here on, r300 and up must be located as ATI modified the PLL
|
||||
// with r300 and the code only tests for >= rt_r300
|
||||
rt_r300, // Radeon 9700
|
||||
rt_r300_4p, // Radeon 9500
|
||||
rt_rv350, // Radeon 9600
|
||||
@@ -84,6 +116,26 @@ typedef enum {
|
||||
} radeon_type;
|
||||
|
||||
|
||||
// TV standard
|
||||
typedef enum {
|
||||
ts_ntsc,
|
||||
ts_pal,
|
||||
ts_palm,
|
||||
ts_palcn,
|
||||
ts_scart_pal,
|
||||
ts_pal60
|
||||
} tv_standard;
|
||||
|
||||
|
||||
// type of TV-Chip
|
||||
typedef enum {
|
||||
tc_none,
|
||||
tc_external_rt1, // external Rage Theatre
|
||||
tc_internal_rt1, // internal version 1
|
||||
tc_internal_rt2, // internal version 2
|
||||
} tv_chip_type;
|
||||
|
||||
|
||||
// info about cursor
|
||||
typedef struct {
|
||||
uint8* data; // pointer to framebuffer containing cursor image
|
||||
@@ -99,6 +151,131 @@ typedef struct {
|
||||
} cursor_info;
|
||||
|
||||
|
||||
// head as seen by accelerant
|
||||
typedef struct {
|
||||
int physical_head; // idx of physical head
|
||||
uint32 rel_x, rel_y; // relative position in multi-monitor mode
|
||||
} virtual_head;
|
||||
|
||||
|
||||
// info about flat panel connected to LVDS or DVI port
|
||||
typedef struct {
|
||||
uint panel_pwr_delay;
|
||||
uint panel_xres, panel_yres;
|
||||
|
||||
uint h_blank, h_over_plus, h_sync_width;
|
||||
uint v_blank, v_over_plus, v_sync_width;
|
||||
uint dot_clock; // in kHz (this is BeOS like, ATI uses 10 kHz steps!)
|
||||
|
||||
bool is_fp2; // true, if second flat panel
|
||||
// display_type_e disp_type;
|
||||
|
||||
uint64 h_ratio; // current stretch ratio, needed for overlays
|
||||
uint64 v_ratio; // (mode_res/native_res; 32.32)
|
||||
} fp_info;
|
||||
|
||||
|
||||
// physical head
|
||||
typedef struct {
|
||||
bool is_crtc2; // true, if connected to crtc2
|
||||
display_device_e active_displays; // currently driven displays
|
||||
display_device_e chosen_displays; // displays to be driven by next mode switch
|
||||
sem_id vblank; // vertical blank interrupt semaphore
|
||||
bool cursor_on_screen; // cursor is visible on this head
|
||||
display_mode mode; // display mode of this head
|
||||
int8 flatpanel_port; // linked flat panel port (-1 if none)
|
||||
} physical_head;
|
||||
|
||||
|
||||
// info about PLLs on graphics card as retrieved from BIOS
|
||||
// all values are in 10kHz
|
||||
typedef struct {
|
||||
uint32 max_pll_freq; // maximum PLL output frequency
|
||||
uint32 min_pll_freq; // minimum PLL output frequency
|
||||
uint32 xclk; // core frequency
|
||||
uint32 ref_div; // default reference divider
|
||||
uint32 ref_freq; // PLL reference frequency
|
||||
} general_pll_info;
|
||||
|
||||
|
||||
// mapping of pll divider code to actual divider value
|
||||
typedef struct {
|
||||
uint8 divider; // divider
|
||||
uint8 code; // code as used in register
|
||||
} pll_divider_map;
|
||||
|
||||
|
||||
// info about a PLL
|
||||
// all values are in 10 kHz
|
||||
typedef struct {
|
||||
pll_divider_map *post_divs; // list of possible post dividers
|
||||
pll_divider_map *extra_post_divs; // list of possible extra post dividers
|
||||
uint32 ref_freq; // reference frequency
|
||||
uint32 vco_min, vco_max; // VCO frequency range
|
||||
uint32 min_ref_div, max_ref_div; // reference divider range
|
||||
uint32 pll_in_min, pll_in_max; // PLL input frequency range
|
||||
uint32 extra_feedback_div; // hardwired divider before feedback divider
|
||||
uint32 min_feedback_div, max_feedback_div; // feedback divider range
|
||||
uint32 best_vco; // preferred VCO frequency (0 for don't care)
|
||||
} pll_info;
|
||||
|
||||
|
||||
// PLL divider values
|
||||
typedef struct {
|
||||
uint32 post_code; // code for post divider
|
||||
uint32 post; // value of post divider
|
||||
uint32 extra_post_code; // code for extra post divider
|
||||
uint32 extra_post; // value of extra post divider
|
||||
uint32 ref; // reference divider
|
||||
uint32 feedback; // feedback divider
|
||||
uint32 freq; // resulting frequency
|
||||
} pll_dividers;
|
||||
|
||||
|
||||
// TV-Out parameters
|
||||
typedef struct {
|
||||
uint16 y_accum_init;
|
||||
uint16 uv_accum_init;
|
||||
uint16 uv_inc;
|
||||
uint16 h_inc;
|
||||
uint32 tv_clocks_to_active;
|
||||
|
||||
uint16 f_restart;
|
||||
uint16 v_restart;
|
||||
uint16 h_restart;
|
||||
bool mode888;
|
||||
|
||||
uint16 y_saw_tooth_slope;
|
||||
uint16 y_saw_tooth_amp;
|
||||
uint16 y_rise_accum_init;
|
||||
uint16 y_fall_accum_init;
|
||||
bool y_coeff_enable;
|
||||
uint8 y_coeff_value;
|
||||
|
||||
pll_dividers tv_dividers;
|
||||
pll_dividers crt_dividers;
|
||||
} tv_params;
|
||||
|
||||
|
||||
// TV-timing
|
||||
typedef struct {
|
||||
uint32 freq; // TV sub carrier frequency x12
|
||||
uint16 h_total;
|
||||
uint16 h_sync_len;
|
||||
uint16 h_genclk_delay;
|
||||
uint16 h_setup_delay;
|
||||
uint16 h_active_delay;
|
||||
uint16 h_active_len;
|
||||
uint16 v_total;
|
||||
uint16 v_active_lines;
|
||||
uint16 v_field_total;
|
||||
uint16 v_fields;
|
||||
uint16 f_total;
|
||||
uint16 frame_size_adjust;
|
||||
uint32 scale;
|
||||
} tv_timing;
|
||||
|
||||
|
||||
// list of register content (used for mode changes)
|
||||
typedef struct {
|
||||
// CRTC regs
|
||||
@@ -111,23 +288,32 @@ typedef struct {
|
||||
uint32 crtc_ext_cntl;
|
||||
uint32 crtc_offset_cntl;
|
||||
|
||||
// Flat panel regs
|
||||
// many of them aren't touched by us, so they aren't stored here
|
||||
uint32 fp_gen_cntl;
|
||||
uint32 fp_horz_stretch;
|
||||
uint32 fp_panel_cntl;
|
||||
// RMX registers
|
||||
uint32 fp_horz_stretch;
|
||||
uint32 fp_vert_stretch;
|
||||
|
||||
// Flat panel regs
|
||||
uint32 fp_gen_cntl;
|
||||
uint32 fp_panel_cntl;
|
||||
uint32 lvds_gen_cntl;
|
||||
uint32 fp_h_sync_strt_wid;
|
||||
uint32 fp_v_sync_strt_wid;
|
||||
uint32 fp2_gen_cntl;
|
||||
|
||||
uint32 fp2_h_sync_strt_wid;
|
||||
uint32 fp2_v_sync_strt_wid;
|
||||
|
||||
// DAC regs
|
||||
uint32 dac_cntl2;
|
||||
uint32 dac_cntl;
|
||||
//uint32 dac2_cntl;
|
||||
uint32 disp_hw_debug;
|
||||
|
||||
// PLL regs
|
||||
uint32 ppll_div_3;
|
||||
uint32 ppll_ref_div;
|
||||
uint32 htotal_cntl;
|
||||
|
||||
// pure information
|
||||
uint32 dot_clock_freq; // in 10 kHz
|
||||
uint32 pll_output_freq;// in 10 kHz
|
||||
int feedback_div;
|
||||
@@ -136,54 +322,45 @@ typedef struct {
|
||||
// Common regs
|
||||
uint32 surface_cntl;
|
||||
uint32 disp_output_cntl;
|
||||
|
||||
// TV-Out registers
|
||||
uint32 tv_ftotal;
|
||||
uint32 tv_vscaler_cntl1;
|
||||
uint32 tv_y_saw_tooth_cntl;
|
||||
uint32 tv_y_fall_cntl;
|
||||
uint32 tv_y_rise_cntl;
|
||||
uint32 tv_vscaler_cntl2;
|
||||
uint32 tv_hrestart;
|
||||
uint32 tv_vrestart;
|
||||
uint32 tv_frestart;
|
||||
uint32 tv_tv_pll_cntl;
|
||||
uint32 tv_crt_pll_cntl;
|
||||
uint32 tv_clock_sel_cntl;
|
||||
uint32 tv_clkout_cntl;
|
||||
uint32 tv_htotal;
|
||||
uint32 tv_hsize;
|
||||
uint32 tv_hdisp;
|
||||
uint32 tv_hstart;
|
||||
uint32 tv_vtotal;
|
||||
uint32 tv_vdisp;
|
||||
uint32 tv_sync_size;
|
||||
uint32 tv_timing_cntl;
|
||||
uint32 tv_dac_cntl; // affects CRT connected to TV-DAC
|
||||
uint32 tv_modulator_cntl1;
|
||||
uint32 tv_modulator_cntl2;
|
||||
uint32 tv_data_delay_a;
|
||||
uint32 tv_data_delay_b;
|
||||
uint32 tv_frame_lock_cntl;
|
||||
uint32 tv_pll_cntl1;
|
||||
uint32 tv_rgb_cntl;
|
||||
uint32 tv_pre_dac_mux_cntl;
|
||||
uint32 tv_master_cntl;
|
||||
uint32 tv_uv_adr;
|
||||
uint32 tv_pll_fine_cntl;
|
||||
} port_regs;
|
||||
|
||||
|
||||
// port as seen by accelerant
|
||||
typedef struct {
|
||||
bool is_crtc2;
|
||||
int physical_port; // idx of physical port
|
||||
|
||||
uint32 rel_x, rel_y; // relative position in multi-monitor mode
|
||||
bool cursor_on_screen; // cursor is visible on this port
|
||||
|
||||
display_mode mode; // display mode of this port
|
||||
} virtual_port;
|
||||
|
||||
|
||||
// physical port
|
||||
typedef struct {
|
||||
display_type_e disp_type;
|
||||
sem_id vblank; // vertical blank interrupt semaphore
|
||||
} physical_port;
|
||||
|
||||
|
||||
// info about flat panel connected to port
|
||||
typedef struct {
|
||||
uint panel_pwr_delay;
|
||||
uint panel_xres, panel_yres;
|
||||
|
||||
uint h_blank, h_over_plus, h_sync_width;
|
||||
uint v_blank, v_over_plus, v_sync_width;
|
||||
uint dot_clock; // in kHz (this is BeOS like, ATI uses 10 kHz steps!)
|
||||
|
||||
display_type_e disp_type;
|
||||
|
||||
uint64 h_ratio; // current stretch ratio, needed for overlays
|
||||
uint64 v_ratio; // (mode_res/native_res; 16.16)
|
||||
} fp_info;
|
||||
|
||||
|
||||
// info about PLL on graphics card
|
||||
typedef struct {
|
||||
uint32 max_pll_freq;
|
||||
uint32 min_pll_freq;
|
||||
uint32 xclk;
|
||||
uint32 ref_div;
|
||||
uint32 ref_freq;
|
||||
} pll_info;
|
||||
|
||||
|
||||
// one overlay buffer
|
||||
typedef struct overlay_buffer_node {
|
||||
struct overlay_buffer_node *next, *prev;
|
||||
uint32 mem_handle;
|
||||
@@ -193,6 +370,8 @@ typedef struct overlay_buffer_node {
|
||||
overlay_buffer buffer;
|
||||
} overlay_buffer_node;
|
||||
|
||||
|
||||
// info about active overlay
|
||||
typedef struct {
|
||||
overlay_token ot;
|
||||
overlay_buffer ob;
|
||||
@@ -201,22 +380,24 @@ typedef struct {
|
||||
uint16 h_display_start;
|
||||
uint16 v_display_start;
|
||||
|
||||
overlay_buffer_node *on;
|
||||
int8 port; // physical port where the overlay is shown on
|
||||
overlay_buffer_node *on; // current buffer
|
||||
overlay_buffer_node *prev_on; // previous buffer (for temporal deinterlace, currently unused)
|
||||
int8 head; // physical head where the overlay is shown on
|
||||
uint32 rel_offset; // offset of overlay source due to clipping
|
||||
} overlay_info;
|
||||
|
||||
// each accelerator gets one "virtual card", i.e. you
|
||||
// can have independant accelerators for each port
|
||||
|
||||
// each accelerant gets one "virtual card", i.e. you
|
||||
// can have independant accelerants for each head
|
||||
// (this is an ongoing project ;)
|
||||
typedef struct {
|
||||
uint32 id; // identifier used to know which card the 2D accelerator
|
||||
// is prepared for (we use area_id of this structure)
|
||||
virtual_port ports[2];
|
||||
uint8 num_ports;
|
||||
virtual_head heads[2]; // heads assigned to virtual card
|
||||
uint8 num_heads; // number of heads assigned to virtual card
|
||||
|
||||
int8 independant_ports; // number of ports to be programmed independantly
|
||||
int8 different_ports; // number of ports showing different parts of framebuffer
|
||||
int8 independant_heads; // number of heads to be programmed independantly
|
||||
int8 different_heads; // number of heads showing different parts of framebuffer
|
||||
bool scroll; // scrolling in virtual area enabled
|
||||
|
||||
uint32 datatype; // Radeon code for pixel format
|
||||
@@ -231,86 +412,156 @@ typedef struct {
|
||||
|
||||
multi_mode_e wanted_multi_mode; // multi monitor mode as requested by user
|
||||
|
||||
bool swapDisplays; // true to swap monitors
|
||||
bool swap_displays; // true to swap monitors
|
||||
|
||||
frame_buffer_config fbc; // data for direct frame buffer access
|
||||
|
||||
display_mode mode; // offical mode with multi-monitor bits set
|
||||
overlay_buffer_node *overlay_buffers; // list of allocated overlay buffers
|
||||
|
||||
//int8 whished_overlay_port; // port where users whishes the overlay to be
|
||||
//int8 whished_overlay_head; // head where users whishes the overlay to be
|
||||
bool uses_overlay; // true if this virtual card owns overlay
|
||||
|
||||
int state_buffer_idx;
|
||||
int state_buffer_size;
|
||||
} virtual_card;
|
||||
|
||||
|
||||
// status of overlay
|
||||
typedef struct {
|
||||
vint32 inuse; // one, if someone allocated overlay port
|
||||
vint32 inuse; // one, if someone allocated overlay head
|
||||
// (this doesn't necessarily mean that an overlay is shown)
|
||||
uint32 token; // arbitrarily chosen token to identify overlay owner
|
||||
// (increased by 1 whenever there is a new owner)
|
||||
uint32 auto_flip_reg; // content of auto_flip_reg
|
||||
} overlay_mgr_info;
|
||||
|
||||
|
||||
// info about indirect CP buffer
|
||||
typedef struct {
|
||||
int next; // next used/free buffer (-1 for EOL)
|
||||
int32 send_tag; // tag assigned when buffer was submitted
|
||||
} indirect_buffer;
|
||||
|
||||
|
||||
// info about command processor (CP) state
|
||||
typedef struct {
|
||||
benaphore lock; // lock to be acquired when talking to CP or
|
||||
// when accesing this structure
|
||||
|
||||
// ring buffer (in non-local memory)
|
||||
struct {
|
||||
uint32 mem_offset; // offset in non-local memory
|
||||
uint32 vm_base; // base of ring buffer as seen by graphics card
|
||||
uint32 tail, tail_mask; // next write position in dwords; mask for wrap-arounds
|
||||
uint32 size; // size in dwords
|
||||
//uint32 head_offset; // offset for automatically updates head in DMA buffer
|
||||
|
||||
//uint32 start_offset;
|
||||
memory_type_e mem_type;
|
||||
//uint32 *start; // pointer to ring buffer
|
||||
//vuint32 *head; // pointer to automatically updated read position
|
||||
|
||||
uint32 space; // known space in ring buffer
|
||||
uint32 mem_handle; // handle of memory of indirect buffers
|
||||
} ring;
|
||||
|
||||
// feedback registers (in PCI memory)
|
||||
struct {
|
||||
//vuint32 *ptr; // pointer to scratch registers
|
||||
uint32 scratch_mem_offset; // offset of scratch registers in feedback memory
|
||||
uint32 head_mem_offset; // offset of head register in feedback memory
|
||||
uint32 scratch_vm_start; // virtual address of scratch as seen by GC
|
||||
uint32 head_vm_address; // virtual address of head as seen by GC
|
||||
memory_type_e mem_type; // memory type of feedback memory
|
||||
uint32 mem_handle; // handle of feedback memory
|
||||
} feedback;
|
||||
|
||||
|
||||
// indirect buffers (in non-local memory)
|
||||
// for indeces: -1 means "none"
|
||||
struct {
|
||||
int free_list; // index of first empty buffer
|
||||
int oldest, // oldest submitted buffer
|
||||
newest; // newest submitted buffer
|
||||
int active_state; // index of active state buffer
|
||||
uint64 cur_tag; // tag of last submitted indirect buffer
|
||||
|
||||
memory_type_e mem_type;
|
||||
uint32 mem_offset; // offset of indirect buffers in non-local memory
|
||||
uint32 vm_start; // start of indirect buffers as seen by graphics card
|
||||
|
||||
indirect_buffer buffers[NUM_INDIRECT_BUFFERS]; // info about buffers
|
||||
uint32 mem_handle; // handle of memory of indirect buffers
|
||||
} buffers;
|
||||
} CP_info;
|
||||
|
||||
|
||||
// info about different graphics-related memory
|
||||
// (see memory_type_e)
|
||||
typedef struct {
|
||||
area_id area; // area to memory
|
||||
uint32 size; // usable size in bytes
|
||||
uint32 virtual_addr_start; // virtual address (for graphics card!)
|
||||
uint32 virtual_size; // reserved virtual address space in bytes
|
||||
} memory_type_info;
|
||||
|
||||
|
||||
// data published by kernel and shared by all accelerant/virtual cards
|
||||
typedef struct {
|
||||
// filled out by kernel
|
||||
uint16 vendor_id; // PCI vendor id
|
||||
uint16 device_id; // PCI device id
|
||||
uint8 revision; // PCI device revision
|
||||
CP_info cp; // info concerning command processor
|
||||
|
||||
bool has_crtc2; // has second CRTC
|
||||
radeon_type asic;
|
||||
|
||||
pll_info pll;
|
||||
|
||||
area_id regs_area; // area of memory mapped registers
|
||||
area_id fb_area; // area of frame buffer
|
||||
uint8 *framebuffer; // pointer to frame buffer (visible by all apps!)
|
||||
void *framebuffer_pci; // physical address of frame buffer
|
||||
|
||||
physical_port ports[2];
|
||||
fp_info fp_port;
|
||||
|
||||
uint32 local_mem_size; // size of graphics memory
|
||||
|
||||
uint32 AGP_vm_start; // logical address (for graphics card) of AGP memory
|
||||
uint32 AGP_vm_size; // size of AGP address range
|
||||
|
||||
uint32 nonlocal_vm_start; // logical address (for graphics card) of nonlocal memory
|
||||
// always use this one, as it is valid in PCI mode too
|
||||
uint32 *nonlocal_mem; // logical address (for CPU) of nonlocal memory
|
||||
uint32 nonlocal_mem_size; // size of nonlocal memory
|
||||
|
||||
|
||||
// set by accelerator
|
||||
// set by accelerant
|
||||
struct {
|
||||
uint64 count; // count of submitted CP commands
|
||||
uint64 last_idle; // count when engine was idle last time
|
||||
uint64 written; // last count passed to CP
|
||||
benaphore lock; // engine lock
|
||||
} engine;
|
||||
|
||||
struct { // DMA ring buffer of CP
|
||||
uint32 start_offset; // offset in DMA buffer
|
||||
uint32 tail, tail_mask; // next write position in dwords; mask for wrap-arounds
|
||||
uint32 size; // size in dwords
|
||||
uint32 head_offset; // offset for automatically updates head in DMA buffer
|
||||
} engine;
|
||||
|
||||
uint32 *start; // pointer to ring buffer
|
||||
vuint32 *head; // pointer to automatically updates read position
|
||||
} ring;
|
||||
uint16 vendor_id; // PCI vendor id
|
||||
uint16 device_id; // PCI device id
|
||||
uint8 revision; // PCI device revision
|
||||
|
||||
vuint32 *scratch_ptr; // pointer to scratch registers (in DMA buffer)
|
||||
//bool has_crtc2; // has second CRTC
|
||||
radeon_type asic; // ASIC version
|
||||
bool is_mobility; // mobility version
|
||||
tv_chip_type tv_chip; // type of TV-Out encoder
|
||||
|
||||
uint8 theatre_channel; // VIP channel of Rage Theatre (if applicable)
|
||||
|
||||
general_pll_info pll;
|
||||
|
||||
area_id regs_area; // area of memory mapped registers
|
||||
area_id ROM_area; // area of ROM
|
||||
//area_id fb_area; // area of frame buffer
|
||||
void *framebuffer_pci; // physical address of frame buffer (aka local memory)
|
||||
// this is a hack needed by BeOS
|
||||
|
||||
physical_head heads[2]; // physical heads
|
||||
uint8 num_heads; // number of physical heads
|
||||
|
||||
display_device_e connected_displays; // bit-field of connected displays
|
||||
|
||||
fp_info flatpanels[2]; // info about connected flat panels (if any)
|
||||
|
||||
memory_type_info memory[mt_last]; // info about memory types
|
||||
memory_type_e nonlocal_type; // default type of non-local memory
|
||||
|
||||
uint8 *local_mem; // address of local memory;
|
||||
// this is a hack requested by BeOS
|
||||
|
||||
area_id mode_list_area; // area containing display mode list
|
||||
uint mode_count;
|
||||
|
||||
uint32 active_vc; // currently selected virtual card
|
||||
|
||||
uint32 active_vc; // currently selected virtual card in terms of 2D acceleration
|
||||
|
||||
uint32 dac_cntl2; // content of dac_cntl2 register
|
||||
|
||||
overlay_info pending_overlay;
|
||||
overlay_info active_overlay;
|
||||
overlay_mgr_info overlay_mgr;
|
||||
overlay_info pending_overlay; // overlay to be shown
|
||||
overlay_info active_overlay; // overlay shown
|
||||
overlay_mgr_info overlay_mgr; // status of overlay
|
||||
|
||||
// data needed for VBI emulation
|
||||
// (currently not fully implemented - if the user disabled graphics card
|
||||
@@ -336,25 +587,76 @@ typedef struct {
|
||||
char *name; // pointer to buffer containing name (in)
|
||||
} radeon_device_name;
|
||||
|
||||
// alloc local memory
|
||||
// alloc (non-)local memory
|
||||
typedef struct {
|
||||
uint32 magic;
|
||||
uint32 size;
|
||||
uint32 fb_offset;
|
||||
uint32 handle;
|
||||
} radeon_alloc_local_mem;
|
||||
uint32 magic;
|
||||
memory_type_e memory_type;// type of memory
|
||||
uint32 size; // size in bytes
|
||||
uint32 offset; // offset in memory
|
||||
uint32 handle; // handle (needed to free memory)
|
||||
bool global; // set this to true if memory should persist even
|
||||
// if client gets terminated
|
||||
} radeon_alloc_mem;
|
||||
|
||||
// free local memory
|
||||
// free (non-)local memory
|
||||
typedef struct {
|
||||
uint32 magic;
|
||||
uint32 handle;
|
||||
} radeon_free_local_mem;
|
||||
uint32 magic;
|
||||
memory_type_e memory_type;// type of memory
|
||||
uint32 handle; // memory handle
|
||||
bool global; // must be same as on alloc_local_mem
|
||||
} radeon_free_mem;
|
||||
|
||||
// get/set i2c signals
|
||||
// wait for idle
|
||||
typedef struct {
|
||||
uint32 magic;
|
||||
int port;
|
||||
int value;
|
||||
} radeon_getset_i2c;
|
||||
uint32 magic;
|
||||
bool keep_lock; // keep lock after engine is idle
|
||||
} radeon_wait_for_idle;
|
||||
|
||||
// read VIP register
|
||||
typedef struct {
|
||||
uint32 magic;
|
||||
uint channel; // channel, i.e. device
|
||||
uint address; // address
|
||||
uint32 data; // read data
|
||||
} radeon_vip_read;
|
||||
|
||||
// write VIP register
|
||||
typedef struct {
|
||||
uint32 magic;
|
||||
uint channel; // channel, i.e. device
|
||||
uint address; // address
|
||||
uint32 data; // data to write
|
||||
} radeon_vip_write;
|
||||
|
||||
// find channel of device with given ID
|
||||
typedef struct {
|
||||
uint32 magic;
|
||||
uint32 device_id; // id of device
|
||||
uint channel; // channel of device (-1 if not found)
|
||||
} radeon_find_vip_device;
|
||||
|
||||
// wait for capture interrupt and get status about
|
||||
typedef struct {
|
||||
uint32 magic;
|
||||
bigtime_t timeout; // timeout to wait for irq
|
||||
bigtime_t timestamp; // timestamp when last capturing was finished
|
||||
uint32 int_status; // content of RADEON_CAP_INT_STATUS
|
||||
uint32 counter; // number of capture interrupts so far
|
||||
} radeon_wait_for_cap_irq;
|
||||
|
||||
// copy data from frame buffer to some memory location
|
||||
typedef struct {
|
||||
uint32 magic;
|
||||
uint32 src; // offset of source data in frame buffer
|
||||
void *target; // target buffer
|
||||
size_t size; // number of bytes to copy
|
||||
bool lock_mem; // true, if target needs to be locked
|
||||
bool contiguous; // true, if target is physically contiguous
|
||||
} radeon_dma_copy;
|
||||
|
||||
// parameter for ioctl without further arguments
|
||||
typedef struct {
|
||||
uint32 magic;
|
||||
} radeon_no_arg;
|
||||
|
||||
#endif
|
||||
|
||||
@@ -13,11 +13,21 @@
|
||||
#define RADEON_GEN_INT_CNTL 0x0040
|
||||
# define RADEON_CRTC_VBLANK_MASK (1 << 0)
|
||||
# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
|
||||
# define RADEON_GUIDMA_MASK (1 << 30)
|
||||
# define RADEON_VIDDMA_MASK (1 << 31)
|
||||
#define RADEON_GEN_INT_STATUS 0x0044
|
||||
# define RADEON_CRTC_VBLANK_STAT (1 << 0)
|
||||
# define RADEON_CRTC_VBLANK_STAT_AK (1 << 0)
|
||||
# define RADEON_CAP0_INT_ACTIVE (1 << 8)
|
||||
# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
|
||||
# define RADEON_CRTC2_VBLANK_STAT_AK (1 << 9)
|
||||
# define RADEON_GUIDMA_STAT (1 << 30)
|
||||
# define RADEON_GUIDMA_AK (1 << 30)
|
||||
# define RADEON_VIDDMA_STAT (1 << 31)
|
||||
# define RADEON_VIDDMA_AK (1 << 31)
|
||||
|
||||
#define RADEON_CAP_INT_CNTL 0x0908
|
||||
#define RADEON_CAP_INT_STATUS 0x090c
|
||||
|
||||
#define RADEON_RBBM_SOFT_RESET 0x00f0
|
||||
# define RADEON_SOFT_RESET_CP (1 << 0)
|
||||
|
||||
@@ -0,0 +1,74 @@
|
||||
/*
|
||||
Copyright (c) 2002, Thomas Kurschel
|
||||
|
||||
|
||||
Part of Radeon driver
|
||||
|
||||
Rage Theatre registers (to be accessed via VIP)
|
||||
*/
|
||||
|
||||
#ifndef _THEATRE_REGS_H
|
||||
#define _THEATRE_REGS_H
|
||||
|
||||
#define THEATRE_ID 0x4D541002
|
||||
|
||||
#define THEATRE_VIP_MASTER_CNTL 0x0040
|
||||
#define THEATRE_VIP_RGB_CNTL 0x0048
|
||||
#define THEATRE_VIP_CLKOUT_CNTL 0x004c
|
||||
#define THEATRE_VIP_SYNC_CNTL 0x0050
|
||||
#define THEATRE_VIP_I2C_CNTL 0x0054
|
||||
#define THEATRE_VIP_HTOTAL 0x0080
|
||||
#define THEATRE_VIP_HDISP 0x0084
|
||||
#define THEATRE_VIP_HSIZE 0x0088
|
||||
#define THEATRE_VIP_HSTART 0x008c
|
||||
#define THEATRE_VIP_HCOUNT 0x0090
|
||||
#define THEATRE_VIP_VTOTAL 0x0094
|
||||
#define THEATRE_VIP_VDISP 0x0098
|
||||
#define THEATRE_VIP_VCOUNT 0x009c
|
||||
#define THEATRE_VIP_FTOTAL 0x00a0
|
||||
#define THEATRE_VIP_FCOUNT 0x00a4
|
||||
#define THEATRE_VIP_FRESTART 0x00a8
|
||||
#define THEATRE_VIP_HRESTART 0x00ac
|
||||
#define THEATRE_VIP_VRESTART 0x00b0
|
||||
#define THEATRE_VIP_SYNC_SIZE 0x00b4
|
||||
#define THEATRE_VIP_TV_PLL_CNTL 0x00c0
|
||||
#define THEATRE_VIP_CRT_PLL_FINE_CNTL 0x00bc
|
||||
#define THEATRE_VIP_TV_PLL_FINE_CNTL 0x00b8
|
||||
#define THEATRE_VIP_CRT_PLL_CNTL 0x00c4
|
||||
#define THEATRE_VIP_PLL_CNTL0 0x00c8
|
||||
#define THEATRE_VIP_PLL_TEST_CNTL 0x00cc
|
||||
#define THEATRE_VIP_CLOCK_SEL_CNTL 0x00d0
|
||||
#define THEATRE_VIP_FRAME_LOCK_CNTL 0x0100
|
||||
#define THEATRE_VIP_SYNC_LOCK_CNTL 0x0104
|
||||
#define THEATRE_VIP_TVO_SYNC_PAT_ACCUM 0x0108
|
||||
#define THEATRE_VIP_TVO_SYNC_THRESHOLD 0x010c
|
||||
#define THEATRE_VIP_TVO_SYNC_PAT_EXPECT 0x0110
|
||||
#define THEATRE_VIP_DELAY_ONE_MAP_A 0x0114
|
||||
#define THEATRE_VIP_DELAY_ONE_MAP_B 0x0118
|
||||
#define THEATRE_VIP_DELAY_ZERO_MAP_A 0x011c
|
||||
#define THEATRE_VIP_DELAY_ZERO_MAP_B 0x0120
|
||||
#define THEATRE_VIP_TVO_DATA_DELAY_A 0x0140
|
||||
#define THEATRE_VIP_TVO_DATA_DELAY_B 0x0144
|
||||
#define THEATRE_VIP_HOST_READ_DATA 0x0180
|
||||
#define THEATRE_VIP_HOST_WRITE_DATA 0x0184
|
||||
#define THEATRE_VIP_HOST_RD_WT_CNTL 0x0188
|
||||
#define THEATRE_VIP_VSCALER_CNTL 0x01c0
|
||||
#define THEATRE_VIP_TIMING_CNTL 0x01c4
|
||||
#define THEATRE_VIP_VSCALER_CNTL2 0x01c8
|
||||
#define THEATRE_VIP_Y_FALL_CNTL 0x01cc
|
||||
#define THEATRE_VIP_Y_RISE_CNTL 0x01d0
|
||||
#define THEATRE_VIP_Y_SAW_TOOTH_CNTL 0x01d4
|
||||
#define THEATRE_VIP_MODULATOR_CNTL1 0x0200
|
||||
#define THEATRE_VIP_MODULATOR_CNTL2 0x0204
|
||||
#define THEATRE_VIP_PRE_DAC_MUX_CNTL 0x0240
|
||||
#define THEATRE_VIP_TV_DAC_CNTL 0x0280
|
||||
#define THEATRE_VIP_CRC_CNTL 0x02c0
|
||||
#define THEATRE_VIP_VIDEO_PORT_SIG 0x02c4
|
||||
#define THEATRE_VIP_VBI_20BIT_CNTL 0x02d0
|
||||
#define THEATRE_VIP_VBI_LEVEL_CNTL 0x02d8
|
||||
#define THEATRE_VIP_UV_ADR 0x0300
|
||||
#define THEATRE_VIP_HSCALER_CONTROL 0x0600
|
||||
#define THEATRE_VIP_VSCALER_CONTROL 0x0604
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,141 @@
|
||||
/*
|
||||
Copyright (c) 2003, Thomas Kurschel
|
||||
|
||||
|
||||
Part of Radeon driver
|
||||
|
||||
TV-Out registers
|
||||
*/
|
||||
|
||||
#ifndef _TV_OUT_REGS_H
|
||||
#define _TV_OUT_REGS_H
|
||||
|
||||
#define RADEON_TV_MASTER_CNTL 0x0800
|
||||
# define RADEON_TV_MASTER_CNTL_TV_ASYNC_RST (1 << 0)
|
||||
# define RADEON_TV_MASTER_CNTL_CRT_ASYNC_RST (1 << 1)
|
||||
# define RADEON_TV_MASTER_CNTL_RESTART_PHASE_FIX (1 << 3)
|
||||
# define RADEON_TV_MASTER_CNTL_TV_FIFO_ASYNC_RST (1 << 4)
|
||||
# define RADEON_TV_MASTER_CNTL_CRT_FIFO_CE_EN (1 << 9)
|
||||
# define RADEON_TV_MASTER_CNTL_TV_FIFO_CE_EN (1 << 10)
|
||||
# define RADEON_TV_MASTER_CNTL_RE_SYNC_NOW_SEL_MASK (3 << 14)
|
||||
# define RADEON_TV_MASTER_CNTL_TV_CLK_ALWAYS_ONb (1 << 30)
|
||||
# define RADEON_TV_MASTER_CNTL_TV_ON (1 << 31)
|
||||
|
||||
#define RADEON_TV_RGB_CNTL 0x0804
|
||||
# define RADEON_TV_RGB_CNTL_RGB_SRC_SEL_SHIFT 8
|
||||
# define RADEON_TV_RGB_CNTL_RGB_DITHER_EN (1 << 5)
|
||||
# define RADEON_TV_RGB_CNTL_UVRAM_READ_MARGIN_SHIFT 16
|
||||
# define RADEON_TV_RGB_CNTL_FIFORAM_FIFOMACRO_READ_MARGIN_SHIFT 20
|
||||
|
||||
#define RADEON_TV_HTOTAL 0x080c
|
||||
#define RADEON_TV_HDISP 0x0810
|
||||
#define RADEON_TV_HSTART 0x0818
|
||||
#define RADEON_TV_VTOTAL 0x0820
|
||||
#define RADEON_TV_VDISP 0x0824
|
||||
#define RADEON_TV_FTOTAL 0x082c
|
||||
#define RADEON_TV_FRESTART 0x0834
|
||||
#define RADEON_TV_HRESTART 0x0838
|
||||
#define RADEON_TV_VRESTART 0x083c
|
||||
|
||||
#define RADEON_TV_VSCALER_CNTL1 0x084c
|
||||
# define RADEON_TV_VSCALER_CNTL1_RESTART_FIELD (1 << 29)
|
||||
# define RADEON_TV_VSCALER_CNTL1_Y_DEL_W_SIG_SHIFT 26
|
||||
|
||||
#define RADEON_TV_TIMING_CNTL 0x0850
|
||||
# define RADEON_TV_TIMING_CNTL_UV_OUTPUT_POST_SCALE_SHIFT 24
|
||||
|
||||
#define RADEON_TV_VSCALER_CNTL2 0x0854
|
||||
# define RADEON_TV_VSCALER_CNTL2_DITHER_MODE (1 << 0)
|
||||
# define RADEON_TV_VSCALER_CNTL2_Y_OUTPUT_DITHER_EN (1 << 1)
|
||||
# define RADEON_TV_VSCALER_CNTL2_UV_OUTPUT_DITHER_EN (1 << 2)
|
||||
# define RADEON_TV_VSCALER_CNTL2_UV_TO_BUF_DITHER_EN (1 << 3)
|
||||
# define RADEON_TV_VSCALER_CNTL2_UV_ACCUM_INIT_SHIFT 24
|
||||
|
||||
#define RADEON_TV_Y_FALL_CNTL 0x0858
|
||||
# define RADEON_TV_Y_FALL_CNTL_Y_FALL_PING_PONG (1 << 16)
|
||||
# define RADEON_TV_Y_FALL_CNTL_Y_COEFF_EN (1 << 17)
|
||||
# define RADEON_TV_Y_FALL_CNTL_Y_COEFF_VALUE_SHIFT 24
|
||||
|
||||
#define RADEON_TV_Y_RISE_CNTL 0x085c
|
||||
# define RADEON_TV_Y_RISE_CNTL_Y_RISE_PING_PONG 16
|
||||
|
||||
#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860
|
||||
# define RADEON_TV_Y_SAW_TOOTH_CNTL_SLOPE_SHIFT 16
|
||||
|
||||
#define RADEON_TV_MODULATOR_CNTL1 0x0870
|
||||
# define RADEON_TV_MODULATOR_CNTL1_ALT_PHASE_EN (1 << 6)
|
||||
# define RADEON_TV_MODULATOR_CNTL1_SYNC_TIP_LEVEL (1 << 7)
|
||||
# define RADEON_TV_MODULATOR_CNTL1_SET_UP_LEVEL_SHIFT 18
|
||||
# define RADEON_TV_MODULATOR_CNTL1_SET_UP_LEVEL_MASK 0x00007f00
|
||||
# define RADEON_TV_MODULATOR_CNTL1_BLANK_LEVEL_SHIFT 16
|
||||
# define RADEON_TV_MODULATOR_CNTL1_BLANK_LEVEL_MASK 0x007f0000
|
||||
|
||||
#define RADEON_TV_MODULATOR_CNTL2 0x0874
|
||||
# define TV_MODULATOR_CNTL2_U_BURST_LEVEL_MASK 0x1ff
|
||||
# define TV_MODULATOR_CNTL2_V_BURST_LEVEL_MASK 0x1ff
|
||||
# define TV_MODULATOR_CNTL2_V_BURST_LEVEL_SHIFT 16
|
||||
|
||||
#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888
|
||||
# define RADEON_TV_PRE_DAC_MUX_CNTL_Y_RED_EN (1 << 0)
|
||||
# define RADEON_TV_PRE_DAC_MUX_CNTL_C_GRN_EN (1 << 1)
|
||||
# define RADEON_TV_PRE_DAC_MUX_CNTL_CMP_BLU_EN (1 << 2)
|
||||
# define RADEON_TV_PRE_DAC_MUX_CNTL_DAC_DITHER_EN (1 << 3)
|
||||
# define RADEON_TV_PRE_DAC_MUX_CNTL_RED_MX_SHIFT 4
|
||||
# define RADEON_TV_PRE_DAC_MUX_CNTL_GRN_MX_SHIFT 8
|
||||
# define RADEON_TV_PRE_DAC_MUX_CNTL_BLU_MX_SHIFT 12
|
||||
# define RADEON_TV_MUX_FORCE_DAC_DATA 6
|
||||
# define RADEON_TV_PRE_DAC_MUX_CNTL_FORCE_DAC_DATA_SHIFT 16
|
||||
|
||||
#define RADEON_TV_DAC_CNTL 0x088c
|
||||
# define RADEON_TV_DAC_CNTL_NBLANK (1 << 0)
|
||||
# define RADEON_TV_DAC_CNTL_NHOLD (1 << 1)
|
||||
# define RADEON_TV_DAC_CNTL_PEDESTAL (1 << 2)
|
||||
# define RADEON_TV_DAC_CNTL_DETECT (1 << 4)
|
||||
# define RADEON_TV_DAC_CNTL_CMPOUT (1 << 5)
|
||||
# define RADEON_TV_DAC_CNTL_BGSLEEP (1 << 6)
|
||||
# define RADEON_TV_DAC_CNTL_STD_PAL (0 << 8)
|
||||
# define RADEON_TV_DAC_CNTL_STD_NTSC (1 << 8)
|
||||
# define RADEON_TV_DAC_CNTL_STD_PS2 (2 << 8)
|
||||
# define RADEON_TV_DAC_CNTL_STD_RS343 (3 << 8)
|
||||
# define RADEON_TV_DAC_CNTL_BGADJ_SHIFT 16
|
||||
# define RADEON_TV_DAC_CNTL_DACADJ_SHIFT 20
|
||||
# define RADEON_TV_DAC_CNTL_RDACDET (1 << 29)
|
||||
# define RADEON_TV_DAC_CNTL_GDACDET (1 << 30)
|
||||
# define RADEON_TV_DAC_CNTL_BDACDET (1 << 31)
|
||||
|
||||
#define RADEON_TV_UV_ADR 0x08ac
|
||||
|
||||
#define RADEON_TV_PLL_FINE_CNTL 0x20
|
||||
|
||||
#define RADEON_TV_PLL_CNTL 0x21
|
||||
# define RADEON_TV_PLL_CNTL_TV_M0_LO_MASK 0xff
|
||||
# define RADEON_TV_PLL_CNTL_TV_N0_LO_MASK 0x1ff
|
||||
# define RADEON_TV_PLL_CNTL_TV_N0_LO_SHIFT 8
|
||||
# define RADEON_TV_PLL_CNTL_TV_M0_LO_BITS 8
|
||||
# define RADEON_TV_PLL_CNTL_TV_M0_HI_SHIFT 18
|
||||
# define RADEON_TV_PLL_CNTL_TV_N0_LO_BITS 9
|
||||
# define RADEON_TV_PLL_CNTL_TV_N0_HI_SHIFT 21
|
||||
# define RADEON_TV_PLL_CNTL_TV_SLIP_EN (1 << 23)
|
||||
# define RADEON_TV_PLL_CNTL_TV_P_SHIFT 24
|
||||
# define RADEON_TV_PLL_CNTL_TV_DTO_EN (1 << 28)
|
||||
|
||||
# define RADEON_TV_CRT_PLL_CNTL_M0_LO_MASK 0xff
|
||||
# define RADEON_TV_CRT_PLL_CNTL_N0_LO_MASK 0x1ff
|
||||
# define RADEON_TV_CRT_PLL_CNTL_N0_LO_SHIFT 8
|
||||
# define RADEON_TV_CRT_PLL_CNTL_M0_LO_BITS 8
|
||||
# define RADEON_TV_CRT_PLL_CNTL_M0_HI_SHIFT 18
|
||||
# define RADEON_TV_CRT_PLL_CNTL_N0_LO_BITS 9
|
||||
# define RADEON_TV_CRT_PLL_CNTL_N0_HI_SHIFT 21
|
||||
# define RADEON_TV_CRT_PLL_CNTL_CLKBY2 (1 << 25)
|
||||
|
||||
|
||||
#define RADEON_TV_PLL_CNTL1 0x22
|
||||
# define RADEON_TV_PLL_CNTL1_TVPCP_SHIFT 8
|
||||
# define RADEON_TV_PLL_CNTL1_TVPVG_SHIFT 11
|
||||
# define RADEON_TV_PLL_CNTL1_TVPDC_SHIFT 14
|
||||
# define RADEON_TV_PLL_CNTL1_TVCLK_SRC_SEL_CPUCLK (0 << 30)
|
||||
# define RADEON_TV_PLL_CNTL1_TVCLK_SRC_SEL_TVPLLCLK (1 << 30)
|
||||
# define RADEON_TV_PLL_CNTL1_TVPLL_TEST (1 << 31)
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
Copyright (c) 2002/03, Thomas Kurschel
|
||||
|
||||
|
||||
Part of Radeon accelerant
|
||||
|
||||
Utility functions
|
||||
*/
|
||||
|
||||
#ifndef _UTILS_H
|
||||
#define _UTILS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
extern int log2( uint32 x );
|
||||
|
||||
static inline int RoundDiv( int num, int den )
|
||||
{
|
||||
return (num + (den / 2)) / den;
|
||||
}
|
||||
|
||||
static inline int32 RoundDiv64( int64 num, int32 den )
|
||||
{
|
||||
return (num + (den / 2)) / den;
|
||||
}
|
||||
|
||||
static inline int ceilShiftDiv( int num, int shift )
|
||||
{
|
||||
return (num + (1 << shift) - 1) >> shift;
|
||||
}
|
||||
|
||||
static inline int ceilDiv( int num, int den )
|
||||
{
|
||||
return (num + den - 1) / den;
|
||||
}
|
||||
|
||||
// macros for fixed-point calculation
|
||||
#define FIX_SHIFT 32
|
||||
#define FIX_SCALE (1LL << FIX_SHIFT)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -8,4 +8,4 @@
|
||||
*/
|
||||
|
||||
// current version
|
||||
#define RADEON_DRIVER_VERSION "Version: 3.2.7.3"
|
||||
#define RADEON_DRIVER_VERSION "Version: 4.1.0.0"
|
||||
|
||||
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
Copyright (c) 2002, Thomas Kurschel
|
||||
|
||||
|
||||
Part of Radeon driver
|
||||
|
||||
VIP host port registers
|
||||
*/
|
||||
|
||||
#ifndef _VIP_REGS_H
|
||||
#define _VIP_REGS_H
|
||||
|
||||
#define RADEON_VIPH_TIMEOUT_STAT 0xc50
|
||||
# define RADEON_VIPH_TIMEOUT_STAT_VIPH_REG_STAT (1 << 4)
|
||||
# define RADEON_VIPH_TIMEOUT_STAT_VIPH_REG_AK (1 << 4)
|
||||
# define RADEON_VIPH_TIMEOUT_STAT_AK_MASK 0xff
|
||||
# define RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS (1 << 24)
|
||||
|
||||
#define RADEON_VIPH_CONTROL 0xc40
|
||||
# define RADEON_VIPH_CONTROL_VIPH_REG_RDY (1 << 13)
|
||||
# define RADEON_VIPH_CONTROL_VIPH_MAX_WAIT_SHIFT 16
|
||||
# define RADEON_VIPH_CONTROL_VIPH_DMA_MODE (1 << 20)
|
||||
# define RADEON_VIPH_CONTROL_VIPH_EN (1 << 21)
|
||||
|
||||
#define RADEON_VIPH_REG_ADDR 0x80
|
||||
#define RADEON_VIPH_REG_DATA 0x84
|
||||
|
||||
#define RADEON_VIPH_DV_LAT 0xc44
|
||||
# define RADEON_VIPH_DV_LAT_VIPH_DV0_LAT_SHIFT 16
|
||||
# define RADEON_VIPH_DV_LAT_VIPH_DV1_LAT_SHIFT 20
|
||||
# define RADEON_VIPH_DV_LAT_VIPH_DV2_LAT_SHIFT 24
|
||||
# define RADEON_VIPH_DV_LAT_VIPH_DV3_LAT_SHIFT 28
|
||||
|
||||
#define RADEON_VIPH_DMA_CHUNK 0xc48
|
||||
# define RADEON_VIPH_DMA_CHUNK_VIPH_CH0_CHUNK_SHIFT 0
|
||||
# define RADEON_VIPH_DMA_CHUNK_VIPH_CH1_CHUNK_SHIFT 4
|
||||
# define RADEON_VIPH_DMA_CHUNK_VIPH_CH2_CHUNK_SHIFT 6
|
||||
# define RADEON_VIPH_DMA_CHUNK_VIPH_CH3_CHUNK_SHIFT 8
|
||||
|
||||
#define RADEON_VIP_VENDOR_DEVICE_ID 0x0000
|
||||
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user