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fix bitwise check for mode timing polarity

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@41466 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
2011-05-12 22:03:47 +00:00
parent 88bfef92b3
commit 9331e9bb0d
1 changed files with 2 additions and 2 deletions
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src/add-ons/accelerants/radeon_hd/mode.cpp
+2 -2
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@@ -159,7 +159,7 @@ CardModeSet(display_mode *mode)
(displayTiming.h_sync_end - displayTiming.h_sync_start) << 16); (displayTiming.h_sync_end - displayTiming.h_sync_start) << 16);
// set flag for neg. H sync // set flag for neg. H sync
if (displayTiming.flags & ~B_POSITIVE_HSYNC) if (!(displayTiming.flags & B_POSITIVE_HSYNC))
write32(regOffset + D1CRTC_H_SYNC_A_CNTL, 0x01); write32(regOffset + D1CRTC_H_SYNC_A_CNTL, 0x01);
// *** Vertical // *** Vertical
@@ -184,7 +184,7 @@ CardModeSet(display_mode *mode)
(displayTiming.v_sync_end - displayTiming.v_sync_start) << 16); (displayTiming.v_sync_end - displayTiming.v_sync_start) << 16);
// set flag for neg. V sync // set flag for neg. V sync
if (displayTiming.flags & ~B_POSITIVE_VSYNC) if (!(displayTiming.flags & B_POSITIVE_VSYNC))
write32(regOffset + D1CRTC_V_SYNC_A_CNTL, 0x01); write32(regOffset + D1CRTC_V_SYNC_A_CNTL, 0x01);
/* set D1CRTC_HORZ_COUNT_BY2_EN to 0; /* set D1CRTC_HORZ_COUNT_BY2_EN to 0;