programming register PLLSEL as being write-only on singlehead cards. This fixes cursor offset to the left (some 4 pixels) on TNT1 (at least) compared to screen content, along with the missing pixels on the right side of the TVscreen in Desktop modes. Also fixes 'random' extra horizontal offsets on the screen(s). Looks like TVout for BT/CX is now exactly the same as with BeTVOut. (Note BTW that BeTVOut nolonger works correctly alongside this driver because this driver now programmes the encoder itself as well.

git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14350 a95241bf-73f2-0310-859d-f6bbb57e9c96

src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c

@@ -1518,20 +1518,28 @@ static status_t BT_start_tvout(void)
 	/* enable access to primary head */
 	set_crtc_owner(0);
 
-	//fixme: checkout...
-	//CAUTION:
-	//On the TNT1, these memadresses apparantly cannot be read (sometimes)!;
-	//write actions do succeed though... (tested only on ISA bus yet..)
+	/* CAUTION:
+	 * On the TNT1, TV_SETUP and PLLSEL cannot be read (sometimes), but
+	 * write actions do succeed ... (tested on both ISA and PCI bus!) */
 
 	/* setup TVencoder connection */
 	/* b1-0 = %01: encoder type is MASTER;
 	 * b24 = 1: VIP datapos is b0-7 */
 	//fixme if needed: setup completely instead of relying on pre-init by BIOS..
+	//(it seems to work OK on TNT1 although read reg. doesn't seem to work)
 	DACW(TV_SETUP, ((DACR(TV_SETUP) & ~0x00000002) | 0x01000001));
 
 	/* tell GPU to use pixelclock from TVencoder instead of using internal source */
 	/* (nessecary or display will 'shiver' on both TV and VGA.) */
-	DACW(PLLSEL, (DACR(PLLSEL) | 0x00030000));
+	if (si->ps.secondary_head)
+	{
+		DACW(PLLSEL, (DACR(PLLSEL) | 0x00030000));
+	}
+	else
+	{
+		/* confirmed PLLSEL to be a write-only register on TNT1! */
+		DACW(PLLSEL, 0x00030700);
+	}
 
 	/* Set overscan color to 'black' */
 	/* note: