i2p/haiku-beta6
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

* Restored forcing the post2 PLL divisor for display B. This should fix all

Browse Source 
remaining problems introduced with r33633.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@33669 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
2009-10-19 22:34:08 +00:00
parent cad8f65d22
commit 9d3ca457dc
1 changed files with 11 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/add-ons/accelerants/intel_extreme/mode.cpp
+11 -6
View File
@@ -352,7 +352,7 @@ retrieve_current_mode(display_mode& mode, uint32 pllRegister)
hTotalRegister = INTEL_DISPLAY_A_HTOTAL;
vTotalRegister = INTEL_DISPLAY_A_VTOTAL;
hSyncRegister = INTEL_DISPLAY_A_HSYNC;
vSyncRegister = INTEL_DISPLAY_A_VSYNC;
vSyncRegister = INTEL_DISPLAY_A_VSYNC;
imageSizeRegister = INTEL_DISPLAY_A_IMAGE_SIZE;
controlRegister = INTEL_DISPLAY_A_CONTROL;
} else if (pllRegister == INTEL_DISPLAY_B_PLL) {
@@ -362,7 +362,7 @@ retrieve_current_mode(display_mode& mode, uint32 pllRegister)
hTotalRegister = INTEL_DISPLAY_B_HTOTAL;
vTotalRegister = INTEL_DISPLAY_B_VTOTAL;
hSyncRegister = INTEL_DISPLAY_B_HSYNC;
vSyncRegister = INTEL_DISPLAY_B_VSYNC;
vSyncRegister = INTEL_DISPLAY_B_VSYNC;
imageSizeRegister = INTEL_DISPLAY_B_IMAGE_SIZE;
controlRegister = INTEL_DISPLAY_B_CONTROL;
} else {
@@ -385,10 +385,15 @@ retrieve_current_mode(display_mode& mode, uint32 pllRegister)
divisors.post1 = (pll & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK)
>> DISPLAY_PLL_POST1_DIVISOR_SHIFT;
if ((pll & DISPLAY_PLL_DIVIDE_HIGH) != 0)
divisors.post2 = limits.max.post2;
else
divisors.post2 = limits.min.post2;
if (pllRegister == INTEL_DISPLAY_B_PLL) {
// TODO: Fix this? Need to support dual channel LVDS.
divisors.post2 = LVDS_POST2_RATE_SLOW;
} else {
if ((pll & DISPLAY_PLL_DIVIDE_HIGH) != 0)
divisors.post2 = limits.max.post2;
else
divisors.post2 = limits.min.post2;
}
} else {
// 8xx
divisors.post1 = (pll & DISPLAY_PLL_POST1_DIVISOR_MASK)