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* Restored forcing the post2 PLL divisor for display B. This should fix all

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remaining problems introduced with r33633.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@33669 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
2009-10-19 22:34:08 +00:00
parent cad8f65d22
commit 9d3ca457dc
1 changed files with 11 additions and 6 deletions
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src/add-ons/accelerants/intel_extreme/mode.cpp
+9 -4
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@@ -385,10 +385,15 @@ retrieve_current_mode(display_mode& mode, uint32 pllRegister)
divisors.post1 = (pll & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK) divisors.post1 = (pll & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK)
>> DISPLAY_PLL_POST1_DIVISOR_SHIFT; >> DISPLAY_PLL_POST1_DIVISOR_SHIFT;
if ((pll & DISPLAY_PLL_DIVIDE_HIGH) != 0) if (pllRegister == INTEL_DISPLAY_B_PLL) {
divisors.post2 = limits.max.post2; // TODO: Fix this? Need to support dual channel LVDS.
else divisors.post2 = LVDS_POST2_RATE_SLOW;
divisors.post2 = limits.min.post2; } else {
if ((pll & DISPLAY_PLL_DIVIDE_HIGH) != 0)
divisors.post2 = limits.max.post2;
else
divisors.post2 = limits.min.post2;
}
} else { } else {
// 8xx // 8xx
divisors.post1 = (pll & DISPLAY_PLL_POST1_DIVISOR_MASK) divisors.post1 = (pll & DISPLAY_PLL_POST1_DIVISOR_MASK)