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updated SCALED_BLIT to do 15-bit space correctly.

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@16168 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2006-01-31 10:32:15 +00:00
parent fd1528f275
commit 9f6aebed5f
1 changed files with 25 additions and 2 deletions
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src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c
+25 -2
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@@ -1,7 +1,7 @@
/* NV Acceleration functions */ /* NV Acceleration functions */
/* Author: /* Author:
Rudolf Cornelissen 8/2003-12/2005. Rudolf Cornelissen 8/2003-1/2006.
This code was possible thanks to: This code was possible thanks to:
- the Linux XFree86 NV driver, - the Linux XFree86 NV driver,
@@ -1792,7 +1792,6 @@ void SCREEN_TO_SCREEN_BLIT_DMA(engine_token *et, blit_params *list, uint32 count
/* scaled and filtered screen to screen blit - i.e. video playback without overlay */ /* scaled and filtered screen to screen blit - i.e. video playback without overlay */
/* note: source and destination may not overlap. */ /* note: source and destination may not overlap. */
//fixme? checkout NV5 and NV10 version of cmd: faster?? (or is 0x77 a 'autoselect' version?) //fixme? checkout NV5 and NV10 version of cmd: faster?? (or is 0x77 a 'autoselect' version?)
//fixme: test 15-bit depth for correct space (conversion)...
void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT_DMA(engine_token *et, scaled_blit_params *list, uint32 count) void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT_DMA(engine_token *et, scaled_blit_params *list, uint32 count)
{ {
uint32 i = 0; uint32 i = 0;
@@ -1835,6 +1834,16 @@ void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT_DMA(engine_token *et, scaled_blit_par
return; return;
} }
/* modify surface depth settings for 15-bit colorspace so command works as intended */
if (si->dm.space == B_RGB15_LITTLE)
{
/* wait for room in fifo for surface setup cmd if needed */
if (nv_acc_fifofree_dma(2) != B_OK) return;
/* now setup 2D surface (writing 1 32bit word) */
nv_acc_cmd_dma(NV4_SURFACE, NV4_SURFACE_FORMAT, 1);
((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000002; /* Format */
}
/* TNT1 has fixed operation mode 'SRCcopy' while the rest can be programmed: */ /* TNT1 has fixed operation mode 'SRCcopy' while the rest can be programmed: */
if (si->ps.card_type != NV04) if (si->ps.card_type != NV04)
{ {
@@ -1923,6 +1932,20 @@ void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT_DMA(engine_token *et, scaled_blit_par
nv_start_dma(); nv_start_dma();
} }
/* reset surface depth settings so the other engine commands works as intended */
if (si->dm.space == B_RGB15_LITTLE)
{
/* wait for room in fifo for surface setup cmd if needed */
if (nv_acc_fifofree_dma(2) != B_OK) return;
/* now setup 2D surface (writing 1 32bit word) */
nv_acc_cmd_dma(NV4_SURFACE, NV4_SURFACE_FORMAT, 1);
((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000004; /* Format */
/* tell the engine to fetch the commands in the DMA buffer that where not
* executed before. */
nv_start_dma();
}
/* tell 3D add-ons that they should reload their rendering states and surfaces */ /* tell 3D add-ons that they should reload their rendering states and surfaces */
si->engine.threeD.reload = 0xffffffff; si->engine.threeD.reload = 0xffffffff;
} }