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atheroswifi: Sync with FreeBSD 11.1.

Browse Source 
Thanks to khaled and return0e for testing!
This commit is contained in:
Augustin Cavalier
2018-07-11 19:32:38 -04:00
parent 09ddf9b9f3
commit a052f4807f
229 changed files with 31034 additions and 6108 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/add-ons/kernel/drivers/network/wlan/Jamfile
+2 -2
View File
@@ -8,7 +8,6 @@ SubInclude HAIKU_TOP src add-ons kernel drivers network wlan iprowifi2100 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan marvell88w8335 ;
# FreeBSD 9.3 drivers
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan atheroswifi ;
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan broadcom43xx ;
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan marvell88w8363 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan ralinkwifi ;
@@ -16,9 +15,10 @@ SubInclude HAIKU_TOP src add-ons kernel drivers network wlan wavelanwifi ;
# FreeBSD 11.1 drivers
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan aironetwifi ;
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan iprowifi2200 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan atheroswifi ;
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan iprowifi3945 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan iprowifi4965 ;
# FreeBSD 11.2 drivers
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan idualwifi7260 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan iprowifi2200 ;
src/add-ons/kernel/drivers/network/wlan/atheroswifi/Jamfile
+26 -8
View File
@@ -1,14 +1,14 @@
SubDir HAIKU_TOP src add-ons kernel drivers network wlan atheroswifi ;
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ]
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd11_network compat ]
: true ;
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_wlan ] : true ;
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd11_wlan ] : true ;
UsePrivateHeaders net system ;
UsePrivateKernelHeaders ;
SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 _XOPEN_SOURCE ]
-Wno-format
-Wno-unused
SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 _XOPEN_SOURCE ]
-Wno-format
-Wno-unused
-Wno-uninitialized ;
UseHeaders [ FDirName $(SUBDIR) ] : true ;
@@ -20,18 +20,32 @@ Depends atheroswifi : atheroswifi_hal.o ;
Depends atheroswifi : atheroswifi_rate.o ;
KernelAddon atheroswifi :
glue.c
if_ath.c
if_ath_beacon.c
if_ath_btcoex.c
if_ath_btcoex_mci.c
if_ath_descdma.c
if_ath_ioctl.c
if_ath_pci.c
if_ath_led.c
if_ath_lna_div.c
if_ath_keycache.c
if_ath_sysctl.c
if_ath_rx.c
if_ath_rx_edma.c
if_ath_spectral.c
if_ath_tdma.c
if_ath_tx.c
if_ath_tx_edma.c
if_ath_tx_ht.c
glue.c
atheroswifi_hal.o
atheroswifi_rate.o
:
libfreebsd_wlan.a
libfreebsd_network.a
libfreebsd11_wlan.a
libfreebsd11_network.a
;
SEARCH_SOURCE += [ FDirName $(SUBDIR) dev ath ath_hal ] ;
@@ -119,11 +133,15 @@ KernelMergeObject atheroswifi_hal.o :
ar5416_recv.c
ar5416_reset.c
ar5416_xmit.c
ar5416_btcoex.c
ar5416_radar.c
ar5416_spectral.c
# RF backend for 5416 and 9160
ar2133.c
# AR9001 and AR9002 support
ar9285_btcoex.c
ar9130_attach.c
ar9130_eeprom.c
ar9130_phy.c
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ah_osdep.c
+105 -29
View File
@@ -26,7 +26,7 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ah_osdep.c 293111 2016-01-03 17:58:11Z adrian $
*/
#include "opt_ah.h"
@@ -38,12 +38,16 @@
#include <sys/bus.h>
#include <sys/malloc.h>
#include <sys/proc.h>
#include <sys/pcpu.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <machine/stdarg.h>
#include <net/ethernet.h> /* XXX for ether_sprintf */
#include <dev/ath/ath_hal/ah.h>
#include <dev/ath/ath_hal/ah_debug.h>
/*
* WiSoC boards overload the bus tag with information about the
@@ -59,6 +63,23 @@
#define BUSTAG(ah) ((ah)->ah_st)
#endif
/*
* This lock is used to seralise register access for chips which have
* problems w/ SMP CPUs issuing concurrent PCI transactions.
*
* XXX This is a global lock for now; it should be pushed to
* a per-device lock in some platform-independent fashion.
*/
#ifndef __HAIKU__
struct mtx ah_regser_mtx;
MTX_SYSINIT(ah_regser, &ah_regser_mtx, "Atheros register access mutex",
MTX_SPIN);
#else
spinlock ah_regser_mtx = B_SPINLOCK_INITIALIZER;
#define mtx_lock_spin(a) acquire_spinlock(a)
#define mtx_unlock_spin(a) release_spinlock(a)
#endif
extern void ath_hal_printf(struct ath_hal *, const char*, ...)
__printflike(2,3);
extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
@@ -81,9 +102,8 @@ static SYSCTL_NODE(_hw_ath, OID_AUTO, hal, CTLFLAG_RD, 0,
#ifdef AH_DEBUG
int ath_hal_debug = 0;
SYSCTL_INT(_hw_ath_hal, OID_AUTO, debug, CTLFLAG_RW, &ath_hal_debug,
SYSCTL_INT(_hw_ath_hal, OID_AUTO, debug, CTLFLAG_RWTUN, &ath_hal_debug,
0, "Atheros HAL debugging printfs");
TUNABLE_INT("hw.ath.hal.debug", &ath_hal_debug);
#endif /* AH_DEBUG */
static MALLOC_DEFINE(M_ATH_HAL, "ath_hal", "ath hal data");
@@ -123,13 +143,29 @@ ath_hal_ether_sprintf(const u_int8_t *mac)
#ifdef AH_DEBUG
/* This must match the definition in ath_hal/ah_debug.h */
#define HAL_DEBUG_UNMASKABLE 0xf0000000
/*
* XXX This is highly relevant only for the AR5416 and later
* PCI/PCIe NICs. It'll need adjustment for other hardware
* variations.
*/
static int
ath_hal_reg_whilst_asleep(struct ath_hal *ah, uint32_t reg)
{
if (reg >= 0x4000 && reg < 0x5000)
return (1);
if (reg >= 0x6000 && reg < 0x7000)
return (1);
if (reg >= 0x7000 && reg < 0x8000)
return (1);
return (0);
}
void
DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
{
if ((mask == HAL_DEBUG_UNMASKABLE) ||
(ah->ah_config.ah_debug & mask) ||
(ah != NULL && ah->ah_config.ah_debug & mask) ||
(ath_hal_debug & mask)) {
__va_list ap;
va_start(ap, fmt);
@@ -240,22 +276,32 @@ ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
bus_space_tag_t tag = BUSTAG(ah);
bus_space_handle_t h = ah->ah_sh;
#ifdef AH_DEBUG
/* Debug - complain if we haven't fully waken things up */
if (! ath_hal_reg_whilst_asleep(ah, reg) &&
ah->ah_powerMode != HAL_PM_AWAKE) {
ath_hal_printf(ah, "%s: reg=0x%08x, val=0x%08x, pm=%d\n",
__func__, reg, val, ah->ah_powerMode);
}
#endif
if (ath_hal_alq) {
struct ale *ale = ath_hal_alq_get(ah);
if (ale) {
struct athregrec *r = (struct athregrec *) ale->ae_data;
r->threadid = curthread->td_tid;
r->op = OP_WRITE;
r->reg = reg;
r->val = val;
alq_post(ath_hal_alq, ale);
}
}
#if _BYTE_ORDER == _BIG_ENDIAN
if (OS_REG_UNSWAPPED(reg))
bus_space_write_4(tag, h, reg, val);
else
#endif
bus_space_write_stream_4(tag, h, reg, val);
if (ah->ah_config.ah_serialise_reg_war)
mtx_lock_spin(&ah_regser_mtx);
bus_space_write_4(tag, h, reg, val);
OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_WRITE);
if (ah->ah_config.ah_serialise_reg_war)
mtx_unlock_spin(&ah_regser_mtx);
}
u_int32_t
@@ -265,16 +311,26 @@ ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
bus_space_handle_t h = ah->ah_sh;
u_int32_t val;
#if _BYTE_ORDER == _BIG_ENDIAN
if (OS_REG_UNSWAPPED(reg))
val = bus_space_read_4(tag, h, reg);
else
#ifdef AH_DEBUG
/* Debug - complain if we haven't fully waken things up */
if (! ath_hal_reg_whilst_asleep(ah, reg) &&
ah->ah_powerMode != HAL_PM_AWAKE) {
ath_hal_printf(ah, "%s: reg=0x%08x, pm=%d\n",
__func__, reg, ah->ah_powerMode);
}
#endif
val = bus_space_read_stream_4(tag, h, reg);
if (ah->ah_config.ah_serialise_reg_war)
mtx_lock_spin(&ah_regser_mtx);
OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_READ);
val = bus_space_read_4(tag, h, reg);
if (ah->ah_config.ah_serialise_reg_war)
mtx_unlock_spin(&ah_regser_mtx);
if (ath_hal_alq) {
struct ale *ale = ath_hal_alq_get(ah);
if (ale) {
struct athregrec *r = (struct athregrec *) ale->ae_data;
r->threadid = curthread->td_tid;
r->op = OP_READ;
r->reg = reg;
r->val = val;
@@ -291,6 +347,7 @@ OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)
struct ale *ale = ath_hal_alq_get(ah);
if (ale) {
struct athregrec *r = (struct athregrec *) ale->ae_data;
r->threadid = curthread->td_tid;
r->op = OP_MARK;
r->reg = id;
r->val = v;
@@ -298,7 +355,8 @@ OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)
}
}
}
#elif defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
#else /* AH_DEBUG_ALQ */
/*
* Memory-mapped device register read/write. These are here
* as routines when debugging support is enabled and/or when
@@ -316,12 +374,21 @@ ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
bus_space_tag_t tag = BUSTAG(ah);
bus_space_handle_t h = ah->ah_sh;
#if _BYTE_ORDER == _BIG_ENDIAN
if (OS_REG_UNSWAPPED(reg))
bus_space_write_4(tag, h, reg, val);
else
#ifdef AH_DEBUG
/* Debug - complain if we haven't fully waken things up */
if (! ath_hal_reg_whilst_asleep(ah, reg) &&
ah->ah_powerMode != HAL_PM_AWAKE) {
ath_hal_printf(ah, "%s: reg=0x%08x, val=0x%08x, pm=%d\n",
__func__, reg, val, ah->ah_powerMode);
}
#endif
bus_space_write_stream_4(tag, h, reg, val);
if (ah->ah_config.ah_serialise_reg_war)
mtx_lock_spin(&ah_regser_mtx);
bus_space_write_4(tag, h, reg, val);
OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_WRITE);
if (ah->ah_config.ah_serialise_reg_war)
mtx_unlock_spin(&ah_regser_mtx);
}
u_int32_t
@@ -331,15 +398,24 @@ ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
bus_space_handle_t h = ah->ah_sh;
u_int32_t val;
#if _BYTE_ORDER == _BIG_ENDIAN
if (OS_REG_UNSWAPPED(reg))
val = bus_space_read_4(tag, h, reg);
else
#ifdef AH_DEBUG
/* Debug - complain if we haven't fully waken things up */
if (! ath_hal_reg_whilst_asleep(ah, reg) &&
ah->ah_powerMode != HAL_PM_AWAKE) {
ath_hal_printf(ah, "%s: reg=0x%08x, pm=%d\n",
__func__, reg, ah->ah_powerMode);
}
#endif
val = bus_space_read_stream_4(tag, h, reg);
if (ah->ah_config.ah_serialise_reg_war)
mtx_lock_spin(&ah_regser_mtx);
OS_BUS_BARRIER_REG(ah, reg, OS_BUS_BARRIER_READ);
val = bus_space_read_4(tag, h, reg);
if (ah->ah_config.ah_serialise_reg_war)
mtx_unlock_spin(&ah_regser_mtx);
return val;
}
#endif /* AH_DEBUG || AH_REGOPS_FUNC */
#endif /* AH_DEBUG_ALQ */
#ifdef AH_ASSERT
void
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ah_osdep.h
+49 -40
View File
@@ -26,7 +26,7 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ah_osdep.h 293111 2016-01-03 17:58:11Z adrian $
*/
#ifndef _ATH_AH_OSDEP_H_
#define _ATH_AH_OSDEP_H_
@@ -48,6 +48,12 @@ typedef void *HAL_SOFTC;
typedef bus_space_tag_t HAL_BUS_TAG;
typedef bus_space_handle_t HAL_BUS_HANDLE;
/*
* Although the underlying hardware may support 64 bit DMA, the
* current Atheros hardware only supports 32 bit addressing.
*/
typedef uint32_t HAL_DMA_ADDR;
/*
* Linker set writearounds for chip and RF backend registration.
*/
@@ -63,6 +69,7 @@ typedef bus_space_handle_t HAL_BUS_HANDLE;
#define OS_INLINE __inline
#define OS_MEMZERO(_a, _n) bzero((_a), (_n))
#define OS_MEMCPY(_d, _s, _n) memcpy(_d,_s,_n)
#define OS_MEMCMP(_a, _b, _l) memcmp((_a), (_b), (_l))
#define abs(_a) __builtin_abs(_a)
@@ -75,6 +82,10 @@ struct ath_hal;
* domain registers are not byte swapped! Thus, on big-endian
* platforms we have to explicitly byte-swap those registers.
* OS_REG_UNSWAPPED identifies the registers that need special handling.
*
* This is not currently used by the FreeBSD HAL osdep code; the HAL
* currently does not configure hardware byteswapping for register space
* accesses and instead does it through the FreeBSD bus space code.
*/
#if _BYTE_ORDER == _BIG_ENDIAN
#define OS_REG_UNSWAPPED(_reg) \
@@ -85,51 +96,49 @@ struct ath_hal;
#endif /* _BYTE_ORDER */
/*
* Register read/write operations are either handled through
* platform-dependent routines (or when debugging is enabled
* with AH_DEBUG); or they are inline expanded using the macros
* defined below.
* For USB/SDIO support (where access latencies are quite high);
* some write accesses may be buffered and then flushed when
* either a read is done, or an explicit flush is done.
*
* These are simply placeholders for now.
*/
#define OS_REG_WRITE_BUFFER_ENABLE(_ah) \
do { } while (0)
#define OS_REG_WRITE_BUFFER_DISABLE(_ah) \
do { } while (0)
#define OS_REG_WRITE_BUFFER_FLUSH(_ah) \
do { } while (0)
/*
* Read and write barriers. Some platforms require more strongly ordered
* operations and unfortunately most of the HAL is written assuming everything
* is either an x86 or the bus layer will do the barriers for you.
*
* Read barriers should occur before each read, and write barriers
* occur after each write.
*
* Later on for SDIO/USB parts we will methodize this and make them no-ops;
* register accesses will go via USB commands.
*/
#define OS_BUS_BARRIER_READ BUS_SPACE_BARRIER_READ
#define OS_BUS_BARRIER_WRITE BUS_SPACE_BARRIER_WRITE
#define OS_BUS_BARRIER_RW \
(BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
#define OS_BUS_BARRIER(_ah, _start, _len, _t) \
bus_space_barrier((bus_space_tag_t)(_ah)->ah_st, \
(bus_space_handle_t)(_ah)->ah_sh, (_start), (_len), (_t))
#define OS_BUS_BARRIER_REG(_ah, _reg, _t) \
OS_BUS_BARRIER((_ah), (_reg), 4, (_t))
/*
* Register read/write operations are handled through
* platform-dependent routines.
*/
#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
#else
/*
* The hardware registers are native little-endian byte order.
* Big-endian hosts are handled by enabling hardware byte-swap
* of register reads and writes at reset. But the PCI clock
* domain registers are not byte swapped! Thus, on big-endian
* platforms we have to explicitly byte-swap those registers.
* Most of this code is collapsed at compile time because the
* register values are constants.
*/
#if _BYTE_ORDER == _BIG_ENDIAN
#define OS_REG_WRITE(_ah, _reg, _val) do { \
if (OS_REG_UNSWAPPED(_reg)) \
bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \
(bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \
else \
bus_space_write_stream_4((bus_space_tag_t)(_ah)->ah_st, \
(bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \
} while (0)
#define OS_REG_READ(_ah, _reg) \
(OS_REG_UNSWAPPED(_reg) ? \
bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \
(bus_space_handle_t)(_ah)->ah_sh, (_reg)) : \
bus_space_read_stream_4((bus_space_tag_t)(_ah)->ah_st, \
(bus_space_handle_t)(_ah)->ah_sh, (_reg)))
#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
#define OS_REG_WRITE(_ah, _reg, _val) \
bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \
(bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val))
#define OS_REG_READ(_ah, _reg) \
bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \
(bus_space_handle_t)(_ah)->ah_sh, (_reg))
#endif /* _BYTE_ORDER */
#endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */
#ifdef AH_DEBUG_ALQ
extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_dfs/null/dfs_null.c
+80 -13
View File
@@ -26,14 +26,15 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_dfs/null/dfs_null.c 298939 2016-05-02 19:56:48Z pfg $
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
__FBSDID("$FreeBSD: releng/11.1/sys/dev/ath/ath_dfs/null/dfs_null.c 298939 2016-05-02 19:56:48Z pfg $");
/*
* This implements an empty DFS module.
*/
#include "opt_ath.h"
#include "opt_inet.h"
#include "opt_wlan.h"
@@ -42,6 +43,7 @@ __FBSDID("$FreeBSD$");
#include <sys/sysctl.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/malloc.h>
#include <sys/mutex.h>
#include <sys/errno.h>
@@ -52,6 +54,7 @@ __FBSDID("$FreeBSD$");
#include <sys/socket.h>
#include <net/if.h>
#include <net/if_var.h>
#include <net/if_media.h>
#include <net/if_arp.h>
#include <net/ethernet.h> /* XXX for ether_sprintf */
@@ -80,7 +83,7 @@ __FBSDID("$FreeBSD$");
int
ath_dfs_attach(struct ath_softc *sc)
{
return 1;
return (1);
}
/*
@@ -89,32 +92,96 @@ ath_dfs_attach(struct ath_softc *sc)
int
ath_dfs_detach(struct ath_softc *sc)
{
return 1;
return (1);
}
/*
* Enable radar check
* Enable radar check. Return 1 if the driver should
* enable radar PHY errors, or 0 if not.
*/
void
int
ath_dfs_radar_enable(struct ath_softc *sc, struct ieee80211_channel *chan)
{
#if 0
HAL_PHYERR_PARAM pe;
/* Check if the hardware supports radar reporting */
/* XXX TODO: migrate HAL_CAP_RADAR/HAL_CAP_AR to somewhere public! */
if (ath_hal_getcapability(sc->sc_ah,
HAL_CAP_PHYDIAG, 0, NULL) != HAL_OK)
return (0);
/* Check if the current channel is radar-enabled */
if (! IEEE80211_IS_CHAN_DFS(chan))
return;
return (0);
/* Fetch the default parameters */
memset(&pe, '\0', sizeof(pe));
if (! ath_hal_getdfsdefaultthresh(sc->sc_ah, &pe))
return (0);
/* Enable radar PHY error reporting */
sc->sc_dodfs = 1;
/* Tell the hardware to enable radar reporting */
pe.pe_enabled = 1;
/* Flip on extension channel events only if doing HT40 */
if (IEEE80211_IS_CHAN_HT40(chan))
pe.pe_extchannel = 1;
else
pe.pe_extchannel = 0;
ath_hal_enabledfs(sc->sc_ah, &pe);
/*
* Disable strong signal fast diversity - needed for
* AR5212 and similar PHYs for reliable short pulse
* duration.
*/
(void) ath_hal_setcapability(sc->sc_ah, HAL_CAP_DIVERSITY, 2, 0, NULL);
return (1);
#else
return (0);
#endif
}
/*
* Explicity disable radar reporting.
*
* Return 0 if it was disabled, < 0 on error.
*/
int
ath_dfs_radar_disable(struct ath_softc *sc)
{
#if 0
HAL_PHYERR_PARAM pe;
(void) ath_hal_getdfsthresh(sc->sc_ah, &pe);
pe.pe_enabled = 0;
(void) ath_hal_enabledfs(sc->sc_ah, &pe);
return (0);
#else
return (0);
#endif
}
/*
* Process DFS related PHY errors
*
* The mbuf is not "ours" and if we want a copy, we have
* to take a copy. It'll be freed after this function returns.
*/
void
ath_dfs_process_phy_err(struct ath_softc *sc, const char *buf,
ath_dfs_process_phy_err(struct ath_softc *sc, struct mbuf *m,
uint64_t tsf, struct ath_rx_status *rxstat)
{
}
/*
* Process the radar events and determine whether a DFS event has occured.
* Process the radar events and determine whether a DFS event has occurred.
*
* This is designed to run outside of the RX processing path.
* The RX path will call ath_dfs_tasklet_needed() to see whether
@@ -124,7 +191,7 @@ int
ath_dfs_process_radar_event(struct ath_softc *sc,
struct ieee80211_channel *chan)
{
return 0;
return (0);
}
/*
@@ -137,7 +204,7 @@ ath_dfs_process_radar_event(struct ath_softc *sc,
int
ath_dfs_tasklet_needed(struct ath_softc *sc, struct ieee80211_channel *chan)
{
return 0;
return (0);
}
/*
@@ -214,7 +281,7 @@ bad:
free(indata, M_TEMP);
if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
free(outdata, M_TEMP);
return error;
return (error);
}
/*
@@ -224,5 +291,5 @@ int
ath_dfs_get_thresholds(struct ath_softc *sc, HAL_PHYERR_PARAM *param)
{
ath_hal_getdfsthresh(sc->sc_ah, param);
return 1;
return (1);
}
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah.c
+255 -46
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah.c 298939 2016-05-02 19:56:48Z pfg $
*/
#include "opt_ah.h"
@@ -24,6 +24,7 @@
#include "ah_eeprom.h" /* for 5ghz fast clock flag */
#include "ar5416/ar5416reg.h" /* NB: includes ar5212reg.h */
#include "ar9003/ar9300_devid.h"
/* linker set of registered chips */
OS_SET_DECLARE(ah_chips, struct ath_hal_chip);
@@ -54,7 +55,9 @@ ath_hal_probe(uint16_t vendorid, uint16_t devid)
*/
struct ath_hal*
ath_hal_attach(uint16_t devid, HAL_SOFTC sc,
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_STATUS *error)
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
HAL_OPS_CONFIG *ah_config,
HAL_STATUS *error)
{
struct ath_hal_chip * const *pchip;
@@ -65,7 +68,8 @@ ath_hal_attach(uint16_t devid, HAL_SOFTC sc,
/* XXX don't have vendorid, assume atheros one works */
if (chip->probe(ATHEROS_VENDOR_ID, devid) == AH_NULL)
continue;
ah = chip->attach(devid, sc, st, sh, eepromdata, error);
ah = chip->attach(devid, sc, st, sh, eepromdata, ah_config,
error);
if (ah != AH_NULL) {
/* copy back private state to public area */
ah->ah_devid = AH_PRIVATE(ah)->ah_devid;
@@ -87,38 +91,60 @@ ath_hal_mac_name(struct ath_hal *ah)
switch (ah->ah_macVersion) {
case AR_SREV_VERSION_CRETE:
case AR_SREV_VERSION_MAUI_1:
return "5210";
return "AR5210";
case AR_SREV_VERSION_MAUI_2:
case AR_SREV_VERSION_OAHU:
return "5211";
return "AR5211";
case AR_SREV_VERSION_VENICE:
return "5212";
return "AR5212";
case AR_SREV_VERSION_GRIFFIN:
return "2413";
return "AR2413";
case AR_SREV_VERSION_CONDOR:
return "5424";
return "AR5424";
case AR_SREV_VERSION_EAGLE:
return "5413";
return "AR5413";
case AR_SREV_VERSION_COBRA:
return "2415";
case AR_SREV_2425:
return "2425";
case AR_SREV_2417:
return "2417";
return "AR2415";
case AR_SREV_2425: /* Swan */
return "AR2425";
case AR_SREV_2417: /* Nala */
return "AR2417";
case AR_XSREV_VERSION_OWL_PCI:
return "5416";
return "AR5416";
case AR_XSREV_VERSION_OWL_PCIE:
return "5418";
return "AR5418";
case AR_XSREV_VERSION_HOWL:
return "9130";
return "AR9130";
case AR_XSREV_VERSION_SOWL:
return "9160";
return "AR9160";
case AR_XSREV_VERSION_MERLIN:
return "9280";
if (AH_PRIVATE(ah)->ah_ispcie)
return "AR9280";
return "AR9220";
case AR_XSREV_VERSION_KITE:
return "9285";
return "AR9285";
case AR_XSREV_VERSION_KIWI:
return "9287";
if (AH_PRIVATE(ah)->ah_ispcie)
return "AR9287";
return "AR9227";
case AR_SREV_VERSION_AR9380:
if (ah->ah_macRev >= AR_SREV_REVISION_AR9580_10)
return "AR9580";
return "AR9380";
case AR_SREV_VERSION_AR9460:
return "AR9460";
case AR_SREV_VERSION_AR9330:
return "AR9330";
case AR_SREV_VERSION_AR9340:
return "AR9340";
case AR_SREV_VERSION_QCA9550:
return "QCA9550";
case AR_SREV_VERSION_AR9485:
return "AR9485";
case AR_SREV_VERSION_QCA9565:
return "QCA9565";
case AR_SREV_VERSION_QCA9530:
return "QCA9530";
}
return "????";
}
@@ -271,36 +297,42 @@ ath_hal_pkt_txtime(struct ath_hal *ah, const HAL_RATE_TABLE *rates, uint32_t fra
/* 11n frame - extract out the number of spatial streams */
numStreams = HT_RC_2_STREAMS(rc);
KASSERT(numStreams == 1 || numStreams == 2, ("number of spatial streams needs to be 1 or 2: MCS rate 0x%x!", rateix));
KASSERT(numStreams > 0 && numStreams <= 4,
("number of spatial streams needs to be 1..3: MCS rate 0x%x!",
rateix));
return ath_computedur_ht(frameLen, rc, numStreams, isht40, shortPreamble);
}
static const uint16_t ht20_bps[32] = {
26, 52, 78, 104, 156, 208, 234, 260,
52, 104, 156, 208, 312, 416, 468, 520,
78, 156, 234, 312, 468, 624, 702, 780,
104, 208, 312, 416, 624, 832, 936, 1040
};
static const uint16_t ht40_bps[32] = {
54, 108, 162, 216, 324, 432, 486, 540,
108, 216, 324, 432, 648, 864, 972, 1080,
162, 324, 486, 648, 972, 1296, 1458, 1620,
216, 432, 648, 864, 1296, 1728, 1944, 2160
};
/*
* Calculate the transmit duration of an 11n frame.
* This only works for MCS0->MCS15.
*/
uint32_t
ath_computedur_ht(uint32_t frameLen, uint16_t rate, int streams, HAL_BOOL isht40,
HAL_BOOL isShortGI)
ath_computedur_ht(uint32_t frameLen, uint16_t rate, int streams,
HAL_BOOL isht40, HAL_BOOL isShortGI)
{
static const uint16_t ht20_bps[16] = {
26, 52, 78, 104, 156, 208, 234, 260,
52, 104, 156, 208, 312, 416, 468, 520
};
static const uint16_t ht40_bps[16] = {
54, 108, 162, 216, 324, 432, 486, 540,
108, 216, 324, 432, 648, 864, 972, 1080,
};
uint32_t bitsPerSymbol, numBits, numSymbols, txTime;
KASSERT(rate & IEEE80211_RATE_MCS, ("not mcs %d", rate));
KASSERT((rate &~ IEEE80211_RATE_MCS) < 16, ("bad mcs 0x%x", rate));
KASSERT((rate &~ IEEE80211_RATE_MCS) < 31, ("bad mcs 0x%x", rate));
if (isht40)
bitsPerSymbol = ht40_bps[rate & 0xf];
bitsPerSymbol = ht40_bps[rate & 0x1f];
else
bitsPerSymbol = ht20_bps[rate & 0xf];
bitsPerSymbol = ht20_bps[rate & 0x1f];
numBits = OFDM_PLCP_BITS + (frameLen << 3);
numSymbols = howmany(numBits, bitsPerSymbol);
if (isShortGI)
@@ -330,7 +362,7 @@ ath_hal_computetxtime(struct ath_hal *ah,
kbps = rates->info[rateix].rateKbps;
/*
* index can be invalid duting dynamic Turbo transitions.
* index can be invalid during dynamic Turbo transitions.
* XXX
*/
if (kbps == 0)
@@ -394,6 +426,50 @@ ath_hal_computetxtime(struct ath_hal *ah,
return txTime;
}
int
ath_hal_get_curmode(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
/*
* Pick a default mode at bootup. A channel change is inevitable.
*/
if (!chan)
return HAL_MODE_11NG_HT20;
if (IEEE80211_IS_CHAN_TURBO(chan))
return HAL_MODE_TURBO;
/* check for NA_HT before plain A, since IS_CHAN_A includes NA_HT */
if (IEEE80211_IS_CHAN_5GHZ(chan) && IEEE80211_IS_CHAN_HT20(chan))
return HAL_MODE_11NA_HT20;
if (IEEE80211_IS_CHAN_5GHZ(chan) && IEEE80211_IS_CHAN_HT40U(chan))
return HAL_MODE_11NA_HT40PLUS;
if (IEEE80211_IS_CHAN_5GHZ(chan) && IEEE80211_IS_CHAN_HT40D(chan))
return HAL_MODE_11NA_HT40MINUS;
if (IEEE80211_IS_CHAN_A(chan))
return HAL_MODE_11A;
/* check for NG_HT before plain G, since IS_CHAN_G includes NG_HT */
if (IEEE80211_IS_CHAN_2GHZ(chan) && IEEE80211_IS_CHAN_HT20(chan))
return HAL_MODE_11NG_HT20;
if (IEEE80211_IS_CHAN_2GHZ(chan) && IEEE80211_IS_CHAN_HT40U(chan))
return HAL_MODE_11NG_HT40PLUS;
if (IEEE80211_IS_CHAN_2GHZ(chan) && IEEE80211_IS_CHAN_HT40D(chan))
return HAL_MODE_11NG_HT40MINUS;
/*
* XXX For FreeBSD, will this work correctly given the DYN
* chan mode (OFDM+CCK dynamic) ? We have pure-G versions DYN-BG..
*/
if (IEEE80211_IS_CHAN_G(chan))
return HAL_MODE_11G;
if (IEEE80211_IS_CHAN_B(chan))
return HAL_MODE_11B;
HALASSERT(0);
return HAL_MODE_11NG_HT20;
}
typedef enum {
WIRELESS_MODE_11a = 0,
WIRELESS_MODE_TURBO = 1,
@@ -444,6 +520,13 @@ ath_hal_mac_clks(struct ath_hal *ah, u_int usecs)
clks <<= 1;
} else
clks = usecs * CLOCK_RATE[WIRELESS_MODE_11b];
/* Compensate for half/quarter rate */
if (c != AH_NULL && IEEE80211_IS_CHAN_HALF(c))
clks = clks / 2;
else if (c != AH_NULL && IEEE80211_IS_CHAN_QUARTER(c))
clks = clks / 4;
return clks;
}
@@ -615,6 +698,10 @@ ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
return pCap->hal4AddrAggrSupport ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_EXT_CHAN_DFS:
return pCap->halExtChanDfsSupport ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_RX_STBC:
return pCap->halRxStbcSupport ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_TX_STBC:
return pCap->halTxStbcSupport ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_COMBINED_RADAR_RSSI:
return pCap->halUseCombinedRadarRssi ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_AUTO_SLEEP:
@@ -626,13 +713,47 @@ ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
case HAL_CAP_REG_FLAG:
*result = AH_PRIVATE(ah)->ah_currentRDext;
return HAL_OK;
case HAL_CAP_ENHANCED_DMA_SUPPORT:
return pCap->halEnhancedDmaSupport ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_NUM_TXMAPS:
*result = pCap->halNumTxMaps;
return HAL_OK;
case HAL_CAP_TXDESCLEN:
*result = pCap->halTxDescLen;
return HAL_OK;
case HAL_CAP_TXSTATUSLEN:
*result = pCap->halTxStatusLen;
return HAL_OK;
case HAL_CAP_RXSTATUSLEN:
*result = pCap->halRxStatusLen;
return HAL_OK;
case HAL_CAP_RXFIFODEPTH:
switch (capability) {
case HAL_RX_QUEUE_HP:
*result = pCap->halRxHpFifoDepth;
return HAL_OK;
case HAL_RX_QUEUE_LP:
*result = pCap->halRxLpFifoDepth;
return HAL_OK;
default:
return HAL_ENOTSUPP;
}
case HAL_CAP_RXBUFSIZE:
case HAL_CAP_NUM_MR_RETRIES:
*result = pCap->halNumMRRetries;
return HAL_OK;
case HAL_CAP_BT_COEX:
return pCap->halBtCoexSupport ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_SPECTRAL_SCAN:
return pCap->halSpectralScanSupport ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_HT20_SGI:
return pCap->halHTSGI20Support ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_RXTSTAMP_PREC: /* rx desc tstamp precision (bits) */
*result = pCap->halTstampPrecision;
return HAL_OK;
case HAL_CAP_ANT_DIV_COMB: /* AR9285/AR9485 LNA diversity */
return pCap->halAntDivCombSupport ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_ENHANCED_DFS_SUPPORT:
return pCap->halEnhancedDfsSupport ? HAL_OK : HAL_ENOTSUPP;
@@ -659,6 +780,17 @@ ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
return pCap->halHasRxSelfLinkedTail ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_LONG_RXDESC_TSF: /* 32 bit TSF in RX descriptor? */
return pCap->halHasLongRxDescTsf ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_BB_READ_WAR: /* Baseband read WAR */
return pCap->halHasBBReadWar? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_SERIALISE_WAR: /* PCI register serialisation */
return pCap->halSerialiseRegWar ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_MFP: /* Management frame protection setting */
*result = pCap->halMfpSupport;
return HAL_OK;
case HAL_CAP_RX_LNA_MIXING: /* Hardware uses an RX LNA mixer to map 2 antennas to a 1 stream receiver */
return pCap->halRxUsingLnaMixing ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_DO_MYBEACON: /* Hardware supports filtering my-beacons */
return pCap->halRxDoMyBeacon ? HAL_OK : HAL_ENOTSUPP;
default:
return HAL_EINVAL;
}
@@ -721,10 +853,11 @@ ath_hal_getregdump(struct ath_hal *ah, const HAL_REGRANGE *regs,
int i;
for (i = 0; space >= 2*sizeof(uint32_t); i++) {
u_int r = regs[i].start;
u_int e = regs[i].end;
*dp++ = (r<<16) | e;
space -= sizeof(uint32_t);
uint32_t r = regs[i].start;
uint32_t e = regs[i].end;
*dp++ = r;
*dp++ = e;
space -= 2*sizeof(uint32_t);
do {
*dp++ = OS_REG_READ(ah, r);
r += sizeof(uint32_t);
@@ -748,6 +881,7 @@ ath_hal_getdiagstate(struct ath_hal *ah, int request,
const void *args, uint32_t argsize,
void **result, uint32_t *resultsize)
{
switch (request) {
case HAL_DIAG_REVS:
*result = &AH_PRIVATE(ah)->ah_devid;
@@ -805,6 +939,10 @@ ath_hal_getdiagstate(struct ath_hal *ah, int request,
} else
return AH_FALSE;
return AH_TRUE;
case HAL_DIAG_CHANSURVEY:
*result = &AH_PRIVATE(ah)->ah_chansurvey;
*resultsize = sizeof(HAL_CHANNEL_SURVEY);
return AH_TRUE;
}
return AH_FALSE;
}
@@ -940,7 +1078,7 @@ ath_hal_getChanNoise(struct ath_hal *ah, const struct ieee80211_channel *chan)
* populated with values from NOISE_FLOOR[] + ath_hal_getNfAdjust().
*
* The caller must supply ctl/ext NF arrays which are at least
* AH_MIMO_MAX_CHAINS entries long.
* AH_MAX_CHAINS entries long.
*/
int
ath_hal_get_mimo_chan_noise(struct ath_hal *ah,
@@ -956,7 +1094,7 @@ ath_hal_get_mimo_chan_noise(struct ath_hal *ah,
HALDEBUG(ah, HAL_DEBUG_NFCAL,
"%s: invalid channel %u/0x%x; no mapping\n",
__func__, chan->ic_freq, chan->ic_flags);
for (i = 0; i < AH_MIMO_MAX_CHAINS; i++) {
for (i = 0; i < AH_MAX_CHAINS; i++) {
nf_ctl[i] = nf_ext[i] = 0;
}
return 0;
@@ -964,7 +1102,7 @@ ath_hal_get_mimo_chan_noise(struct ath_hal *ah,
/* Return 0 if there's no valid MIMO values (yet) */
if (! (ichan->privFlags & CHANNEL_MIMO_NF_VALID)) {
for (i = 0; i < AH_MIMO_MAX_CHAINS; i++) {
for (i = 0; i < AH_MAX_CHAINS; i++) {
nf_ctl[i] = nf_ext[i] = 0;
}
return 0;
@@ -977,7 +1115,7 @@ ath_hal_get_mimo_chan_noise(struct ath_hal *ah,
* stations which have a very low RSSI, below the
* 'normalised' NF values in NOISE_FLOOR[].
*/
for (i = 0; i < AH_MIMO_MAX_CHAINS; i++) {
for (i = 0; i < AH_MAX_CHAINS; i++) {
nf_ctl[i] = nf_ext[i] = NOISE_FLOOR[mode] +
ath_hal_getNfAdjust(ah, ichan);
}
@@ -996,7 +1134,7 @@ ath_hal_get_mimo_chan_noise(struct ath_hal *ah,
* don't "wrap" when RSSI is less than the "adjusted" NF value.
* ("Adjust" here is via ichan->noiseFloorAdjust.)
*/
for (i = 0; i < AH_MIMO_MAX_CHAINS; i++) {
for (i = 0; i < AH_MAX_CHAINS; i++) {
nf_ctl[i] = ichan->noiseFloorCtl[i] + ath_hal_getNfAdjust(ah, ichan);
nf_ext[i] = ichan->noiseFloorExt[i] + ath_hal_getNfAdjust(ah, ichan);
}
@@ -1258,3 +1396,74 @@ ath_hal_getcca(struct ath_hal *ah)
return 1;
return ((diag & 0x500000) == 0);
}
/*
* This routine is only needed when supporting EEPROM-in-RAM setups
* (eg embedded SoCs and on-board PCI/PCIe devices.)
*/
/* NB: This is in 16 bit words; not bytes */
/* XXX This doesn't belong here! */
#define ATH_DATA_EEPROM_SIZE 2048
HAL_BOOL
ath_hal_EepromDataRead(struct ath_hal *ah, u_int off, uint16_t *data)
{
if (ah->ah_eepromdata == AH_NULL) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: no eeprom data!\n", __func__);
return AH_FALSE;
}
if (off > ATH_DATA_EEPROM_SIZE) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: offset %x > %x\n",
__func__, off, ATH_DATA_EEPROM_SIZE);
return AH_FALSE;
}
(*data) = ah->ah_eepromdata[off];
return AH_TRUE;
}
/*
* Do a 2GHz specific MHz->IEEE based on the hardware
* frequency.
*
* This is the unmapped frequency which is programmed into the hardware.
*/
int
ath_hal_mhz2ieee_2ghz(struct ath_hal *ah, int freq)
{
if (freq == 2484)
return 14;
if (freq < 2484)
return ((int) freq - 2407) / 5;
else
return 15 + ((freq - 2512) / 20);
}
/*
* Clear the current survey data.
*
* This should be done during a channel change.
*/
void
ath_hal_survey_clear(struct ath_hal *ah)
{
OS_MEMZERO(&AH_PRIVATE(ah)->ah_chansurvey,
sizeof(AH_PRIVATE(ah)->ah_chansurvey));
}
/*
* Add a sample to the channel survey.
*/
void
ath_hal_survey_add_sample(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs)
{
HAL_CHANNEL_SURVEY *cs;
cs = &AH_PRIVATE(ah)->ah_chansurvey;
OS_MEMCPY(&cs->samples[cs->cur_sample], hs, sizeof(*hs));
cs->samples[cs->cur_sample].seq_num = cs->cur_seq;
cs->cur_sample = (cs->cur_sample + 1) % CHANNEL_SURVEY_SAMPLE_COUNT;
cs->cur_seq++;
}
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah.h
+547 -32
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah.h 301043 2016-05-31 16:08:06Z adrian $
*/
#ifndef _ATH_AH_H_
@@ -35,7 +35,7 @@
* This is intended to be used by various statistics gathering operations
* (NF, RSSI, EVM).
*/
#define AH_MIMO_MAX_CHAINS 3
#define AH_MAX_CHAINS 3
#define AH_MIMO_MAX_EVM_PILOTS 6
/*
@@ -73,6 +73,7 @@ typedef enum {
HAL_EINPROGRESS = 15, /* Operation incomplete */
HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */
HAL_EEBADCC = 17, /* EEPROM invalid country code */
HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */
} HAL_STATUS;
typedef enum {
@@ -109,7 +110,7 @@ typedef enum {
HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */
HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */
HAL_CAP_11D = 28, /* 11d beacon support for changing cc */
HAL_CAP_PCIE_PS = 29,
HAL_CAP_HT = 30, /* hardware can support HT */
HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */
HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */
@@ -118,7 +119,9 @@ typedef enum {
HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */
HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */
HAL_CAP_RIFS_RX = 39,
HAL_CAP_RIFS_TX = 40,
HAL_CAP_FORCE_PPM = 41,
HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */
HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */
HAL_CAP_DFS_DMN = 44, /* current DFS domain */
@@ -130,25 +133,73 @@ typedef enum {
HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */
HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */
HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */
HAL_CAP_BB_RIFS_HANG = 52,
HAL_CAP_RIFS_RX_ENABLED = 53,
HAL_CAP_BB_DFS_HANG = 54,
HAL_CAP_RX_STBC = 58,
HAL_CAP_TX_STBC = 59,
HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */
HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */
HAL_CAP_DS = 67, /* 2 stream */
HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68,
HAL_CAP_MAC_HANG = 69, /* can MAC hang */
HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */
HAL_CAP_TS = 72, /* 3 stream */
HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */
HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */
HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */
HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */
HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */
HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */
HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */
HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */
HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */
HAL_CAP_SPECTRAL_SCAN = 90, /* Hardware supports spectral scan */
HAL_CAP_BB_PANIC_WATCHDOG = 92,
HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */
HAL_CAP_LDPC = 99,
HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */
HAL_CAP_ANT_DIV_COMB = 105, /* Enable antenna diversity/combining */
HAL_CAP_PHYRESTART_CLR_WAR = 106, /* in some cases, clear phy restart to fix bb hang */
HAL_CAP_ENTERPRISE_MODE = 107, /* Enterprise mode features */
HAL_CAP_LDPCWAR = 108,
HAL_CAP_CHANNEL_SWITCH_TIME_USEC = 109, /* Channel change time, usec */
HAL_CAP_ENABLE_APM = 110, /* APM enabled */
HAL_CAP_PCIE_LCR_EXTSYNC_EN = 111,
HAL_CAP_PCIE_LCR_OFFSET = 112,
HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */
HAL_CAP_MCI = 118,
HAL_CAP_SMARTANTENNA = 119,
HAL_CAP_TRAFFIC_FAST_RECOVER = 120,
HAL_CAP_TX_DIVERSITY = 121,
HAL_CAP_CRDC = 122,
/* The following are private to the FreeBSD HAL (224 onward) */
HAL_CAP_INTMIT = 229, /* interference mitigation */
HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */
HAL_CAP_BB_HANG = 235, /* can baseband hang */
HAL_CAP_MAC_HANG = 236, /* can MAC hang */
HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */
HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */
HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */
HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */
HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */
HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */
HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */
HAL_CAP_ENFORCE_TXOP = 246, /* Enforce TXOP if supported */
HAL_CAP_RX_LNA_MIXING = 247, /* RX hardware uses LNA mixing */
HAL_CAP_DO_MYBEACON = 248, /* Supports HAL_RX_FILTER_MYBEACON */
} HAL_CAPABILITY_TYPE;
/*
@@ -178,10 +229,26 @@ typedef enum {
HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */
HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */
HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */
HAL_TX_QUEUE_CFEND = 6,
HAL_TX_QUEUE_PAPRD = 7,
} HAL_TX_QUEUE;
#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */
/*
* Receive queue types. These are used to tag
* each transmit queue in the hardware and to identify a set
* of transmit queues for operations such as start/stop dma.
*/
typedef enum {
HAL_RX_QUEUE_HP = 0, /* high priority recv queue */
HAL_RX_QUEUE_LP = 1, /* low priority recv queue */
} HAL_RX_QUEUE;
#define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */
#define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth */
/*
* Transmit queue subtype. These map directly to
* WME Access Categories (except for UPSD). Refer
@@ -338,6 +405,7 @@ typedef enum {
HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */
HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */
HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
HAL_RX_FILTER_MYBEACON = 0x00000200, /* Filter beacons other than mine */
HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */
HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */
HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */
@@ -346,7 +414,7 @@ typedef enum {
/* Allow all mcast/bcast frames */
/*
* Magic RX filter flags that aren't targetting hardware bits
* Magic RX filter flags that aren't targeting hardware bits
* but instead the HAL sets individual bits - eg PHYERR will result
* in OFDM/CCK timing error frames being received.
*/
@@ -360,6 +428,23 @@ typedef enum {
HAL_PM_UNDEFINED = 3
} HAL_POWER_MODE;
/*
* Enterprise mode flags
*/
#define AH_ENT_DUAL_BAND_DISABLE 0x00000001
#define AH_ENT_CHAIN2_DISABLE 0x00000002
#define AH_ENT_5MHZ_DISABLE 0x00000004
#define AH_ENT_10MHZ_DISABLE 0x00000008
#define AH_ENT_49GHZ_DISABLE 0x00000010
#define AH_ENT_LOOPBACK_DISABLE 0x00000020
#define AH_ENT_TPC_PERF_DISABLE 0x00000040
#define AH_ENT_MIN_PKT_SIZE_DISABLE 0x00000080
#define AH_ENT_SPECTRAL_PRECISION 0x00000300
#define AH_ENT_SPECTRAL_PRECISION_S 8
#define AH_ENT_RTSCTS_DELIM_WAR 0x00010000
#define AH_FIRST_DESC_NDELIMS 60
/*
* NOTE WELL:
* These are mapped to take advantage of the common locations for many of
@@ -371,18 +456,24 @@ typedef enum {
*/
typedef enum {
HAL_INT_RX = 0x00000001, /* Non-common mapping */
HAL_INT_RXDESC = 0x00000002,
HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */
HAL_INT_RXERR = 0x00000004,
HAL_INT_RXHP = 0x00000001, /* EDMA */
HAL_INT_RXLP = 0x00000002, /* EDMA */
HAL_INT_RXNOFRM = 0x00000008,
HAL_INT_RXEOL = 0x00000010,
HAL_INT_RXORN = 0x00000020,
HAL_INT_TX = 0x00000040, /* Non-common mapping */
HAL_INT_TXDESC = 0x00000080,
HAL_INT_TIM_TIMER= 0x00000100,
HAL_INT_MCI = 0x00000200,
HAL_INT_BBPANIC = 0x00000400,
HAL_INT_TXURN = 0x00000800,
HAL_INT_MIB = 0x00001000,
HAL_INT_RXPHY = 0x00004000,
HAL_INT_RXKCM = 0x00008000,
HAL_INT_SWBA = 0x00010000,
HAL_INT_BRSSI = 0x00020000,
HAL_INT_BMISS = 0x00040000,
HAL_INT_BNR = 0x00100000,
HAL_INT_TIM = 0x00200000, /* Non-common mapping */
@@ -392,6 +483,8 @@ typedef enum {
HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */
HAL_INT_TBTT = 0x08000000, /* Non-common mapping */
/* Atheros ref driver has a generic timer interrupt now..*/
HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */
HAL_INT_CST = 0x10000000, /* Non-common mapping */
HAL_INT_GTT = 0x20000000, /* Non-common mapping */
HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
@@ -414,18 +507,86 @@ typedef enum {
| HAL_INT_RXKCM
| HAL_INT_SWBA
| HAL_INT_BMISS
| HAL_INT_BRSSI
| HAL_INT_BNR
| HAL_INT_GPIO,
} HAL_INT;
/*
* MSI vector assignments
*/
typedef enum {
HAL_GPIO_MUX_OUTPUT = 0,
HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1,
HAL_GPIO_MUX_PCIE_POWER_LED = 2,
HAL_GPIO_MUX_TX_FRAME = 3,
HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4,
HAL_GPIO_MUX_MAC_NETWORK_LED = 5,
HAL_GPIO_MUX_MAC_POWER_LED = 6
HAL_MSIVEC_MISC = 0,
HAL_MSIVEC_TX = 1,
HAL_MSIVEC_RXLP = 2,
HAL_MSIVEC_RXHP = 3,
} HAL_MSIVEC;
typedef enum {
HAL_INT_LINE = 0,
HAL_INT_MSI = 1,
} HAL_INT_TYPE;
/* For interrupt mitigation registers */
typedef enum {
HAL_INT_RX_FIRSTPKT=0,
HAL_INT_RX_LASTPKT,
HAL_INT_TX_FIRSTPKT,
HAL_INT_TX_LASTPKT,
HAL_INT_THRESHOLD
} HAL_INT_MITIGATION;
/* XXX this is duplicate information! */
typedef struct {
u_int32_t cyclecnt_diff; /* delta cycle count */
u_int32_t rxclr_cnt; /* rx clear count */
u_int32_t extrxclr_cnt; /* ext chan rx clear count */
u_int32_t txframecnt_diff; /* delta tx frame count */
u_int32_t rxframecnt_diff; /* delta rx frame count */
u_int32_t listen_time; /* listen time in msec - time for which ch is free */
u_int32_t ofdmphyerr_cnt; /* OFDM err count since last reset */
u_int32_t cckphyerr_cnt; /* CCK err count since last reset */
u_int32_t ofdmphyerrcnt_diff; /* delta OFDM Phy Error Count */
HAL_BOOL valid; /* if the stats are valid*/
} HAL_ANISTATS;
typedef struct {
u_int8_t txctl_offset;
u_int8_t txctl_numwords;
u_int8_t txstatus_offset;
u_int8_t txstatus_numwords;
u_int8_t rxctl_offset;
u_int8_t rxctl_numwords;
u_int8_t rxstatus_offset;
u_int8_t rxstatus_numwords;
u_int8_t macRevision;
} HAL_DESC_INFO;
typedef enum {
HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0,
HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1,
HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2,
HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3,
HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4,
HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5,
HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6,
HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA,
HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK,
HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA,
HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK,
HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX,
HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX,
HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX,
HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX,
HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE,
HAL_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA,
HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL0,
HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL1,
HAL_GPIO_OUTPUT_MUX_AS_SMARTANT_CTRL2,
HAL_GPIO_OUTPUT_MUX_NUM_ENTRIES
} HAL_GPIO_MUX_TYPE;
typedef enum {
@@ -434,6 +595,15 @@ typedef enum {
HAL_GPIO_INTR_DISABLE = 2
} HAL_GPIO_INTR_TYPE;
typedef struct halCounters {
u_int32_t tx_frame_count;
u_int32_t rx_frame_count;
u_int32_t rx_clear_count;
u_int32_t cycle_count;
u_int8_t is_rx_active; // true (1) or false (0)
u_int8_t is_tx_active; // true (1) or false (0)
} HAL_COUNTERS;
typedef enum {
HAL_RFGAIN_INACTIVE = 0,
HAL_RFGAIN_READ_REQUESTED = 1,
@@ -456,6 +626,17 @@ typedef struct {
uint32_t beacons;
} HAL_MIB_STATS;
/*
* These bits represent what's in ah_currentRDext.
*/
typedef enum {
REG_EXT_FCC_MIDBAND = 0,
REG_EXT_JAPAN_MIDBAND = 1,
REG_EXT_FCC_DFS_HT40 = 2,
REG_EXT_JAPAN_NONDFS_HT40 = 3,
REG_EXT_JAPAN_DFS_HT40 = 4
} REG_EXT_BITMAP;
enum {
HAL_MODE_11A = 0x001, /* 11a channels */
HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
@@ -483,7 +664,7 @@ enum {
typedef struct {
int rateCount; /* NB: for proper padding */
uint8_t rateCodeToIndex[144]; /* back mapping */
uint8_t rateCodeToIndex[256]; /* back mapping */
struct {
uint8_t valid; /* valid for rate control use */
uint8_t phy; /* CCK/OFDM/XR */
@@ -497,12 +678,12 @@ typedef struct {
* rate; used for dur. calcs */
uint16_t lpAckDuration; /* long preamble ACK duration */
uint16_t spAckDuration; /* short preamble ACK duration*/
} info[32];
} info[64];
} HAL_RATE_TABLE;
typedef struct {
u_int rs_count; /* number of valid entries */
uint8_t rs_rates[32]; /* rates */
uint8_t rs_rates[64]; /* rates */
} HAL_RATE_SET;
/*
@@ -515,13 +696,16 @@ typedef enum {
typedef struct {
u_int Tries;
u_int Rate;
u_int Rate; /* hardware rate code */
u_int RateIndex; /* rate series table index */
u_int PktDuration;
u_int ChSel;
u_int RateFlags;
#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
#define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */
u_int tx_power_cap; /* in 1/2 dBm units XXX TODO */
} HAL_11N_RATE_SERIES;
typedef enum {
@@ -545,6 +729,11 @@ typedef enum {
HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */
} HAL_HT_RXCLEAR;
typedef enum {
HAL_FREQ_BAND_5GHZ = 0,
HAL_FREQ_BAND_2GHZ = 1,
} HAL_FREQ_BAND;
/*
* Antenna switch control. By default antenna selection
* enables multiple (2) antenna use. To force use of the
@@ -564,15 +753,33 @@ typedef enum {
HAL_M_MONITOR = 8 /* Monitor mode */
} HAL_OPMODE;
typedef enum {
HAL_RESET_NORMAL = 0, /* Do normal reset */
HAL_RESET_BBPANIC = 1, /* Reset because of BB panic */
HAL_RESET_FORCE_COLD = 2, /* Force full reset */
} HAL_RESET_TYPE;
typedef struct {
uint8_t kv_type; /* one of HAL_CIPHER */
uint8_t kv_pad;
uint8_t kv_apsd; /* Mask for APSD enabled ACs */
uint16_t kv_len; /* length in bits */
uint8_t kv_val[16]; /* enough for 128-bit keys */
uint8_t kv_mic[8]; /* TKIP MIC key */
uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */
} HAL_KEYVAL;
/*
* This is the TX descriptor field which marks the key padding requirement.
* The naming is unfortunately unclear.
*/
#define AH_KEYTYPE_MASK 0x0F
typedef enum {
HAL_KEY_TYPE_CLEAR,
HAL_KEY_TYPE_WEP,
HAL_KEY_TYPE_AES,
HAL_KEY_TYPE_TKIP,
} HAL_KEY_TYPE;
typedef enum {
HAL_CIPHER_WEP = 0,
HAL_CIPHER_AES_OCB = 1,
@@ -601,9 +808,16 @@ typedef struct {
uint32_t bs_nexttbtt; /* next beacon in TU */
uint32_t bs_nextdtim; /* next DTIM in TU */
uint32_t bs_intval; /* beacon interval+flags */
/*
* HAL_BEACON_PERIOD, HAL_BEACON_ENA and HAL_BEACON_RESET_TSF
* are all 1:1 correspondances with the pre-11n chip AR_BEACON
* register.
*/
#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
#define HAL_BEACON_PERIOD_TU8 0x0007ffff /* beacon interval, tu/8 */
#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
#define HAL_TSFOOR_THRESHOLD 0x00004240 /* TSF OOR thresh (16k uS) */
uint32_t bs_dtimperiod;
uint16_t bs_cfpperiod; /* CFP period in TU */
uint16_t bs_cfpmaxduration; /* max CFP duration in TU */
@@ -611,6 +825,7 @@ typedef struct {
uint16_t bs_timoffset; /* byte offset to TIM bitmap */
uint16_t bs_bmissthreshold; /* beacon miss threshold */
uint32_t bs_sleepduration; /* max sleep duration */
uint32_t bs_tsfoor_threshold; /* TSF out of range threshold */
} HAL_BEACON_STATE;
/*
@@ -641,6 +856,49 @@ typedef struct {
#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
/*
* This is the ANI state and MIB stats.
*
* It's used by the HAL modules to keep state /and/ by the debug ioctl
* to fetch ANI information.
*/
typedef struct {
uint32_t ast_ani_niup; /* ANI increased noise immunity */
uint32_t ast_ani_nidown; /* ANI decreased noise immunity */
uint32_t ast_ani_spurup; /* ANI increased spur immunity */
uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */
uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */
uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */
uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */
uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */
uint32_t ast_ani_stepup; /* ANI increased first step level */
uint32_t ast_ani_stepdown;/* ANI decreased first step level */
uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */
uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */
uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */
uint32_t ast_ani_lzero; /* ANI listen time forced to zero */
uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */
HAL_MIB_STATS ast_mibstats; /* MIB counter stats */
HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */
} HAL_ANI_STATS;
typedef struct {
uint8_t noiseImmunityLevel;
uint8_t spurImmunityLevel;
uint8_t firstepLevel;
uint8_t ofdmWeakSigDetectOff;
uint8_t cckWeakSigThreshold;
uint32_t listenTime;
/* NB: intentionally ordered so data exported to user space is first */
uint32_t txFrameCount; /* Last txFrameCount */
uint32_t rxFrameCount; /* Last rx Frame count */
uint32_t cycleCount; /* Last cycleCount
(to detect wrap-around) */
uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */
uint32_t cckPhyErrCount; /* CCK err count since last reset */
} HAL_ANI_STATE;
struct ath_desc;
struct ath_tx_status;
struct ath_rx_status;
@@ -658,7 +916,11 @@ typedef struct {
uint32_t tx_busy;
uint32_t rx_busy;
uint32_t chan_busy;
uint32_t ext_chan_busy;
uint32_t cycle_count;
/* XXX TODO */
uint32_t ofdm_phyerr_count;
uint32_t cck_phyerr_count;
} HAL_SURVEY_SAMPLE;
/*
@@ -691,8 +953,11 @@ typedef enum {
HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */
HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */
HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */
HAL_ANI_MRC_CCK = 8,
} HAL_ANI_CMD;
#define HAL_ANI_ALL 0xffffffff
/*
* This is the layout of the ANI INTMIT capability.
*
@@ -731,10 +996,27 @@ typedef struct {
*/
int32_t pe_extchannel; /* Enable DFS on ext channel */
int32_t pe_enabled; /* Whether radar detection is enabled */
int32_t pe_enrelpwr;
int32_t pe_en_relstep_check;
} HAL_PHYERR_PARAM;
#define HAL_PHYERR_PARAM_NOVAL 65535
#define HAL_PHYERR_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */
typedef struct {
u_int16_t ss_fft_period; /* Skip interval for FFT reports */
u_int16_t ss_period; /* Spectral scan period */
u_int16_t ss_count; /* # of reports to return from ss_active */
u_int16_t ss_short_report;/* Set to report ony 1 set of FFT results */
u_int8_t radar_bin_thresh_sel; /* strong signal radar FFT threshold configuration */
u_int16_t ss_spectral_pri; /* are we doing a noise power cal ? */
int8_t ss_nf_cal[AH_MAX_CHAINS*2]; /* nf calibrated values for ctl+ext from eeprom */
int8_t ss_nf_pwr[AH_MAX_CHAINS*2]; /* nf pwr values for ctl+ext from eeprom */
int32_t ss_nf_temp_data; /* temperature data taken during nf scan */
int ss_enabled;
int ss_active;
} HAL_SPECTRAL_PARAM;
#define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF
#define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */
/*
* DFS operating mode flags.
@@ -746,6 +1028,39 @@ typedef enum {
HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */
} HAL_DFS_DOMAIN;
/*
* MFP decryption options for initializing the MAC.
*/
typedef enum {
HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */
HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough */
HAL_MFP_HW_CRYPTO /* hardware decryption enabled. Merlin can do it. */
} HAL_MFP_OPT_T;
/* LNA config supported */
typedef enum {
HAL_ANT_DIV_COMB_LNA1_MINUS_LNA2 = 0,
HAL_ANT_DIV_COMB_LNA2 = 1,
HAL_ANT_DIV_COMB_LNA1 = 2,
HAL_ANT_DIV_COMB_LNA1_PLUS_LNA2 = 3,
} HAL_ANT_DIV_COMB_LNA_CONF;
typedef struct {
u_int8_t main_lna_conf;
u_int8_t alt_lna_conf;
u_int8_t fast_div_bias;
u_int8_t main_gaintb;
u_int8_t alt_gaintb;
u_int8_t antdiv_configgroup;
int8_t lna1_lna2_delta;
} HAL_ANT_COMB_CONFIG;
#define DEFAULT_ANTDIV_CONFIG_GROUP 0x00
#define HAL_ANTDIV_CONFIG_GROUP_1 0x01
#define HAL_ANTDIV_CONFIG_GROUP_2 0x02
#define HAL_ANTDIV_CONFIG_GROUP_3 0x03
/*
* Flag for setting QUIET period
*/
@@ -770,6 +1085,48 @@ struct hal_dfs_event {
};
typedef struct hal_dfs_event HAL_DFS_EVENT;
/*
* Generic Timer domain
*/
typedef enum {
HAL_GEN_TIMER_TSF = 0,
HAL_GEN_TIMER_TSF2,
HAL_GEN_TIMER_TSF_ANY
} HAL_GEN_TIMER_DOMAIN;
/*
* BT Co-existence definitions
*/
#include "ath_hal/ah_btcoex.h"
struct hal_bb_panic_info {
u_int32_t status;
u_int32_t tsf;
u_int32_t phy_panic_wd_ctl1;
u_int32_t phy_panic_wd_ctl2;
u_int32_t phy_gen_ctrl;
u_int32_t rxc_pcnt;
u_int32_t rxf_pcnt;
u_int32_t txf_pcnt;
u_int32_t cycles;
u_int32_t wd;
u_int32_t det;
u_int32_t rdar;
u_int32_t r_odfm;
u_int32_t r_cck;
u_int32_t t_odfm;
u_int32_t t_cck;
u_int32_t agc;
u_int32_t src;
};
/* Serialize Register Access Mode */
typedef enum {
SER_REG_MODE_OFF = 0,
SER_REG_MODE_ON = 1,
SER_REG_MODE_AUTO = 2,
} SER_REG_MODE;
typedef struct
{
int ah_debug; /* only used if AH_DEBUG is defined */
@@ -779,6 +1136,51 @@ typedef struct
int ah_dma_beacon_response_time;/* in TU's */
int ah_sw_beacon_response_time; /* in TU's */
int ah_additional_swba_backoff; /* in TU's */
int ah_force_full_reset; /* force full chip reset rather then warm reset */
int ah_serialise_reg_war; /* force serialisation of register IO */
/* XXX these don't belong here, they're just for the ar9300 HAL port effort */
int ath_hal_desc_tpc; /* Per-packet TPC */
int ath_hal_sta_update_tx_pwr_enable; /* GreenTX */
int ath_hal_sta_update_tx_pwr_enable_S1; /* GreenTX */
int ath_hal_sta_update_tx_pwr_enable_S2; /* GreenTX */
int ath_hal_sta_update_tx_pwr_enable_S3; /* GreenTX */
/* I'm not sure what the default values for these should be */
int ath_hal_pll_pwr_save;
int ath_hal_pcie_power_save_enable;
int ath_hal_intr_mitigation_rx;
int ath_hal_intr_mitigation_tx;
int ath_hal_pcie_clock_req;
#define AR_PCIE_PLL_PWRSAVE_CONTROL (1<<0)
#define AR_PCIE_PLL_PWRSAVE_ON_D3 (1<<1)
#define AR_PCIE_PLL_PWRSAVE_ON_D0 (1<<2)
int ath_hal_pcie_waen;
int ath_hal_pcie_ser_des_write;
/* these are important for correct AR9300 behaviour */
int ath_hal_ht_enable; /* needs to be enabled for AR9300 HT */
int ath_hal_diversity_control;
int ath_hal_antenna_switch_swap;
int ath_hal_ext_lna_ctl_gpio;
int ath_hal_spur_mode;
int ath_hal_6mb_ack; /* should set this to 1 for 11a/11na? */
int ath_hal_enable_msi; /* enable MSI interrupts (needed?) */
int ath_hal_beacon_filter_interval; /* ok to be 0 for now? */
/* For now, set this to 0 - net80211 needs to know about hardware MFP support */
int ath_hal_mfp_support;
int ath_hal_enable_ani; /* should set this.. */
int ath_hal_cwm_ignore_ext_cca;
int ath_hal_show_bb_panic;
int ath_hal_ant_ctrl_comm2g_switch_enable;
int ath_hal_ext_atten_margin_cfg;
int ath_hal_min_gainidx;
int ath_hal_war70c;
uint32_t ath_hal_mci_config;
} HAL_OPS_CONFIG;
/*
@@ -809,6 +1211,12 @@ struct ath_hal {
uint16_t *ah_eepromdata; /* eeprom buffer, if needed */
uint32_t ah_intrstate[8]; /* last int state */
uint32_t ah_syncstate; /* last sync intr state */
/* Current powerstate from HAL calls */
HAL_POWER_MODE ah_powerMode;
HAL_OPS_CONFIG ah_config;
const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
u_int mode);
@@ -817,10 +1225,13 @@ struct ath_hal {
/* Reset functions */
HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE,
struct ieee80211_channel *,
HAL_BOOL bChannelChange, HAL_STATUS *status);
HAL_BOOL bChannelChange,
HAL_RESET_TYPE resetType,
HAL_STATUS *status);
HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *);
HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *);
void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore);
void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore,
HAL_BOOL power_off);
void __ahdecl(*ah_disablePCIE)(struct ath_hal *);
void __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*,
@@ -865,7 +1276,8 @@ struct ath_hal {
u_int txRate2, u_int txTries2,
u_int txRate3, u_int txTries3);
HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *,
u_int segLen, HAL_BOOL firstSeg,
HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList,
u_int descId, u_int qcuId, HAL_BOOL firstSeg,
HAL_BOOL lastSeg, const struct ath_desc *);
HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *,
struct ath_desc *, struct ath_tx_status *);
@@ -873,10 +1285,20 @@ struct ath_hal {
void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*);
HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *,
const struct ath_desc *ds, int *rates, int *tries);
void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds,
uint32_t link);
void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds,
uint32_t *link);
void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds,
uint32_t **linkptr);
void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *,
void *ts_start, uint32_t ts_paddr_start,
uint16_t size);
void __ahdecl(*ah_getTxRawTxDesc)(struct ath_hal *, u_int32_t *);
/* Receive Functions */
uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*);
void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp);
uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE);
void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE);
void __ahdecl(*ah_enableReceive)(struct ath_hal*);
HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
void __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
@@ -902,9 +1324,6 @@ struct ath_hal {
const struct ieee80211_channel *);
void __ahdecl(*ah_procMibEvent)(struct ath_hal *,
const HAL_NODE_STATS *);
void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *,
struct ath_rx_status *,
unsigned long, int);
/* Misc Functions */
HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *,
@@ -934,6 +1353,7 @@ struct ath_hal {
void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t);
uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
void __ahdecl(*ah_setTsf64)(struct ath_hal *, uint64_t);
void __ahdecl(*ah_resetTsf)(struct ath_hal*);
HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*);
void __ahdecl(*ah_updateMibCounters)(struct ath_hal*,
@@ -959,17 +1379,32 @@ struct ath_hal {
HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period,
uint32_t duration, uint32_t nextStart,
HAL_QUIET_FLAG flag);
void __ahdecl(*ah_setChainMasks)(struct ath_hal *,
uint32_t, uint32_t);
/* DFS functions */
void __ahdecl(*ah_enableDfs)(struct ath_hal *ah,
HAL_PHYERR_PARAM *pe);
void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah,
HAL_PHYERR_PARAM *pe);
HAL_BOOL __ahdecl(*ah_getDfsDefaultThresh)(struct ath_hal *ah,
HAL_PHYERR_PARAM *pe);
HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah,
struct ath_rx_status *rxs, uint64_t fulltsf,
const char *buf, HAL_DFS_EVENT *event);
HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah);
/* Spectral Scan functions */
void __ahdecl(*ah_spectralConfigure)(struct ath_hal *ah,
HAL_SPECTRAL_PARAM *sp);
void __ahdecl(*ah_spectralGetConfig)(struct ath_hal *ah,
HAL_SPECTRAL_PARAM *sp);
void __ahdecl(*ah_spectralStart)(struct ath_hal *);
void __ahdecl(*ah_spectralStop)(struct ath_hal *);
HAL_BOOL __ahdecl(*ah_spectralIsEnabled)(struct ath_hal *);
HAL_BOOL __ahdecl(*ah_spectralIsActive)(struct ath_hal *);
/* XXX getNfPri() and getNfExt() */
/* Key Cache Functions */
uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*);
HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t);
@@ -1001,9 +1436,12 @@ struct ath_hal {
/* 802.11n Functions */
HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *,
struct ath_desc *, u_int, u_int, HAL_PKT_TYPE,
u_int, HAL_CIPHER, uint8_t, u_int, HAL_BOOL,
HAL_BOOL);
struct ath_desc *,
HAL_DMA_ADDR *bufAddrList,
uint32_t *segLenList,
u_int, u_int, HAL_PKT_TYPE,
u_int, HAL_CIPHER, uint8_t, HAL_BOOL,
HAL_BOOL, HAL_BOOL);
HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *,
struct ath_desc *, u_int, u_int, u_int,
u_int, u_int, u_int, u_int, u_int);
@@ -1012,12 +1450,32 @@ struct ath_hal {
void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *,
struct ath_desc *, u_int, u_int,
HAL_11N_RATE_SERIES [], u_int, u_int);
/*
* The next 4 (set11ntxdesc -> set11naggrlast) are specific
* to the EDMA HAL. Descriptors are chained together by
* using filltxdesc (not ChainTxDesc) and then setting the
* aggregate flags appropriately using first/middle/last.
*/
void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *,
void *, u_int, HAL_PKT_TYPE, u_int, u_int,
u_int);
void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *,
struct ath_desc *, u_int, u_int);
void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *,
struct ath_desc *, u_int);
void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *,
struct ath_desc *);
void __ahdecl(*ah_clr11nAggr)(struct ath_hal *,
struct ath_desc *);
void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *,
struct ath_desc *, u_int);
void __ahdecl(*ah_set11nVirtMoreFrag)(struct ath_hal *,
struct ath_desc *, u_int);
HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *,
HAL_SURVEY_SAMPLE *);
uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *);
void __ahdecl(*ah_set11nMac2040)(struct ath_hal *,
HAL_HT_MACMODE);
@@ -1030,6 +1488,40 @@ struct ath_hal {
HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*);
HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
/* Bluetooth Coexistence functions */
void __ahdecl(*ah_btCoexSetInfo)(struct ath_hal *,
HAL_BT_COEX_INFO *);
void __ahdecl(*ah_btCoexSetConfig)(struct ath_hal *,
HAL_BT_COEX_CONFIG *);
void __ahdecl(*ah_btCoexSetQcuThresh)(struct ath_hal *,
int);
void __ahdecl(*ah_btCoexSetWeights)(struct ath_hal *,
uint32_t);
void __ahdecl(*ah_btCoexSetBmissThresh)(struct ath_hal *,
uint32_t);
void __ahdecl(*ah_btCoexSetParameter)(struct ath_hal *,
uint32_t, uint32_t);
void __ahdecl(*ah_btCoexDisable)(struct ath_hal *);
int __ahdecl(*ah_btCoexEnable)(struct ath_hal *);
/* Bluetooth MCI methods */
void __ahdecl(*ah_btMciSetup)(struct ath_hal *,
uint32_t, void *, uint16_t, uint32_t);
HAL_BOOL __ahdecl(*ah_btMciSendMessage)(struct ath_hal *,
uint8_t, uint32_t, uint32_t *, uint8_t,
HAL_BOOL, HAL_BOOL);
uint32_t __ahdecl(*ah_btMciGetInterrupt)(struct ath_hal *,
uint32_t *, uint32_t *);
uint32_t __ahdecl(*ah_btMciState)(struct ath_hal *,
uint32_t, uint32_t *);
void __ahdecl(*ah_btMciDetach)(struct ath_hal *);
/* LNA diversity configuration */
void __ahdecl(*ah_divLnaConfGet)(struct ath_hal *,
HAL_ANT_COMB_CONFIG *);
void __ahdecl(*ah_divLnaConfSet)(struct ath_hal *,
HAL_ANT_COMB_CONFIG *);
};
/*
@@ -1053,7 +1545,8 @@ extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid);
* be returned if the status parameter is non-zero.
*/
extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC,
HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status);
HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata,
HAL_OPS_CONFIG *ah_config, HAL_STATUS* status);
extern const char *ath_hal_mac_name(struct ath_hal *);
extern const char *ath_hal_rf_name(struct ath_hal *);
@@ -1121,6 +1614,12 @@ extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah);
*/
extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*);
/*
* Get the HAL wireless mode for the given channel.
*/
extern int ath_hal_get_curmode(struct ath_hal *ah,
const struct ieee80211_channel *chan);
/*
* Calculate the packet TX time for a legacy or 11n frame
*/
@@ -1156,4 +1655,20 @@ void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena);
*/
int __ahdecl ath_hal_getcca(struct ath_hal *ah);
/*
* Read EEPROM data from ah_eepromdata
*/
HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah,
u_int off, uint16_t *data);
/*
* For now, simply pass through MFP frames.
*/
static inline u_int32_t
ath_hal_get_mfp_qos(struct ath_hal *ah)
{
//return AH_PRIVATE(ah)->ah_mfp_qos;
return HAL_MFP_QOSDATA;
}
#endif /* _ATH_AH_H_ */
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_btcoex.h
+523
View File
@@ -0,0 +1,523 @@
/*
* Copyright (c) 2014 Qualcomm Atheros, Inc.
* All Rights Reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_btcoex.h 301303 2016-06-04 07:28:09Z adrian $
*/
#ifndef __ATH_HAL_BTCOEX_H__
#define __ATH_HAL_BTCOEX_H__
/*
* General BT coexistence definitions.
*/
typedef enum {
HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */
HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */
HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */
HAL_MAX_BT_MODULES
} HAL_BT_MODULE;
typedef struct {
HAL_BT_MODULE bt_module;
u_int8_t bt_coex_config;
u_int8_t bt_gpio_bt_active;
u_int8_t bt_gpio_bt_priority;
u_int8_t bt_gpio_wlan_active;
u_int8_t bt_active_polarity;
HAL_BOOL bt_single_ant;
u_int8_t bt_isolation;
} HAL_BT_COEX_INFO;
typedef enum {
HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */
HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */
HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */
HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */
} HAL_BT_COEX_MODE;
typedef enum {
HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */
HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */
HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */
HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */
HAL_BT_COEX_CFG_3WIRE, /* 3-wire */
HAL_BT_COEX_CFG_MCI /* MCI */
} HAL_BT_COEX_CFG;
typedef enum {
HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */
HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */
HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */
HAL_BT_COEX_MCI_MAX_TX_PWR, /* Set max tx power for concurrent tx */
HAL_BT_COEX_MCI_FTP_STOMP_RX, /* Use a different weight for stomp low */
} HAL_BT_COEX_SET_PARAMETER;
/*
* MCI specific coexistence definitions.
*/
#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001
#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002
/* Check Rx Diversity is allowed */
#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004
/* Check Diversity is on or off */
#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008
#define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b
/* main: LNA1, alt: LNA2 */
#define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09
#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04
#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09
#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02
#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06
#define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30
#define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666
#define HAL_BT_COEX_HELIUS_CHAINMASK 0x02
#define HAL_BT_COEX_LOW_ACK_POWER 0x0
#define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f
typedef enum {
HAL_BT_COEX_NO_STOMP = 0,
HAL_BT_COEX_STOMP_ALL,
HAL_BT_COEX_STOMP_LOW,
HAL_BT_COEX_STOMP_NONE,
HAL_BT_COEX_STOMP_ALL_FORCE,
HAL_BT_COEX_STOMP_LOW_FORCE,
HAL_BT_COEX_STOMP_AUDIO,
} HAL_BT_COEX_STOMP_TYPE;
typedef struct {
/* extend rx_clear after tx/rx to protect the burst (in usec). */
u_int8_t bt_time_extend;
/*
* extend rx_clear as long as txsm is
* transmitting or waiting for ack.
*/
HAL_BOOL bt_txstate_extend;
/*
* extend rx_clear so that when tx_frame
* is asserted, rx_clear will drop.
*/
HAL_BOOL bt_txframe_extend;
/*
* coexistence mode
*/
HAL_BT_COEX_MODE bt_mode;
/*
* treat BT high priority traffic as
* a quiet collision
*/
HAL_BOOL bt_quiet_collision;
/*
* invert rx_clear as WLAN_ACTIVE
*/
HAL_BOOL bt_rxclear_polarity;
/*
* slotted mode only. indicate the time in usec
* from the rising edge of BT_ACTIVE to the time
* BT_PRIORITY can be sampled to indicate priority.
*/
u_int8_t bt_priority_time;
/*
* slotted mode only. indicate the time in usec
* from the rising edge of BT_ACTIVE to the time
* BT_PRIORITY can be sampled to indicate tx/rx and
* BT_FREQ is sampled.
*/
u_int8_t bt_first_slot_time;
/*
* slotted mode only. rx_clear and bt_ant decision
* will be held the entire time that BT_ACTIVE is asserted,
* otherwise the decision is made before every slot boundary.
*/
HAL_BOOL bt_hold_rxclear;
} HAL_BT_COEX_CONFIG;
#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001
#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002
#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 /* Check Rx Diversity is allowed */
#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 /* Check Diversity is on or off */
#define HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR 0x00000010
#define HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX 0x00000020
#define HAL_MCI_FLAG_DISABLE_TIMESTAMP 0x00000001 /* Disable time stamp */
typedef enum mci_message_header {
MCI_LNA_CTRL = 0x10, /* len = 0 */
MCI_CONT_NACK = 0x20, /* len = 0 */
MCI_CONT_INFO = 0x30, /* len = 4 */
MCI_CONT_RST = 0x40, /* len = 0 */
MCI_SCHD_INFO = 0x50, /* len = 16 */
MCI_CPU_INT = 0x60, /* len = 4 */
MCI_SYS_WAKING = 0x70, /* len = 0 */
MCI_GPM = 0x80, /* len = 16 */
MCI_LNA_INFO = 0x90, /* len = 1 */
MCI_LNA_STATE = 0x94,
MCI_LNA_TAKE = 0x98,
MCI_LNA_TRANS = 0x9c,
MCI_SYS_SLEEPING = 0xa0, /* len = 0 */
MCI_REQ_WAKE = 0xc0, /* len = 0 */
MCI_DEBUG_16 = 0xfe, /* len = 2 */
MCI_REMOTE_RESET = 0xff /* len = 16 */
} MCI_MESSAGE_HEADER;
/* Default remote BT device MCI COEX version */
#define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT 3
#define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0
/* Local WLAN MCI COEX version */
#define MCI_GPM_COEX_MAJOR_VERSION_WLAN 3
#define MCI_GPM_COEX_MINOR_VERSION_WLAN 0
typedef enum mci_gpm_subtype {
MCI_GPM_BT_CAL_REQ = 0,
MCI_GPM_BT_CAL_GRANT = 1,
MCI_GPM_BT_CAL_DONE = 2,
MCI_GPM_WLAN_CAL_REQ = 3,
MCI_GPM_WLAN_CAL_GRANT = 4,
MCI_GPM_WLAN_CAL_DONE = 5,
MCI_GPM_COEX_AGENT = 0x0C,
MCI_GPM_RSVD_PATTERN = 0xFE,
MCI_GPM_RSVD_PATTERN32 = 0xFEFEFEFE,
MCI_GPM_BT_DEBUG = 0xFF
} MCI_GPM_SUBTYPE_T;
typedef enum mci_gpm_coex_opcode {
MCI_GPM_COEX_VERSION_QUERY = 0,
MCI_GPM_COEX_VERSION_RESPONSE = 1,
MCI_GPM_COEX_STATUS_QUERY = 2,
MCI_GPM_COEX_HALT_BT_GPM = 3,
MCI_GPM_COEX_WLAN_CHANNELS = 4,
MCI_GPM_COEX_BT_PROFILE_INFO = 5,
MCI_GPM_COEX_BT_STATUS_UPDATE = 6,
MCI_GPM_COEX_BT_UPDATE_FLAGS = 7
} MCI_GPM_COEX_OPCODE_T;
typedef enum mci_gpm_coex_query_type {
/* WLAN information */
MCI_GPM_COEX_QUERY_WLAN_ALL_INFO = 0x01,
/* BT information */
MCI_GPM_COEX_QUERY_BT_ALL_INFO = 0x01,
MCI_GPM_COEX_QUERY_BT_TOPOLOGY = 0x02,
MCI_GPM_COEX_QUERY_BT_DEBUG = 0x04
} MCI_GPM_COEX_QUERY_TYPE_T;
typedef enum mci_gpm_coex_halt_bt_gpm {
MCI_GPM_COEX_BT_GPM_UNHALT = 0,
MCI_GPM_COEX_BT_GPM_HALT = 1
} MCI_GPM_COEX_HALT_BT_GPM_T;
typedef enum mci_gpm_coex_profile_type {
MCI_GPM_COEX_PROFILE_UNKNOWN = 0,
MCI_GPM_COEX_PROFILE_RFCOMM = 1,
MCI_GPM_COEX_PROFILE_A2DP = 2,
MCI_GPM_COEX_PROFILE_HID = 3,
MCI_GPM_COEX_PROFILE_BNEP = 4,
MCI_GPM_COEX_PROFILE_VOICE = 5,
MCI_GPM_COEX_PROFILE_MAX
} MCI_GPM_COEX_PROFILE_TYPE_T;
typedef enum mci_gpm_coex_profile_state {
MCI_GPM_COEX_PROFILE_STATE_END = 0,
MCI_GPM_COEX_PROFILE_STATE_START = 1
} MCI_GPM_COEX_PROFILE_STATE_T;
typedef enum mci_gpm_coex_profile_role {
MCI_GPM_COEX_PROFILE_SLAVE = 0,
MCI_GPM_COEX_PROFILE_MASTER = 1
} MCI_GPM_COEX_PROFILE_ROLE_T;
typedef enum mci_gpm_coex_bt_status_type {
MCI_GPM_COEX_BT_NONLINK_STATUS = 0,
MCI_GPM_COEX_BT_LINK_STATUS = 1
} MCI_GPM_COEX_BT_STATUS_TYPE_T;
typedef enum mci_gpm_coex_bt_status_state {
MCI_GPM_COEX_BT_NORMAL_STATUS = 0,
MCI_GPM_COEX_BT_CRITICAL_STATUS = 1
} MCI_GPM_COEX_BT_STATUS_STATE_T;
#define MCI_GPM_INVALID_PROFILE_HANDLE 0xff
typedef enum mci_gpm_coex_bt_updata_flags_op {
MCI_GPM_COEX_BT_FLAGS_READ = 0x00,
MCI_GPM_COEX_BT_FLAGS_SET = 0x01,
MCI_GPM_COEX_BT_FLAGS_CLEAR = 0x02
} MCI_GPM_COEX_BT_FLAGS_OP_T;
/* MCI GPM/Coex opcode/type definitions */
enum {
MCI_GPM_COEX_W_GPM_PAYLOAD = 1,
MCI_GPM_COEX_B_GPM_TYPE = 4,
MCI_GPM_COEX_B_GPM_OPCODE = 5,
/* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */
MCI_GPM_WLAN_CAL_W_SEQUENCE = 2,
/* MCI_GPM_COEX_VERSION_QUERY */
/* MCI_GPM_COEX_VERSION_RESPONSE */
MCI_GPM_COEX_B_MAJOR_VERSION = 6,
MCI_GPM_COEX_B_MINOR_VERSION = 7,
/* MCI_GPM_COEX_STATUS_QUERY */
MCI_GPM_COEX_B_BT_BITMAP = 6,
MCI_GPM_COEX_B_WLAN_BITMAP = 7,
/* MCI_GPM_COEX_HALT_BT_GPM */
MCI_GPM_COEX_B_HALT_STATE = 6,
/* MCI_GPM_COEX_WLAN_CHANNELS */
MCI_GPM_COEX_B_CHANNEL_MAP = 6,
/* MCI_GPM_COEX_BT_PROFILE_INFO */
MCI_GPM_COEX_B_PROFILE_TYPE = 6,
MCI_GPM_COEX_B_PROFILE_LINKID = 7,
MCI_GPM_COEX_B_PROFILE_STATE = 8,
MCI_GPM_COEX_B_PROFILE_ROLE = 9,
MCI_GPM_COEX_B_PROFILE_RATE = 10,
MCI_GPM_COEX_B_PROFILE_VOTYPE = 11,
MCI_GPM_COEX_H_PROFILE_T = 12,
MCI_GPM_COEX_B_PROFILE_W = 14,
MCI_GPM_COEX_B_PROFILE_A = 15,
/* MCI_GPM_COEX_BT_STATUS_UPDATE */
MCI_GPM_COEX_B_STATUS_TYPE = 6,
MCI_GPM_COEX_B_STATUS_LINKID = 7,
MCI_GPM_COEX_B_STATUS_STATE = 8,
/* MCI_GPM_COEX_BT_UPDATE_FLAGS */
MCI_GPM_COEX_B_BT_FLAGS_OP = 10,
MCI_GPM_COEX_W_BT_FLAGS = 6
};
#define MCI_GPM_RECYCLE(_p_gpm) \
{ \
*(((u_int32_t *)(_p_gpm)) + MCI_GPM_COEX_W_GPM_PAYLOAD) = MCI_GPM_RSVD_PATTERN32; \
}
#define MCI_GPM_TYPE(_p_gpm) \
(*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff)
#define MCI_GPM_OPCODE(_p_gpm) \
(*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff)
#define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) \
{ \
*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff; \
}
#define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) \
{ \
*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \
*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff; \
}
#define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE)
#define MCI_NUM_BT_CHANNELS 79
#define MCI_GPM_SET_CHANNEL_BIT(_p_gpm, _bt_chan) \
{ \
if (_bt_chan < MCI_NUM_BT_CHANNELS) { \
*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \
(_bt_chan / 8)) |= 1 << (_bt_chan & 7); \
} \
}
#define MCI_GPM_CLR_CHANNEL_BIT(_p_gpm, _bt_chan) \
{ \
if (_bt_chan < MCI_NUM_BT_CHANNELS) { \
*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \
(_bt_chan / 8)) &= ~(1 << (_bt_chan & 7)); \
} \
}
#define HAL_MCI_INTERRUPT_SW_MSG_DONE 0x00000001
#define HAL_MCI_INTERRUPT_CPU_INT_MSG 0x00000002
#define HAL_MCI_INTERRUPT_RX_CHKSUM_FAIL 0x00000004
#define HAL_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008
#define HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010
#define HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020
#define HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080
#define HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100
#define HAL_MCI_INTERRUPT_RX_MSG 0x00000200
#define HAL_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400
#define HAL_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000
#define HAL_MCI_INTERRUPT_MSG_FAIL_MASK ( HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL | \
HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL | \
HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL | \
HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL )
#define HAL_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001
#define HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002
#define HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004
#define HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008
#define HAL_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010
#define HAL_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020
#define HAL_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040
#define HAL_MCI_INTERRUPT_RX_MSG_GPM 0x00000100
#define HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200
#define HAL_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400
#define HAL_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800
#define HAL_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000
#define HAL_MCI_INTERRUPT_RX_MSG_MONITOR (HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \
HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO | \
HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK | \
HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO | \
HAL_MCI_INTERRUPT_RX_MSG_CONT_RST)
typedef enum mci_bt_state {
MCI_BT_SLEEP,
MCI_BT_AWAKE,
MCI_BT_CAL_START,
MCI_BT_CAL
} MCI_BT_STATE_T;
/* Type of state query */
typedef enum mci_state_type {
HAL_MCI_STATE_ENABLE,
HAL_MCI_STATE_INIT_GPM_OFFSET,
HAL_MCI_STATE_NEXT_GPM_OFFSET,
HAL_MCI_STATE_LAST_GPM_OFFSET,
HAL_MCI_STATE_BT,
HAL_MCI_STATE_SET_BT_SLEEP,
HAL_MCI_STATE_SET_BT_AWAKE,
HAL_MCI_STATE_SET_BT_CAL_START,
HAL_MCI_STATE_SET_BT_CAL,
HAL_MCI_STATE_LAST_SCHD_MSG_OFFSET,
HAL_MCI_STATE_REMOTE_SLEEP,
HAL_MCI_STATE_CONT_RSSI_POWER,
HAL_MCI_STATE_CONT_PRIORITY,
HAL_MCI_STATE_CONT_TXRX,
HAL_MCI_STATE_RESET_REQ_WAKE,
HAL_MCI_STATE_SEND_WLAN_COEX_VERSION,
HAL_MCI_STATE_SET_BT_COEX_VERSION,
HAL_MCI_STATE_SEND_WLAN_CHANNELS,
HAL_MCI_STATE_SEND_VERSION_QUERY,
HAL_MCI_STATE_SEND_STATUS_QUERY,
HAL_MCI_STATE_NEED_FLUSH_BT_INFO,
HAL_MCI_STATE_SET_CONCUR_TX_PRI,
HAL_MCI_STATE_RECOVER_RX,
HAL_MCI_STATE_NEED_FTP_STOMP,
HAL_MCI_STATE_NEED_TUNING,
HAL_MCI_STATE_SHARED_CHAIN_CONCUR_TX,
HAL_MCI_STATE_DEBUG,
HAL_MCI_STATE_MAX
} HAL_MCI_STATE_TYPE;
#define HAL_MCI_STATE_DEBUG_REQ_BT_DEBUG 1
#define HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR 0x00000002
#define HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR 0x00000004
#define HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD 0x00000008
#define HAL_MCI_BT_MCI_FLAGS_LNA_CTRL 0x00000010
#define HAL_MCI_BT_MCI_FLAGS_DEBUG 0x00000020
#define HAL_MCI_BT_MCI_FLAGS_SCHED_MSG 0x00000040
#define HAL_MCI_BT_MCI_FLAGS_CONT_MSG 0x00000080
#define HAL_MCI_BT_MCI_FLAGS_COEX_GPM 0x00000100
#define HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG 0x00000200
#define HAL_MCI_BT_MCI_FLAGS_MCI_MODE 0x00000400
#define HAL_MCI_BT_MCI_FLAGS_EGRET_MODE 0x00000800
#define HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE 0x00001000
#define HAL_MCI_BT_MCI_FLAGS_OTHER 0x00010000
#define HAL_MCI_DEFAULT_BT_MCI_FLAGS 0x00011dde
/*
HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR = 1
HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR = 1
HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD = 1
HAL_MCI_BT_MCI_FLAGS_LNA_CTRL = 1
HAL_MCI_BT_MCI_FLAGS_DEBUG = 0
HAL_MCI_BT_MCI_FLAGS_SCHED_MSG = 1
HAL_MCI_BT_MCI_FLAGS_CONT_MSG = 1
HAL_MCI_BT_MCI_FLAGS_COEX_GPM = 1
HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG = 0
HAL_MCI_BT_MCI_FLAGS_MCI_MODE = 1
HAL_MCI_BT_MCI_FLAGS_EGRET_MODE = 1
HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE = 1
HAL_MCI_BT_MCI_FLAGS_OTHER = 1
*/
#define HAL_MCI_TOGGLE_BT_MCI_FLAGS \
( HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR | \
HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR | \
HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD | \
HAL_MCI_BT_MCI_FLAGS_MCI_MODE )
#define HAL_MCI_2G_FLAGS_CLEAR_MASK 0x00000000
#define HAL_MCI_2G_FLAGS_SET_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS
#define HAL_MCI_2G_FLAGS HAL_MCI_DEFAULT_BT_MCI_FLAGS
#define HAL_MCI_5G_FLAGS_CLEAR_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS
#define HAL_MCI_5G_FLAGS_SET_MASK 0x00000000
#define HAL_MCI_5G_FLAGS (HAL_MCI_DEFAULT_BT_MCI_FLAGS & \
~HAL_MCI_TOGGLE_BT_MCI_FLAGS)
#define HAL_MCI_GPM_NOMORE 0
#define HAL_MCI_GPM_MORE 1
#define HAL_MCI_GPM_INVALID 0xffffffff
#define ATH_AIC_MAX_BT_CHANNEL 79
/*
* Default value for Jupiter is 0x00002201
* Default value for Aphrodite is 0x00002282
*/
#define ATH_MCI_CONFIG_CONCUR_TX 0x00000003
#define ATH_MCI_CONFIG_MCI_OBS_MCI 0x00000004
#define ATH_MCI_CONFIG_MCI_OBS_TXRX 0x00000008
#define ATH_MCI_CONFIG_MCI_OBS_BT 0x00000010
#define ATH_MCI_CONFIG_DISABLE_MCI_CAL 0x00000020
#define ATH_MCI_CONFIG_DISABLE_OSLA 0x00000040
#define ATH_MCI_CONFIG_DISABLE_FTP_STOMP 0x00000080
#define ATH_MCI_CONFIG_AGGR_THRESH 0x00000700
#define ATH_MCI_CONFIG_AGGR_THRESH_S 8
#define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH 0x00000800
#define ATH_MCI_CONFIG_CLK_DIV 0x00003000
#define ATH_MCI_CONFIG_CLK_DIV_S 12
#define ATH_MCI_CONFIG_DISABLE_TUNING 0x00004000
#define ATH_MCI_CONFIG_DISABLE_AIC 0x00008000
#define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN 0x007f0000
#define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN_S 16
#define ATH_MCI_CONFIG_NO_QUIET_ACK 0x00800000
#define ATH_MCI_CONFIG_NO_QUIET_ACK_S 23
#define ATH_MCI_CONFIG_ANT_ARCH 0x07000000
#define ATH_MCI_CONFIG_ANT_ARCH_S 24
#define ATH_MCI_CONFIG_FORCE_QUIET_ACK 0x08000000
#define ATH_MCI_CONFIG_FORCE_QUIET_ACK_S 27
#define ATH_MCI_CONFIG_FORCE_2CHAIN_ACK 0x10000000
#define ATH_MCI_CONFIG_MCI_STAT_DBG 0x20000000
#define ATH_MCI_CONFIG_MCI_WEIGHT_DBG 0x40000000
#define ATH_MCI_CONFIG_DISABLE_MCI 0x80000000
#define ATH_MCI_CONFIG_MCI_OBS_MASK ( ATH_MCI_CONFIG_MCI_OBS_MCI | \
ATH_MCI_CONFIG_MCI_OBS_TXRX | \
ATH_MCI_CONFIG_MCI_OBS_BT )
#define ATH_MCI_CONFIG_MCI_OBS_GPIO 0x0000002F
#define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_NON_SHARED 0x00
#define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED 0x01
#define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_NON_SHARED 0x02
#define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED 0x03
#define ATH_MCI_ANT_ARCH_3_ANT 0x04
#define MCI_ANT_ARCH_PA_LNA_SHARED(c) \
((MS(c, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED) || \
(MS(c, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED))
#define ATH_MCI_CONCUR_TX_SHARED_CHN 0x01
#define ATH_MCI_CONCUR_TX_UNSHARED_CHN 0x02
#define ATH_MCI_CONCUR_TX_DEBUG 0x03
#endif
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_debug.h
+9 -2
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_debug.h 249131 2013-04-05 07:41:47Z adrian $
*/
#ifndef _ATH_AH_DEBUG_H_
#define _ATH_AH_DEBUG_H_
@@ -47,8 +47,15 @@ enum {
HAL_DEBUG_DIVERSITY = 0x00100000, /* diversity debugging */
HAL_DEBUG_DFS = 0x00200000, /* DFS debugging */
HAL_DEBUG_HANG = 0x00400000, /* BB/MAC hang debugging */
HAL_DEBUG_CALIBRATE = 0x00800000, /* setup calibration */
HAL_DEBUG_POWER_MGMT = 0x01000000, /* power calibration */
HAL_DEBUG_CHANNEL = 0x02000000,
HAL_DEBUG_QUEUE = 0x04000000,
HAL_DEBUG_PRINT_REG = 0x08000000,
HAL_DEBUG_FCS_RTT = 0x10000000,
HAL_DEBUG_BT_COEX = 0x20000000,
HAL_DEBUG_UNMASKABLE = 0xf0000000, /* always printed */
HAL_DEBUG_UNMASKABLE = 0x80000000, /* always printed */
HAL_DEBUG_ANY = 0xffffffff
};
#endif /* _ATH_AH_DEBUG_H_ */
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_decode.h
+5 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_decode.h 269749 2014-08-09 09:13:10Z adrian $
*/
#ifndef _ATH_AH_DECODE_H_
#define _ATH_AH_DECODE_H_
@@ -29,6 +29,7 @@
* existing file.
*/
struct athregrec {
uint32_t threadid;
uint32_t op : 8,
reg : 24;
uint32_t val;
@@ -52,6 +53,8 @@ enum {
AH_MARK_ANI_POLL, /* ar*AniReset, listen time */
AH_MARK_ANI_CONTROL, /* ar*AniReset, cmd */
AH_MARK_RX_CTL, /* RX DMA control */
AH_MARK_CHIP_POWER, /* chip power control, mode */
AH_MARK_CHIP_POWER_DONE, /* chip power control done, status */
};
enum {
@@ -60,6 +63,7 @@ enum {
AH_MARK_RX_CTL_DMA_START,
AH_MARK_RX_CTL_DMA_STOP,
AH_MARK_RX_CTL_DMA_STOP_ERR,
AH_MARK_RX_CTL_DMA_STOP_OK,
};
#endif /* _ATH_AH_DECODE_H_ */
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_desc.h
+79 -19
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_desc.h 301041 2016-05-31 16:05:54Z adrian $
*/
#ifndef _DEV_ATH_DESC_H
@@ -22,6 +22,19 @@
#include "opt_ah.h" /* NB: required for AH_SUPPORT_AR5416 */
/*
* For now, define this for the structure definitions.
* Because of how the HAL / driver module currently builds,
* it's not very feasible to build the module without
* this defined. The rest of the code (eg in the driver
* body) can work fine with these fields being uninitialised;
* they'll be initialised to 0 anyway.
*/
#ifndef AH_SUPPORT_AR5416
#define AH_SUPPORT_AR5416 1
#endif
/*
* Transmit descriptor status. This structure is filled
* in only after the tx descriptor process method finds a
@@ -44,15 +57,19 @@ struct ath_tx_status {
uint8_t ts_finaltsi; /* final transmit series index */
#ifdef AH_SUPPORT_AR5416
/* 802.11n status */
uint8_t ts_flags; /* misc flags */
int8_t ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */
int8_t ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */
uint8_t ts_flags; /* misc flags */
uint8_t ts_queue_id; /* AR9300: TX queue id */
uint8_t ts_desc_id; /* AR9300: TX descriptor id */
uint8_t ts_tid; /* TID */
/* #define ts_rssi ts_rssi_combined */
uint32_t ts_ba_low; /* blockack bitmap low */
uint32_t ts_ba_high; /* blockack bitmap high */
uint32_t ts_evm0; /* evm bytes */
uint32_t ts_evm1;
uint32_t ts_evm2;
uint32_t ts_ba_low; /* blockack bitmap low */
uint32_t ts_ba_high; /* blockack bitmap high */
uint32_t ts_evm0; /* evm bytes */
uint32_t ts_evm1;
uint32_t ts_evm2;
int8_t ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */
int8_t ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */
uint8_t ts_pad[2];
#endif /* AH_SUPPORT_AR5416 */
};
@@ -108,11 +125,12 @@ struct ath_rx_status {
int8_t rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */
uint8_t rs_isaggr; /* is part of the aggregate */
uint8_t rs_moreaggr; /* more frames in aggr to follow */
uint16_t rs_flags; /* misc flags */
uint8_t rs_num_delims; /* number of delims in aggr */
uint8_t rs_flags; /* misc flags */
uint8_t rs_spare0; /* padding */
uint32_t rs_evm0; /* evm bytes */
uint32_t rs_evm1;
uint32_t rs_evm2;
uint32_t rs_evm2;
uint32_t rs_evm3; /* needed for ar9300 and later */
uint32_t rs_evm4; /* needed for ar9300 and later */
#endif /* AH_SUPPORT_AR5416 */
@@ -124,16 +142,46 @@ struct ath_rx_status {
#define HAL_RXERR_FIFO 0x04 /* fifo overrun */
#define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */
#define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */
#define HAL_RXERR_INCOMP 0x20 /* Rx Desc processing is incomplete */
#define HAL_RXERR_KEYMISS 0x40 /* Key not found in keycache */
/* bits found in rs_flags */
#define HAL_RX_MORE 0x01 /* more descriptors follow */
#define HAL_RX_MORE_AGGR 0x02 /* more frames in aggr */
#define HAL_RX_GI 0x04 /* full gi */
#define HAL_RX_2040 0x08 /* 40 Mhz */
#define HAL_RX_DELIM_CRC_PRE 0x10 /* crc error in delimiter pre */
#define HAL_RX_DELIM_CRC_POST 0x20 /* crc error in delim after */
#define HAL_RX_DECRYPT_BUSY 0x40 /* decrypt was too slow */
#define HAL_RX_HI_RX_CHAIN 0x80 /* SM power save: hi Rx chain control */
#define HAL_RX_MORE 0x0001 /* more descriptors follow */
#define HAL_RX_MORE_AGGR 0x0002 /* more frames in aggr */
#define HAL_RX_GI 0x0004 /* full gi */
#define HAL_RX_2040 0x0008 /* 40 Mhz */
#define HAL_RX_DELIM_CRC_PRE 0x0010 /* crc error in delimiter pre */
#define HAL_RX_DELIM_CRC_POST 0x0020 /* crc error in delim after */
#define HAL_RX_DECRYPT_BUSY 0x0040 /* decrypt was too slow */
#define HAL_RX_HI_RX_CHAIN 0x0080 /* SM power save: hi Rx chain control */
#define HAL_RX_IS_APSD 0x0100 /* Is ASPD trigger frame */
#define HAL_RX_STBC 0x0200 /* Is an STBC frame */
/*
* This is the format of RSSI[2] on the AR9285/AR9485.
* It encodes the LNA configuration information.
*
* For boards with an external diversity antenna switch,
* HAL_RX_LNA_EXTCFG encodes which configuration was
* used (antenna 1 or antenna 2.) This feeds into the
* switch table and ensures that the given antenna was
* connected to an LNA.
*/
#define HAL_RX_LNA_LNACFG 0x80 /* 1 = main LNA config used, 0 = ALT */
#define HAL_RX_LNA_EXTCFG 0x40 /* 0 = external diversity ant1, 1 = ant2 */
#define HAL_RX_LNA_CFG_USED 0x30 /* 2 bits; LNA config used on RX */
#define HAL_RX_LNA_CFG_USED_S 4
#define HAL_RX_LNA_CFG_MAIN 0x0c /* 2 bits; "Main" LNA config */
#define HAL_RX_LNA_CFG_ALT 0x02 /* 2 bits; "Alt" LNA config */
/*
* This is the format of RSSI_EXT[2] on the AR9285/AR9485.
* It encodes the switch table configuration and fast diversity
* value.
*/
#define HAL_RX_LNA_FASTDIV 0x40 /* 1 = fast diversity measurement done */
#define HAL_RX_LNA_SWITCH_0 0x30 /* 2 bits; sw_0[1:0] */
#define HAL_RX_LNA_SWITCH_COM 0x0f /* 4 bits, sw_com[3:0] */
enum {
HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */
@@ -164,6 +212,8 @@ enum {
HAL_PHYERR_HT_CRC_ERROR = 34, /* */
HAL_PHYERR_HT_LENGTH_ILLEGAL = 35, /* */
HAL_PHYERR_HT_RATE_ILLEGAL = 36, /* */
HAL_PHYERR_SPECTRAL = 38,
};
/* value found in rs_keyix to mark invalid entries */
@@ -200,6 +250,12 @@ struct ath_desc {
uint32_t ds_hw[HAL_DESC_HW_SIZE]; /* opaque h/w region */
};
struct ath_desc_txedma {
uint32_t ds_info;
uint32_t ds_link;
uint32_t ds_hw[21]; /* includes buf/len */
};
struct ath_desc_status {
union {
struct ath_tx_status tx;/* xmit status */
@@ -211,6 +267,7 @@ struct ath_desc_status {
#define ds_rxstat ds_us.rx
/* flags passed to tx descriptor setup methods */
/* This is a uint16_t field in ath_buf, just be warned! */
#define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */
#define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */
#define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */
@@ -222,6 +279,9 @@ struct ath_desc_status {
#define HAL_TXDESC_EXT_ONLY 0x0080 /* send on ext channel only (11n) */
#define HAL_TXDESC_EXT_AND_CTL 0x0100 /* send on ext + ctl channels (11n) */
#define HAL_TXDESC_VMF 0x0200 /* virtual more frag */
#define HAL_TXDESC_LOWRXCHAIN 0x0400 /* switch to low RX chain */
#define HAL_TXDESC_LDPC 0x1000 /* Set LDPC TX for all rates */
#define HAL_TXDESC_HWTS 0x2000 /* Request Azimuth Timestamp in TX payload */
/* flags passed to rx descriptor setup methods */
#define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_devid.h
+16 -3
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_devid.h 291413 2015-11-28 00:27:16Z adrian $
*/
#ifndef _DEV_ATH_DEVID_H_
@@ -73,16 +73,29 @@
/* AR5416 compatible devid's */
#define AR5416_DEVID_PCI 0x0023 /* AR5416 PCI (MB/CB) Owl */
#define AR5416_DEVID_PCIE 0x0024 /* AR5416 PCI-E (XB) Owl */
#define AR5416_DEVID_PCIE 0x0024 /* AR5418 PCI-E (XB) Owl */
#define AR5416_AR9130_DEVID 0x000b /* AR9130 SoC WiMAC */
#define AR9160_DEVID_PCI 0x0027 /* AR9160 PCI Sowl */
#define AR9280_DEVID_PCI 0x0029 /* AR9280 PCI Merlin */
#define AR9280_DEVID_PCIE 0x002a /* AR9280 PCI-E Merlin */
#define AR9280_DEVID_PCIE 0x002a /* AR9220 PCI-E Merlin */
#define AR9285_DEVID_PCIE 0x002b /* AR9285 PCI-E Kite */
#define AR2427_DEVID_PCIE 0x002c /* AR2427 PCI-E w/ 802.11n bonded out */
#define AR9287_DEVID_PCI 0x002d /* AR9227 PCI Kiwi */
#define AR9287_DEVID_PCIE 0x002e /* AR9287 PCI-E Kiwi */
/* AR9300 */
#define AR9300_DEVID_AR9380_PCIE 0x0030
#define AR9300_DEVID_EMU_PCIE 0xabcd
#define AR9300_DEVID_AR9340 0x0031
#define AR9300_DEVID_AR9485_PCIE 0x0032
#define AR9300_DEVID_AR9580_PCIE 0x0033
#define AR9300_DEVID_AR946X_PCIE 0x0034
#define AR9300_DEVID_AR9330 0x0035
#define AR9300_DEVID_QCA9565 0x0036
#define AR9300_DEVID_AR1111_PCIE 0x0037
#define AR9300_DEVID_QCA955X 0x0039
#define AR9300_DEVID_QCA953X 0x003d /* Honey Bee */
#define AR_SUBVENDOR_ID_NOG 0x0e11 /* No 11G subvendor ID */
#define AR_SUBVENDOR_ID_NEW_A 0x7065 /* Update device to new RD */
#endif /* _DEV_ATH_DEVID_H */
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_diagcodes.h
+5 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_diagcodes.h 239629 2012-08-24 00:17:39Z adrian $
*/
#ifndef _ATH_AH_DIAGCODES_H_
#define _ATH_AH_DIAGCODES_H_
@@ -63,6 +63,10 @@ enum {
HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */
HAL_DIAG_SETREGS = 33, /* write registers */
HAL_DIAG_CHANSURVEY = 34, /* channel survey */
HAL_DIAG_PRINT_REG = 35,
HAL_DIAG_PRINT_REG_ALL = 36,
HAL_DIAG_CHANNELS = 37,
HAL_DIAG_PRINT_REG_COUNTER = 38,
};
#endif /* _ATH_AH_DIAGCODES_H_ */
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom.h
+29 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_eeprom.h 239637 2012-08-24 01:14:00Z adrian $
*/
#ifndef _ATH_AH_EEPROM_H_
#define _ATH_AH_EEPROM_H_
@@ -105,6 +105,10 @@ enum {
AR_EEP_TEMPSENSE_SLOPE, /* int8_t* */
AR_EEP_TEMPSENSE_SLOPE_PAL_ON, /* int8_t* */
AR_EEP_FRAC_N_5G, /* uint8_t* */
/* New fields for AR9300 and later */
AR_EEP_DRIVE_STRENGTH,
AR_EEP_PAPRD_ENABLED,
};
typedef struct {
@@ -127,6 +131,30 @@ typedef struct {
#define CTL_2GHT40 7
#define CTL_5GHT40 8
/* XXX must match what FCC/MKK/ETSI are defined as in ah_regdomain.h */
#define HAL_REG_DMN_MASK 0xf0
#define HAL_REGDMN_FCC 0x10
#define HAL_REGDMN_MKK 0x40
#define HAL_REGDMN_ETSI 0x30
#define is_reg_dmn_fcc(reg_dmn) \
(((reg_dmn & HAL_REG_DMN_MASK) == HAL_REGDMN_FCC) ? 1 : 0)
#define is_reg_dmn_etsi(reg_dmn) \
(((reg_dmn & HAL_REG_DMN_MASK) == HAL_REGDMN_ETSI) ? 1 : 0)
#define is_reg_dmn_mkk(reg_dmn) \
(((reg_dmn & HAL_REG_DMN_MASK) == HAL_REGDMN_MKK) ? 1 : 0)
#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
/* regulatory capabilities prior to eeprom version 4.0 */
#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
#define AR_NO_SPUR 0x8000
/* XXX exposed to chip code */
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom_9287.c
+7 -7
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_eeprom_9287.c 239704 2012-08-26 04:26:49Z adrian $
*/
#include "opt_ah.h"
@@ -310,12 +310,12 @@ ath_hal_9287EepromAttach(struct ath_hal *ah)
"%s Error reading Eeprom MAGIC\n", __func__);
return HAL_EEREAD;
}
}
HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s Eeprom Magic = 0x%x\n",
__func__, magic);
if (magic != AR5416_EEPROM_MAGIC) {
HALDEBUG(ah, HAL_DEBUG_ANY, "Bad magic number\n");
return HAL_EEMAGIC;
HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s Eeprom Magic = 0x%x\n",
__func__, magic);
if (magic != AR5416_EEPROM_MAGIC) {
HALDEBUG(ah, HAL_DEBUG_ANY, "Bad magic number\n");
return HAL_EEMAGIC;
}
}
ee = ath_hal_malloc(sizeof(HAL_EEPROM_9287));
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom_9287.h
+1 -1
View File
@@ -13,7 +13,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_eeprom_9287.h 223615 2011-06-28 00:01:55Z adrian $
*/
#ifndef __AH_EEPROM_9287_H__
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom_v1.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_eeprom_v1.c 221896 2011-05-14 15:12:02Z adrian $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom_v1.h
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_eeprom_v1.h 204644 2010-03-03 17:32:32Z rpaulo $
*/
#ifndef _ATH_AH_EEPROM_V1_H_
#define _ATH_AH_EEPROM_V1_H_
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom_v14.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_eeprom_v14.c 224519 2011-07-30 13:45:12Z adrian $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom_v14.h
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_eeprom_v14.h 224519 2011-07-30 13:45:12Z adrian $
*/
#ifndef _AH_EEPROM_V14_H_
#define _AH_EEPROM_V14_H_
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom_v3.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_eeprom_v3.c 221896 2011-05-14 15:12:02Z adrian $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom_v3.h
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_eeprom_v3.h 204644 2010-03-03 17:32:32Z rpaulo $
*/
#ifndef _ATH_AH_EEPROM_V3_H_
#define _ATH_AH_EEPROM_V3_H_
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom_v4k.c
+1 -1
View File
@@ -15,7 +15,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_eeprom_v4k.c 234508 2012-04-20 21:56:13Z adrian $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_eeprom_v4k.h
+1 -1
View File
@@ -15,7 +15,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_eeprom_v4k.h 220946 2011-04-22 10:57:46Z adrian $
*/
#ifndef _AH_EEPROM_V4K_H_
#define _AH_EEPROM_V4K_H_
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_internal.h
+239 -26
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_internal.h 291469 2015-11-30 06:26:59Z adrian $
*/
#ifndef _ATH_AH_INTERAL_H_
#define _ATH_AH_INTERAL_H_
@@ -30,6 +30,10 @@
#include <net80211/_ieee80211.h>
#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */
#ifndef AH_SUPPORT_AR5416
#define AH_SUPPORT_AR5416 1
#endif
#ifndef NBBY
#define NBBY 8 /* number of bits/byte */
#endif
@@ -46,8 +50,8 @@
#endif
typedef struct {
uint16_t start; /* first register */
uint16_t end; /* ending register or zero */
uint32_t start; /* first register */
uint32_t end; /* ending register or zero */
} HAL_REGRANGE;
typedef struct {
@@ -74,6 +78,11 @@ typedef enum {
HAL_CAP_AR = 1, /* AR capability */
} HAL_PHYDIAG_CAPS;
/*
* Enable/disable strong signal fast diversity
*/
#define HAL_CAP_STRONG_DIV 2
/*
* Each chip or class of chips registers to offer support.
*/
@@ -82,6 +91,7 @@ struct ath_hal_chip {
const char *(*probe)(uint16_t vendorid, uint16_t devid);
struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC,
HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata,
HAL_OPS_CONFIG *ah,
HAL_STATUS *error);
};
#ifndef AH_CHIP
@@ -127,6 +137,41 @@ struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode);
#define AH_MAXCHAN 96
#endif
#define HAL_NF_CAL_HIST_LEN_FULL 5
#define HAL_NF_CAL_HIST_LEN_SMALL 1
#define HAL_NUM_NF_READINGS 6 /* 3 chains * (ctl + ext) */
#define HAL_NF_LOAD_DELAY 1000
/*
* PER_CHAN doesn't work for now, as it looks like the device layer
* has to pre-populate the per-channel list with nominal values.
*/
//#define ATH_NF_PER_CHAN 1
typedef struct {
u_int8_t curr_index;
int8_t invalidNFcount; /* TO DO: REMOVE THIS! */
int16_t priv_nf[HAL_NUM_NF_READINGS];
} HAL_NFCAL_BASE;
typedef struct {
HAL_NFCAL_BASE base;
int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_FULL][HAL_NUM_NF_READINGS];
} HAL_NFCAL_HIST_FULL;
typedef struct {
HAL_NFCAL_BASE base;
int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_SMALL][HAL_NUM_NF_READINGS];
} HAL_NFCAL_HIST_SMALL;
#ifdef ATH_NF_PER_CHAN
typedef HAL_NFCAL_HIST_FULL HAL_CHAN_NFCAL_HIST;
#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (ichan ? &ichan->nf_cal_hist: NULL)
#else
typedef HAL_NFCAL_HIST_SMALL HAL_CHAN_NFCAL_HIST;
#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (&AH_PRIVATE(ah)->nf_cal_hist)
#endif /* ATH_NF_PER_CHAN */
/*
* Internal per-channel state. These are found
* using ic_devdata in the ieee80211_channel.
@@ -144,10 +189,16 @@ typedef struct {
int16_t rawNoiseFloor;
int16_t noiseFloorAdjust;
#ifdef AH_SUPPORT_AR5416
int16_t noiseFloorCtl[AH_MIMO_MAX_CHAINS];
int16_t noiseFloorExt[AH_MIMO_MAX_CHAINS];
int16_t noiseFloorCtl[AH_MAX_CHAINS];
int16_t noiseFloorExt[AH_MAX_CHAINS];
#endif /* AH_SUPPORT_AR5416 */
uint16_t mainSpur; /* cached spur value for this channel */
/*XXX TODO: make these part of privFlags */
uint8_t paprd_done:1, /* 1: PAPRD DONE, 0: PAPRD Cal not done */
paprd_table_write_done:1; /* 1: DONE, 0: Cal data write not done */
int one_time_cals_done;
HAL_CHAN_NFCAL_HIST nf_cal_hist;
} HAL_CHANNEL_INTERNAL;
/* channel requires noise floor check */
@@ -208,8 +259,32 @@ typedef struct {
halBssidMatchSupport : 1,
hal4kbSplitTransSupport : 1,
halHasRxSelfLinkedTail : 1,
halSupportsFastClock5GHz : 1, /* Hardware supports 5ghz fast clock; check eeprom/channel before using */
halHasLongRxDescTsf : 1;
halSupportsFastClock5GHz : 1,
halHasLongRxDescTsf : 1,
halHasBBReadWar : 1,
halSerialiseRegWar : 1,
halMciSupport : 1,
halRxTxAbortSupport : 1,
halPaprdEnabled : 1,
halHasUapsdSupport : 1,
halWpsPushButtonSupport : 1,
halBtCoexApsmWar : 1,
halGenTimerSupport : 1,
halLDPCSupport : 1,
halHwBeaconProcSupport : 1,
halEnhancedDmaSupport : 1;
uint32_t halIsrRacSupport : 1,
halApmEnable : 1,
halIntrMitigation : 1,
hal49GhzSupport : 1,
halAntDivCombSupport : 1,
halAntDivCombSupportOrg : 1,
halRadioRetentionSupport : 1,
halSpectralScanSupport : 1,
halRxUsingLnaMixing : 1,
halRxDoMyBeacon : 1,
halHwUapsdTrig : 1;
uint32_t halWirelessModes;
uint16_t halTotalQueues;
uint16_t halKeyCacheSize;
@@ -225,10 +300,32 @@ typedef struct {
uint32_t halIntrMask;
uint8_t halTxStreams;
uint8_t halRxStreams;
HAL_MFP_OPT_T halMfpSupport;
/* AR9300 HAL porting capabilities */
int hal_paprd_enabled;
int hal_pcie_lcr_offset;
int hal_pcie_lcr_extsync_en;
int halNumTxMaps;
int halTxDescLen;
int halTxStatusLen;
int halRxStatusLen;
int halRxHpFifoDepth;
int halRxLpFifoDepth;
uint32_t halRegCap; /* XXX needed? */
int halNumMRRetries;
int hal_ani_poll_interval;
int hal_channel_switch_time_usec;
} HAL_CAPABILITIES;
struct regDomain;
/*
* Definitions for ah_flags in ath_hal_private
*/
#define AH_USE_EEPROM 0x1
#define AH_IS_HB63 0x2
/*
* The ``private area'' follows immediately after the ``public area''
* in the data structure returned by ath_hal_attach. Private data are
@@ -288,7 +385,9 @@ struct ath_hal_private {
uint16_t ah_phyRev; /* PHY revision */
uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
uint32_t ah_flags; /* misc flags */
uint8_t ah_ispcie; /* PCIE, special treatment */
uint8_t ah_devType; /* card type - CB, PCI, PCIe */
HAL_OPMODE ah_opmode; /* operating mode from reset */
const struct ieee80211_channel *ah_curchan;/* operating channel */
@@ -297,6 +396,7 @@ struct ath_hal_private {
int16_t ah_powerLimit; /* tx power cap */
uint16_t ah_maxPowerLevel; /* calculated max tx power */
u_int ah_tpScale; /* tx power scale factor */
u_int16_t ah_extraTxPow; /* low rates extra-txpower */
uint32_t ah_11nCompat; /* 11n compat controls */
/*
@@ -321,6 +421,14 @@ struct ath_hal_private {
*/
uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */
int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */
/* Only used if ATH_NF_PER_CHAN is defined */
HAL_NFCAL_HIST_FULL nf_cal_hist;
/*
* Channel survey history - current channel only.
*/
HAL_CHANNEL_SURVEY ah_chansurvey; /* channel survey */
};
#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah))
@@ -349,13 +457,20 @@ struct ath_hal_private {
AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c)
#define ath_hal_getNoiseFloor(_ah, _nfArray) \
AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray)
#define ath_hal_configPCIE(_ah, _reset) \
(_ah)->ah_configPCIE(_ah, _reset)
#define ath_hal_configPCIE(_ah, _reset, _poweroff) \
(_ah)->ah_configPCIE(_ah, _reset, _poweroff)
#define ath_hal_disablePCIE(_ah) \
(_ah)->ah_disablePCIE(_ah)
#define ath_hal_setInterrupts(_ah, _mask) \
(_ah)->ah_setInterrupts(_ah, _mask)
#define ath_hal_isrfkillenabled(_ah) \
(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, AH_NULL) == HAL_OK)
#define ath_hal_enable_rfkill(_ah, _v) \
ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _v, AH_NULL)
#define ath_hal_hasrfkill_int(_ah) \
(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 3, AH_NULL) == HAL_OK)
#define ath_hal_eepromDetach(_ah) do { \
if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \
AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \
@@ -472,10 +587,23 @@ isBigEndian(void)
OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f))
#define OS_REG_CLR_BIT(_a, _r, _f) \
OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f))
#define OS_REG_IS_BIT_SET(_a, _r, _f) \
((OS_REG_READ(_a, _r) & (_f)) != 0)
#define OS_REG_RMW_FIELD_ALT(_a, _r, _f, _v) \
OS_REG_WRITE(_a, _r, \
(OS_REG_READ(_a, _r) &~(_f<<_f##_S)) | \
(((_v) << _f##_S) & (_f<<_f##_S)))
#define OS_REG_READ_FIELD(_a, _r, _f) \
(((OS_REG_READ(_a, _r) & _f) >> _f##_S))
#define OS_REG_READ_FIELD_ALT(_a, _r, _f) \
((OS_REG_READ(_a, _r) >> (_f##_S))&(_f))
/* Analog register writes may require a delay between each one (eg Merlin?) */
#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \
do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0)
do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | \
(((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0)
#define OS_A_REG_WRITE(_a, _r, _v) \
do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0)
/* wait for the register contents to have the specified value */
extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,
@@ -503,26 +631,15 @@ extern void ath_hal_free(void *);
extern int ath_hal_debug; /* Global debug flags */
/*
* This is used for global debugging, when ahp doesn't yet have the
* related debugging state. For example, during probe/attach.
*/
#define HALDEBUG_G(_ah, __m, ...) \
do { \
if ((__m) == HAL_DEBUG_UNMASKABLE || \
ath_hal_debug & (__m)) { \
DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \
} \
} while (0);
/*
* This is used for local debugging, when ahp isn't NULL and
* thus may have debug flags set.
* The typecast is purely because some callers will pass in
* AH_NULL directly rather than using a NULL ath_hal pointer.
*/
#define HALDEBUG(_ah, __m, ...) \
do { \
if ((__m) == HAL_DEBUG_UNMASKABLE || \
ath_hal_debug & (__m) || \
(_ah)->ah_config.ah_debug & (__m)) { \
((_ah) != NULL && \
((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \
DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \
} \
} while(0);
@@ -531,7 +648,6 @@ extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
__printflike(3,4);
#else
#define HALDEBUG(_ah, __m, ...)
#define HALDEBUG_G(_ah, __m, ...)
#endif /* AH_DEBUG */
/*
@@ -630,6 +746,46 @@ extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,
/* The diagnostic codes used to be internally defined here -adrian */
#include "ah_diagcodes.h"
/*
* The AR5416 and later HALs have MAC and baseband hang checking.
*/
typedef struct {
uint32_t hang_reg_offset;
uint32_t hang_val;
uint32_t hang_mask;
uint32_t hang_offset;
} hal_hw_hang_check_t;
typedef struct {
uint32_t dma_dbg_3;
uint32_t dma_dbg_4;
uint32_t dma_dbg_5;
uint32_t dma_dbg_6;
} mac_dbg_regs_t;
typedef enum {
dcu_chain_state = 0x1,
dcu_complete_state = 0x2,
qcu_state = 0x4,
qcu_fsp_ok = 0x8,
qcu_fsp_state = 0x10,
qcu_stitch_state = 0x20,
qcu_fetch_state = 0x40,
qcu_complete_state = 0x80
} hal_mac_hangs_t;
typedef struct {
int states;
uint8_t dcu_chain_state;
uint8_t dcu_complete_state;
uint8_t qcu_state;
uint8_t qcu_fsp_ok;
uint8_t qcu_fsp_state;
uint8_t qcu_stitch_state;
uint8_t qcu_fetch_state;
uint8_t qcu_complete_state;
} hal_mac_hang_check_t;
enum {
HAL_BB_HANG_DFS = 0x0001,
HAL_BB_HANG_RIFS = 0x0002,
@@ -649,6 +805,17 @@ enum {
| HAL_MAC_HANG_UNKNOWN,
};
/* Merge these with above */
typedef enum hal_hw_hangs {
HAL_DFS_BB_HANG_WAR = 0x1,
HAL_RIFS_BB_HANG_WAR = 0x2,
HAL_RX_STUCK_LOW_BB_HANG_WAR = 0x4,
HAL_MAC_HANG_WAR = 0x8,
HAL_PHYRESTART_CLR_WAR = 0x10,
HAL_MAC_HANG_DETECTED = 0x40000000,
HAL_BB_HANG_DETECTED = 0x80000000
} hal_hw_hangs_t;
/*
* Device revision information.
*/
@@ -830,5 +997,51 @@ extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft,
AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \
ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G))
/*
* Fetch the maximum regulatory domain power for the given channel
* in 1/2dBm steps.
*/
static inline int
ath_hal_get_twice_max_regpower(struct ath_hal_private *ahp,
const HAL_CHANNEL_INTERNAL *ichan, const struct ieee80211_channel *chan)
{
struct ath_hal *ah = &ahp->h;
if (! chan) {
ath_hal_printf(ah, "%s: called with chan=NULL!\n", __func__);
return (0);
}
return (chan->ic_maxpower);
}
/*
* Get the maximum antenna gain allowed, in 1/2dBm steps.
*/
static inline int
ath_hal_getantennaallowed(struct ath_hal *ah,
const struct ieee80211_channel *chan)
{
if (! chan)
return (0);
return (chan->ic_maxantgain);
}
/*
* Map the given 2GHz channel to an IEEE number.
*/
extern int ath_hal_mhz2ieee_2ghz(struct ath_hal *, int freq);
/*
* Clear the channel survey data.
*/
extern void ath_hal_survey_clear(struct ath_hal *ah);
/*
* Add a sample to the channel survey data.
*/
extern void ath_hal_survey_add_sample(struct ath_hal *ah,
HAL_SURVEY_SAMPLE *hs);
#endif /* _ATH_AH_INTERAL_H_ */
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_regdomain.c
+279 -210
View File
@@ -15,7 +15,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_regdomain.c 300267 2016-05-20 06:06:21Z adrian $
*/
#include "opt_ah.h"
@@ -35,7 +35,7 @@
*/
/* used throughout this file... */
#define N(a) (sizeof (a) / sizeof (a[0]))
#define N(a) nitems(a)
#define HAL_MODE_11A_TURBO HAL_MODE_108A
#define HAL_MODE_11G_TURBO HAL_MODE_108G
@@ -99,30 +99,32 @@
#include "ah_regdomain/ah_rd_domains.h"
static const struct cmode modes[] = {
{ HAL_MODE_TURBO, IEEE80211_CHAN_ST },
{ HAL_MODE_11A, IEEE80211_CHAN_A },
{ HAL_MODE_11B, IEEE80211_CHAN_B },
{ HAL_MODE_11G, IEEE80211_CHAN_G },
{ HAL_MODE_11G_TURBO, IEEE80211_CHAN_108G },
{ HAL_MODE_11A_TURBO, IEEE80211_CHAN_108A },
{ HAL_MODE_TURBO, IEEE80211_CHAN_ST, &regDmn5GhzTurboFreq[0] },
{ HAL_MODE_11A, IEEE80211_CHAN_A, &regDmn5GhzFreq[0] },
{ HAL_MODE_11B, IEEE80211_CHAN_B, &regDmn2GhzFreq[0] },
{ HAL_MODE_11G, IEEE80211_CHAN_G, &regDmn2Ghz11gFreq[0] },
{ HAL_MODE_11G_TURBO, IEEE80211_CHAN_108G, &regDmn2Ghz11gTurboFreq[0] },
{ HAL_MODE_11A_TURBO, IEEE80211_CHAN_108A, &regDmn5GhzTurboFreq[0] },
{ HAL_MODE_11A_QUARTER_RATE,
IEEE80211_CHAN_A | IEEE80211_CHAN_QUARTER },
IEEE80211_CHAN_A | IEEE80211_CHAN_QUARTER, &regDmn5GhzFreq[0] },
{ HAL_MODE_11A_HALF_RATE,
IEEE80211_CHAN_A | IEEE80211_CHAN_HALF },
IEEE80211_CHAN_A | IEEE80211_CHAN_HALF, &regDmn5GhzFreq[0] },
{ HAL_MODE_11G_QUARTER_RATE,
IEEE80211_CHAN_G | IEEE80211_CHAN_QUARTER },
IEEE80211_CHAN_G | IEEE80211_CHAN_QUARTER, &regDmn2Ghz11gFreq[0] },
{ HAL_MODE_11G_HALF_RATE,
IEEE80211_CHAN_G | IEEE80211_CHAN_HALF },
{ HAL_MODE_11NG_HT20, IEEE80211_CHAN_G | IEEE80211_CHAN_HT20 },
IEEE80211_CHAN_G | IEEE80211_CHAN_HALF, &regDmn2Ghz11gFreq[0] },
{ HAL_MODE_11NG_HT20,
IEEE80211_CHAN_G | IEEE80211_CHAN_HT20, &regDmn2Ghz11gFreq[0] },
{ HAL_MODE_11NG_HT40PLUS,
IEEE80211_CHAN_G | IEEE80211_CHAN_HT40U },
IEEE80211_CHAN_G | IEEE80211_CHAN_HT40U, &regDmn2Ghz11gFreq[0] },
{ HAL_MODE_11NG_HT40MINUS,
IEEE80211_CHAN_G | IEEE80211_CHAN_HT40D },
{ HAL_MODE_11NA_HT20, IEEE80211_CHAN_A | IEEE80211_CHAN_HT20 },
IEEE80211_CHAN_G | IEEE80211_CHAN_HT40D, &regDmn2Ghz11gFreq[0] },
{ HAL_MODE_11NA_HT20,
IEEE80211_CHAN_A | IEEE80211_CHAN_HT20, &regDmn5GhzFreq[0] },
{ HAL_MODE_11NA_HT40PLUS,
IEEE80211_CHAN_A | IEEE80211_CHAN_HT40U },
IEEE80211_CHAN_A | IEEE80211_CHAN_HT40U, &regDmn5GhzFreq[0] },
{ HAL_MODE_11NA_HT40MINUS,
IEEE80211_CHAN_A | IEEE80211_CHAN_HT40D },
IEEE80211_CHAN_A | IEEE80211_CHAN_HT40D, &regDmn5GhzFreq[0] },
};
static void ath_hal_update_dfsdomain(struct ath_hal *ah);
@@ -169,7 +171,12 @@ isEepromValid(struct ath_hal *ah)
if (regDomainPairs[i].regDmnEnum == rd)
return AH_TRUE;
}
HALDEBUG_G(ah, HAL_DEBUG_REGDOMAIN,
if (rd == FCC_UBNT) {
return AH_TRUE;
}
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
"%s: invalid regulatory domain/country code 0x%x\n", __func__, rd);
return AH_FALSE;
}
@@ -353,6 +360,235 @@ getregstate(struct ath_hal *ah, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn,
return HAL_OK;
}
static uint64_t *
getchannelBM(u_int mode, REG_DOMAIN *rd)
{
switch (mode) {
case HAL_MODE_11B:
return (rd->chan11b);
case HAL_MODE_11G_QUARTER_RATE:
return (rd->chan11g_quarter);
case HAL_MODE_11G_HALF_RATE:
return (rd->chan11g_half);
case HAL_MODE_11G:
case HAL_MODE_11NG_HT20:
case HAL_MODE_11NG_HT40PLUS:
case HAL_MODE_11NG_HT40MINUS:
return (rd->chan11g);
case HAL_MODE_11G_TURBO:
return (rd->chan11g_turbo);
case HAL_MODE_11A_QUARTER_RATE:
return (rd->chan11a_quarter);
case HAL_MODE_11A_HALF_RATE:
return (rd->chan11a_half);
case HAL_MODE_11A:
case HAL_MODE_11NA_HT20:
case HAL_MODE_11NA_HT40PLUS:
case HAL_MODE_11NA_HT40MINUS:
return (rd->chan11a);
case HAL_MODE_TURBO:
return (rd->chan11a_turbo);
case HAL_MODE_11A_TURBO:
return (rd->chan11a_dyn_turbo);
default:
return (AH_NULL);
}
}
static void
setchannelflags(struct ieee80211_channel *c, REG_DMN_FREQ_BAND *fband,
REG_DOMAIN *rd)
{
if (fband->usePassScan & rd->pscan)
c->ic_flags |= IEEE80211_CHAN_PASSIVE;
if (fband->useDfs & rd->dfsMask)
c->ic_flags |= IEEE80211_CHAN_DFS;
if (IEEE80211_IS_CHAN_5GHZ(c) && (rd->flags & DISALLOW_ADHOC_11A))
c->ic_flags |= IEEE80211_CHAN_NOADHOC;
if (IEEE80211_IS_CHAN_TURBO(c) &&
(rd->flags & DISALLOW_ADHOC_11A_TURB))
c->ic_flags |= IEEE80211_CHAN_NOADHOC;
if (rd->flags & NO_HOSTAP)
c->ic_flags |= IEEE80211_CHAN_NOHOSTAP;
if (rd->flags & LIMIT_FRAME_4MS)
c->ic_flags |= IEEE80211_CHAN_4MSXMIT;
if (rd->flags & NEED_NFC)
c->ic_flags |= CHANNEL_NFCREQUIRED;
}
static int
addchan(struct ath_hal *ah, struct ieee80211_channel chans[],
u_int maxchans, int *nchans, uint16_t freq, uint32_t flags,
REG_DMN_FREQ_BAND *fband, REG_DOMAIN *rd)
{
struct ieee80211_channel *c;
if (*nchans >= maxchans)
return (HAL_ENOMEM);
c = &chans[(*nchans)++];
c->ic_freq = freq;
c->ic_flags = flags;
setchannelflags(c, fband, rd);
c->ic_maxregpower = fband->powerDfs;
ath_hal_getpowerlimits(ah, c);
c->ic_maxantgain = fband->antennaMax;
return (0);
}
static int
copychan_prev(struct ath_hal *ah, struct ieee80211_channel chans[],
u_int maxchans, int *nchans, uint16_t freq)
{
struct ieee80211_channel *c;
if (*nchans == 0)
return (HAL_EINVAL);
if (*nchans >= maxchans)
return (HAL_ENOMEM);
c = &chans[(*nchans)++];
c[0] = c[-1];
c->ic_freq = freq;
/* XXX is it needed here? */
ath_hal_getpowerlimits(ah, c);
return (0);
}
static int
add_chanlist_band(struct ath_hal *ah, struct ieee80211_channel chans[],
int maxchans, int *nchans, uint16_t freq_lo, uint16_t freq_hi, int step,
uint32_t flags, REG_DMN_FREQ_BAND *fband, REG_DOMAIN *rd)
{
uint16_t freq = freq_lo;
int error;
if (freq_hi < freq_lo)
return (0);
error = addchan(ah, chans, maxchans, nchans, freq, flags, fband, rd);
for (freq += step; freq <= freq_hi && error == 0; freq += step)
error = copychan_prev(ah, chans, maxchans, nchans, freq);
return (error);
}
static void
adj_freq_ht40(u_int mode, int *low_adj, int *hi_adj, int *channelSep)
{
*low_adj = *hi_adj = *channelSep = 0;
switch (mode) {
case HAL_MODE_11NA_HT40PLUS:
*channelSep = 40;
/* FALLTHROUGH */
case HAL_MODE_11NG_HT40PLUS:
*hi_adj = -20;
break;
case HAL_MODE_11NA_HT40MINUS:
*channelSep = 40;
/* FALLTHROUGH */
case HAL_MODE_11NG_HT40MINUS:
*low_adj = 20;
break;
}
}
static void
add_chanlist_mode(struct ath_hal *ah, struct ieee80211_channel chans[],
u_int maxchans, int *nchans, const struct cmode *cm, REG_DOMAIN *rd,
HAL_BOOL enableExtendedChannels)
{
uint64_t *channelBM;
uint16_t freq_lo, freq_hi;
int b, error, low_adj, hi_adj, channelSep;
if (!ath_hal_getChannelEdges(ah, cm->flags, &freq_lo, &freq_hi)) {
/* channel not supported by hardware, skip it */
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
"%s: channels 0x%x not supported by hardware\n",
__func__, cm->flags);
return;
}
channelBM = getchannelBM(cm->mode, rd);
if (isChanBitMaskZero(channelBM))
return;
/*
* Setup special handling for HT40 channels; e.g.
* 5G HT40 channels require 40Mhz channel separation.
*/
adj_freq_ht40(cm->mode, &low_adj, &hi_adj, &channelSep);
for (b = 0; b < 64*BMLEN; b++) {
REG_DMN_FREQ_BAND *fband;
uint16_t bfreq_lo, bfreq_hi;
int step;
if (!IS_BIT_SET(b, channelBM))
continue;
fband = &cm->freqs[b];
if ((fband->usePassScan & IS_ECM_CHAN) &&
!enableExtendedChannels) {
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
"skip ecm channels\n");
continue;
}
#if 0
if ((fband->useDfs & rd->dfsMask) &&
(cm->flags & IEEE80211_CHAN_HT40)) {
/* NB: DFS and HT40 don't mix */
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
"skip HT40 chan, DFS required\n");
continue;
}
#endif
bfreq_lo = MAX(fband->lowChannel + low_adj, freq_lo);
bfreq_hi = MIN(fband->highChannel + hi_adj, freq_hi);
if (fband->channelSep >= channelSep)
step = fband->channelSep;
else
step = roundup(channelSep, fband->channelSep);
error = add_chanlist_band(ah, chans, maxchans, nchans,
bfreq_lo, bfreq_hi, step, cm->flags, fband, rd);
if (error != 0) {
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
"%s: too many channels for channel table\n",
__func__);
return;
}
}
}
static u_int
getmodesmask(struct ath_hal *ah, REG_DOMAIN *rd5GHz, u_int modeSelect)
{
#define HAL_MODE_11A_ALL \
(HAL_MODE_11A | HAL_MODE_11A_TURBO | HAL_MODE_TURBO | \
HAL_MODE_11A_QUARTER_RATE | HAL_MODE_11A_HALF_RATE)
u_int modesMask;
/* get modes that HW is capable of */
modesMask = ath_hal_getWirelessModes(ah);
modesMask &= modeSelect;
/* optimize work below if no 11a channels */
if (isChanBitMaskZero(rd5GHz->chan11a) &&
(modesMask & HAL_MODE_11A_ALL)) {
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
"%s: disallow all 11a\n", __func__);
modesMask &= ~HAL_MODE_11A_ALL;
}
return (modesMask);
#undef HAL_MODE_11A_ALL
}
/*
* Construct the channel list for the specified regulatory config.
*/
@@ -364,16 +600,9 @@ getchannels(struct ath_hal *ah,
COUNTRY_CODE_TO_ENUM_RD **pcountry,
REG_DOMAIN **prd2GHz, REG_DOMAIN **prd5GHz)
{
#define CHANNEL_HALF_BW 10
#define CHANNEL_QUARTER_BW 5
#define HAL_MODE_11A_ALL \
(HAL_MODE_11A | HAL_MODE_11A_TURBO | HAL_MODE_TURBO | \
HAL_MODE_11A_QUARTER_RATE | HAL_MODE_11A_HALF_RATE)
REG_DOMAIN *rd5GHz, *rd2GHz;
u_int modesAvail;
u_int modesMask;
const struct cmode *cm;
struct ieee80211_channel *ic;
int next, b;
HAL_STATUS status;
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: cc %u regDmn 0x%x mode 0x%x%s\n",
@@ -384,206 +613,43 @@ getchannels(struct ath_hal *ah,
if (status != HAL_OK)
return status;
/* get modes that HW is capable of */
modesAvail = ath_hal_getWirelessModes(ah);
/* optimize work below if no 11a channels */
if (isChanBitMaskZero(rd5GHz->chan11a) &&
(modesAvail & HAL_MODE_11A_ALL)) {
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
"%s: disallow all 11a\n", __func__);
modesAvail &= ~HAL_MODE_11A_ALL;
}
modesMask = getmodesmask(ah, rd5GHz, modeSelect);
/* XXX error? */
if (modesMask == 0)
goto done;
next = 0;
ic = &chans[0];
for (cm = modes; cm < &modes[N(modes)]; cm++) {
uint16_t c, c_hi, c_lo;
uint64_t *channelBM = AH_NULL;
REG_DMN_FREQ_BAND *fband = AH_NULL,*freqs;
int low_adj, hi_adj, channelSep, lastc;
uint32_t rdflags;
uint64_t dfsMask;
uint64_t pscan;
REG_DOMAIN *rd;
if ((cm->mode & modeSelect) == 0) {
if ((cm->mode & modesMask) == 0) {
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
"%s: skip mode 0x%x flags 0x%x\n",
__func__, cm->mode, cm->flags);
continue;
}
if ((cm->mode & modesAvail) == 0) {
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
"%s: !avail mode 0x%x (0x%x) flags 0x%x\n",
__func__, modesAvail, cm->mode, cm->flags);
continue;
}
if (!ath_hal_getChannelEdges(ah, cm->flags, &c_lo, &c_hi)) {
/* channel not supported by hardware, skip it */
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
"%s: channels 0x%x not supported by hardware\n",
__func__,cm->flags);
continue;
}
switch (cm->mode) {
case HAL_MODE_TURBO:
case HAL_MODE_11A_TURBO:
rdflags = rd5GHz->flags;
dfsMask = rd5GHz->dfsMask;
pscan = rd5GHz->pscan;
if (cm->mode == HAL_MODE_TURBO)
channelBM = rd5GHz->chan11a_turbo;
else
channelBM = rd5GHz->chan11a_dyn_turbo;
freqs = &regDmn5GhzTurboFreq[0];
break;
case HAL_MODE_11G_TURBO:
rdflags = rd2GHz->flags;
dfsMask = rd2GHz->dfsMask;
pscan = rd2GHz->pscan;
channelBM = rd2GHz->chan11g_turbo;
freqs = &regDmn2Ghz11gTurboFreq[0];
break;
case HAL_MODE_11A:
case HAL_MODE_11A_HALF_RATE:
case HAL_MODE_11A_QUARTER_RATE:
case HAL_MODE_11NA_HT20:
case HAL_MODE_11NA_HT40PLUS:
case HAL_MODE_11NA_HT40MINUS:
rdflags = rd5GHz->flags;
dfsMask = rd5GHz->dfsMask;
pscan = rd5GHz->pscan;
if (cm->mode == HAL_MODE_11A_HALF_RATE)
channelBM = rd5GHz->chan11a_half;
else if (cm->mode == HAL_MODE_11A_QUARTER_RATE)
channelBM = rd5GHz->chan11a_quarter;
else
channelBM = rd5GHz->chan11a;
freqs = &regDmn5GhzFreq[0];
break;
case HAL_MODE_11B:
case HAL_MODE_11G:
case HAL_MODE_11G_HALF_RATE:
case HAL_MODE_11G_QUARTER_RATE:
case HAL_MODE_11NG_HT20:
case HAL_MODE_11NG_HT40PLUS:
case HAL_MODE_11NG_HT40MINUS:
rdflags = rd2GHz->flags;
dfsMask = rd2GHz->dfsMask;
pscan = rd2GHz->pscan;
if (cm->mode == HAL_MODE_11G_HALF_RATE)
channelBM = rd2GHz->chan11g_half;
else if (cm->mode == HAL_MODE_11G_QUARTER_RATE)
channelBM = rd2GHz->chan11g_quarter;
else if (cm->mode == HAL_MODE_11B)
channelBM = rd2GHz->chan11b;
else
channelBM = rd2GHz->chan11g;
if (cm->mode == HAL_MODE_11B)
freqs = &regDmn2GhzFreq[0];
else
freqs = &regDmn2Ghz11gFreq[0];
break;
default:
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
"%s: Unkonwn HAL mode 0x%x\n", __func__, cm->mode);
continue;
}
if (isChanBitMaskZero(channelBM))
continue;
/*
* Setup special handling for HT40 channels; e.g.
* 5G HT40 channels require 40Mhz channel separation.
*/
hi_adj = (cm->mode == HAL_MODE_11NA_HT40PLUS ||
cm->mode == HAL_MODE_11NG_HT40PLUS) ? -20 : 0;
low_adj = (cm->mode == HAL_MODE_11NA_HT40MINUS ||
cm->mode == HAL_MODE_11NG_HT40MINUS) ? 20 : 0;
channelSep = (cm->mode == HAL_MODE_11NA_HT40PLUS ||
cm->mode == HAL_MODE_11NA_HT40MINUS) ? 40 : 0;
for (b = 0; b < 64*BMLEN; b++) {
if (!IS_BIT_SET(b, channelBM))
continue;
fband = &freqs[b];
lastc = 0;
for (c = fband->lowChannel + low_adj;
c <= fband->highChannel + hi_adj;
c += fband->channelSep) {
if (!(c_lo <= c && c <= c_hi)) {
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
"%s: c %u out of range [%u..%u]\n",
__func__, c, c_lo, c_hi);
continue;
}
if (next >= maxchans){
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
"%s: too many channels for channel table\n",
__func__);
goto done;
}
if ((fband->usePassScan & IS_ECM_CHAN) &&
!enableExtendedChannels) {
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
"skip ecm channel\n");
continue;
}
#if 0
if ((fband->useDfs & dfsMask) &&
(cm->flags & IEEE80211_CHAN_HT40)) {
/* NB: DFS and HT40 don't mix */
HALDEBUG(ah, HAL_DEBUG_REGDOMAIN,
"skip HT40 chan, DFS required\n");
continue;
}
#endif
/*
* Make sure that channel separation
* meets the requirement.
*/
if (lastc && channelSep &&
(c-lastc) < channelSep)
continue;
lastc = c;
OS_MEMZERO(ic, sizeof(*ic));
ic->ic_freq = c;
ic->ic_flags = cm->flags;
ic->ic_maxregpower = fband->powerDfs;
ath_hal_getpowerlimits(ah, ic);
ic->ic_maxantgain = fband->antennaMax;
if (fband->usePassScan & pscan)
ic->ic_flags |= IEEE80211_CHAN_PASSIVE;
if (fband->useDfs & dfsMask)
ic->ic_flags |= IEEE80211_CHAN_DFS;
if (IEEE80211_IS_CHAN_5GHZ(ic) &&
(rdflags & DISALLOW_ADHOC_11A))
ic->ic_flags |= IEEE80211_CHAN_NOADHOC;
if (IEEE80211_IS_CHAN_TURBO(ic) &&
(rdflags & DISALLOW_ADHOC_11A_TURB))
ic->ic_flags |= IEEE80211_CHAN_NOADHOC;
if (rdflags & NO_HOSTAP)
ic->ic_flags |= IEEE80211_CHAN_NOHOSTAP;
if (rdflags & LIMIT_FRAME_4MS)
ic->ic_flags |= IEEE80211_CHAN_4MSXMIT;
if (rdflags & NEED_NFC)
ic->ic_flags |= CHANNEL_NFCREQUIRED;
ic++, next++;
}
if (cm->flags & IEEE80211_CHAN_5GHZ)
rd = rd5GHz;
else if (cm->flags & IEEE80211_CHAN_2GHZ)
rd = rd2GHz;
else {
ath_hal_printf(ah, "%s: Unkonwn HAL flags 0x%x\n",
__func__, cm->flags);
return HAL_EINVAL;
}
add_chanlist_mode(ah, chans, maxchans, nchans, cm,
rd, enableExtendedChannels);
if (*nchans >= maxchans)
goto done;
}
done:
*nchans = next;
/* NB: pcountry set above by getregstate */
if (prd2GHz != AH_NULL)
*prd2GHz = rd2GHz;
if (prd5GHz != AH_NULL)
*prd5GHz = rd5GHz;
return HAL_OK;
#undef HAL_MODE_11A_ALL
#undef CHANNEL_HALF_BW
#undef CHANNEL_QUARTER_BW
}
/*
@@ -613,7 +679,9 @@ ath_hal_mapgsm(int sku, int freq)
return 1544 + freq;
if (sku == SKU_SR9)
return 3344 - freq;
HALDEBUG_G(AH_NULL, HAL_DEBUG_ANY,
if (sku == SKU_XC900M)
return 1517 + freq;
HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
"%s: cannot map freq %u unknown gsm sku %u\n",
__func__, freq, sku);
return freq;
@@ -727,6 +795,7 @@ ath_hal_set_channels(struct ath_hal *ah,
case SKU_SR9:
case SKU_XR9:
case SKU_GZ901:
case SKU_XC900M:
/*
* Map 900MHz sku's. The frequencies will be mapped
* according to the sku to compensate for the down-converter.
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_regdomain.h
+4 -3
View File
@@ -15,7 +15,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_regdomain.h 300246 2016-05-19 23:00:30Z avos $
*/
#ifndef __AH_REGDOMAIN_H__
#define __AH_REGDOMAIN_H__
@@ -157,7 +157,8 @@ typedef struct regDomain {
} REG_DOMAIN;
struct cmode {
u_int mode;
u_int flags;
u_int mode;
u_int flags;
REG_DMN_FREQ_BAND *freqs;
};
#endif
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_regdomain/ah_rd_ctry.h
+1 -1
View File
@@ -15,7 +15,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_ctry.h 224226 2011-07-20 12:46:58Z adrian $
*/
#ifndef __AH_REGDOMAIN_CTRY_H__
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_regdomain/ah_rd_domains.h
+26 -1
View File
@@ -15,7 +15,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_domains.h 248677 2013-03-24 04:42:56Z adrian $
*/
#ifndef __AH_REGDOMAIN_DOMAINS_H__
@@ -741,6 +741,31 @@ static REG_DOMAIN regDomains[] = {
WG1_2467_2467),
.chan11g_turbo = BM1(T3_2437_2437)},
{.regDmnEnum = WORC_WORLD,
.conformanceTestLimit = NO_CTL,
.dfsMask = DFS_FCC3 | DFS_ETSI,
.pscan = PSCAN_WWR,
.flags = ADHOC_PER_11D,
.chan11a = BM4(W1_5260_5320,
W1_5180_5240,
W1_5745_5825,
W1_5500_5700),
.chan11b = BM7(W1_2412_2412,
W1_2437_2442,
W1_2462_2462,
W1_2472_2472,
W1_2417_2432,
W1_2447_2457,
W1_2467_2467),
.chan11g = BM7(WG1_2412_2412,
WG1_2437_2442,
WG1_2462_2462,
WG1_2472_2472,
WG1_2417_2432,
WG1_2447_2457,
WG1_2467_2467),
.chan11g_turbo = BM1(T3_2437_2437)},
{.regDmnEnum = NULL1,
.conformanceTestLimit = NO_CTL,
}
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_regdomain/ah_rd_freqbands.h
+1 -1
View File
@@ -15,7 +15,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_freqbands.h 219442 2011-03-10 03:13:56Z adrian $
*/
#ifndef __AH_REGDOMAIN_FREQBANDS_H__
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_regdomain/ah_rd_regenum.h
+2 -1
View File
@@ -15,7 +15,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_regenum.h 262375 2014-02-23 18:07:17Z hiren $
*/
#ifndef __AH_REGDOMAIN_REGENUM_H__
@@ -51,6 +51,7 @@ enum {
FCC2_FCCA = 0x20, /* Canada */
FCC2_WORLD = 0x21, /* Australia & HK */
FCC2_ETSIC = 0x22,
FCC_UBNT = 0x2A, /* Ubiquity PicoStation M2HP */
FRANCE_RES = 0x31, /* Legacy France for OEM */
FCC3_FCCA = 0x3A, /* USA & Canada w/5470 band, 11h, DFS enabled */
FCC3_WORLD = 0x3B, /* USA & Canada w/5470 band, 11h, DFS enabled */
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_regdomain/ah_rd_regmap.h
+2 -1
View File
@@ -15,7 +15,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_regmap.h 248677 2013-03-24 04:42:56Z adrian $
*/
#ifndef __AH_REGDOMAIN_REGMAP_H__
@@ -129,6 +129,7 @@ static REG_DMN_PAIR_MAPPING regDomainPairs[] = {
{WOR9_WORLD, WOR9_WORLD, WOR9_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
{WORA_WORLD, WORA_WORLD, WORA_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
{WORB_WORLD, WORB_WORLD, WORB_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
{WORC_WORLD, WORC_WORLD, WORC_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
};
#endif
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ah_soc.h
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ah_soc.h 204644 2010-03-03 17:32:32Z rpaulo $
*/
#ifndef _ATH_AH_SOC_H_
#define _ATH_AH_SOC_H_
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/ar5210.h
+22 -6
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5210/ar5210.h 290612 2015-11-09 15:59:42Z adrian $
*/
#ifndef _ATH_AR5210_H_
#define _ATH_AR5210_H_
@@ -108,7 +108,6 @@ struct ath_hal_5210 {
uint32_t ah_txDescInterruptMask;
uint32_t ah_txEolInterruptMask;
uint32_t ah_txUrnInterruptMask;
HAL_POWER_MODE ah_powerMode;
uint8_t ah_bssid[IEEE80211_ADDR_LEN];
HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; /* beacon+cab+data */
/*
@@ -121,6 +120,8 @@ struct ath_hal_5210 {
u_int ah_slottime; /* user-specified slot time */
u_int ah_acktimeout; /* user-specified ack timeout */
u_int ah_ctstimeout; /* user-specified cts timeout */
uint16_t ah_associd; /* association id */
};
#define AH5210(ah) ((struct ath_hal_5210 *)(ah))
@@ -128,7 +129,8 @@ struct ath_hal;
extern void ar5210Detach(struct ath_hal *ah);
extern HAL_BOOL ar5210Reset(struct ath_hal *, HAL_OPMODE,
struct ieee80211_channel *, HAL_BOOL bChannelChange, HAL_STATUS *);
struct ieee80211_channel *, HAL_BOOL bChannelChange,
HAL_RESET_TYPE, HAL_STATUS *);
extern void ar5210SetPCUConfig(struct ath_hal *);
extern HAL_BOOL ar5210PhyDisable(struct ath_hal *);
extern HAL_BOOL ar5210Disable(struct ath_hal *);
@@ -171,7 +173,8 @@ extern HAL_BOOL ar5210SetupXTxDesc(struct ath_hal *, struct ath_desc *,
u_int txRate2, u_int txRetries2,
u_int txRate3, u_int txRetries3);
extern HAL_BOOL ar5210FillTxDesc(struct ath_hal *, struct ath_desc *,
u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList,
u_int descId, u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
const struct ath_desc *ds0);
extern HAL_STATUS ar5210ProcTxDesc(struct ath_hal *,
struct ath_desc *, struct ath_tx_status *);
@@ -179,9 +182,15 @@ extern void ar5210GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
extern void ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
extern HAL_BOOL ar5210GetTxCompletionRates(struct ath_hal *ah,
const struct ath_desc *, int *rates, int *tries);
extern void ar5210SetTxDescLink(struct ath_hal *ah, void *ds,
uint32_t link);
extern void ar5210GetTxDescLink(struct ath_hal *ah, void *ds,
uint32_t *link);
extern void ar5210GetTxDescLinkPtr(struct ath_hal *ah, void *ds,
uint32_t **linkptr);
extern uint32_t ar5210GetRxDP(struct ath_hal *);
extern void ar5210SetRxDP(struct ath_hal *, uint32_t rxdp);
extern uint32_t ar5210GetRxDP(struct ath_hal *, HAL_RX_QUEUE);
extern void ar5210SetRxDP(struct ath_hal *, uint32_t rxdp, HAL_RX_QUEUE);
extern void ar5210EnableReceive(struct ath_hal *);
extern HAL_BOOL ar5210StopDmaReceive(struct ath_hal *);
extern void ar5210StartPcuReceive(struct ath_hal *);
@@ -249,6 +258,13 @@ extern HAL_BOOL ar5210SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
extern HAL_BOOL ar5210GetDiagState(struct ath_hal *ah, int request,
const void *args, uint32_t argsize,
void **result, uint32_t *resultsize);
extern uint32_t ar5210Get11nExtBusy(struct ath_hal *);
extern HAL_BOOL ar5210GetMibCycleCounts(struct ath_hal *,
HAL_SURVEY_SAMPLE *);
extern void ar5210SetChainMasks(struct ath_hal *, uint32_t, uint32_t);
extern void ar5210EnableDfs(struct ath_hal *, HAL_PHYERR_PARAM *);
extern void ar5210GetDfsThresh(struct ath_hal *, HAL_PHYERR_PARAM *);
extern void ar5210UpdateDiagReg(struct ath_hal *ah, uint32_t val);
extern u_int ar5210GetKeyCacheSize(struct ath_hal *);
extern HAL_BOOL ar5210IsKeyCacheEntryValid(struct ath_hal *, uint16_t);
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/ar5210_attach.c
+28 -9
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5210/ar5210_attach.c 272292 2014-09-30 03:19:29Z adrian $
*/
#include "opt_ah.h"
@@ -33,7 +33,8 @@ static HAL_BOOL ar5210GetChannelEdges(struct ath_hal *,
static HAL_BOOL ar5210GetChipPowerLimits(struct ath_hal *ah,
struct ieee80211_channel *chan);
static void ar5210ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
static void ar5210ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
HAL_BOOL power_on);
static void ar5210DisablePCIE(struct ath_hal *ah);
static const struct ath_hal_private ar5210hal = {{
@@ -74,6 +75,9 @@ static const struct ath_hal_private ar5210hal = {{
.ah_getTxIntrQueue = ar5210GetTxIntrQueue,
.ah_reqTxIntrDesc = ar5210IntrReqTxDesc,
.ah_getTxCompletionRates = ar5210GetTxCompletionRates,
.ah_setTxDescLink = ar5210SetTxDescLink,
.ah_getTxDescLink = ar5210GetTxDescLink,
.ah_getTxDescLinkPtr = ar5210GetTxDescLinkPtr,
/* RX Functions */
.ah_getRxDP = ar5210GetRxDP,
@@ -129,8 +133,15 @@ static const struct ath_hal_private ar5210hal = {{
.ah_getAckCTSRate = ar5210GetAckCTSRate,
.ah_setCTSTimeout = ar5210SetCTSTimeout,
.ah_getCTSTimeout = ar5210GetCTSTimeout,
.ah_setDecompMask = ar5210SetDecompMask,
.ah_setCoverageClass = ar5210SetCoverageClass,
.ah_setDecompMask = ar5210SetDecompMask,
.ah_setCoverageClass = ar5210SetCoverageClass,
.ah_get11nExtBusy = ar5210Get11nExtBusy,
.ah_getMibCycleCounts = ar5210GetMibCycleCounts,
.ah_setChainMasks = ar5210SetChainMasks,
.ah_enableDfs = ar5210EnableDfs,
.ah_getDfsThresh = ar5210GetDfsThresh,
/* XXX procRadarEvent */
/* XXX isFastClockEnabled */
/* Key Cache Functions */
.ah_getKeyCacheSize = ar5210GetKeyCacheSize,
@@ -172,7 +183,7 @@ static HAL_BOOL ar5210FillCapabilityInfo(struct ath_hal *ah);
*/
static struct ath_hal *
ar5210Attach(uint16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh,
uint16_t *eepromdata, HAL_STATUS *status)
uint16_t *eepromdata, HAL_OPS_CONFIG *ah_config, HAL_STATUS *status)
{
#define N(a) (sizeof(a)/sizeof(a[0]))
struct ath_hal_5210 *ahp;
@@ -182,14 +193,14 @@ ar5210Attach(uint16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh,
HAL_STATUS ecode;
int i;
HALDEBUG_G(AH_NULL, HAL_DEBUG_ATTACH,
HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH,
"%s: devid 0x%x sc %p st %p sh %p\n", __func__, devid,
sc, (void*) st, (void*) sh);
/* NB: memory is returned zero'd */
ahp = ath_hal_malloc(sizeof (struct ath_hal_5210));
if (ahp == AH_NULL) {
HALDEBUG_G(AH_NULL, HAL_DEBUG_ANY,
HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
"%s: no memory for state block\n", __func__);
ecode = HAL_ENOMEM;
goto bad;
@@ -208,7 +219,7 @@ ar5210Attach(uint16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh,
AH_PRIVATE(ah)->ah_powerLimit = AR5210_MAX_RATE_POWER;
AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */
ahp->ah_powerMode = HAL_PM_UNDEFINED;
ah->ah_powerMode = HAL_PM_UNDEFINED;
ahp->ah_staId1Defaults = 0;
ahp->ah_rssiThr = INIT_RSSI_THR;
ahp->ah_sifstime = (u_int) -1;
@@ -326,7 +337,7 @@ ar5210GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan)
}
static void
ar5210ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
ar5210ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
{
}
@@ -351,6 +362,8 @@ ar5210FillCapabilityInfo(struct ath_hal *ah)
pCap->halSleepAfterBeaconBroken = AH_TRUE;
pCap->halPSPollBroken = AH_FALSE;
pCap->halNumMRRetries = 1; /* No hardware MRR support */
pCap->halNumTxMaps = 1; /* Single TX ptr per descr */
pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
pCap->halKeyCacheSize = 64;
@@ -359,6 +372,12 @@ ar5210FillCapabilityInfo(struct ath_hal *ah)
pCap->halChanHalfRate = AH_FALSE;
pCap->halChanQuarterRate = AH_FALSE;
/*
* RSSI uses the combined field; some 11n NICs may use
* the control chain RSSI.
*/
pCap->halUseCombinedRadarRssi = AH_TRUE;
if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL)) {
/*
* Setup initial rfsilent settings based on the EEPROM
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/ar5210_beacon.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5210/ar5210_beacon.c 225444 2011-09-08 01:23:05Z adrian $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/ar5210_interrupts.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5210/ar5210_interrupts.c 192397 2009-05-19 17:35:15Z sam $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/ar5210_keycache.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5210/ar5210_keycache.c 204644 2010-03-03 17:32:32Z rpaulo $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/ar5210_misc.c
+59 -4
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5210/ar5210_misc.c 264899 2014-04-24 23:11:18Z adrian $
*/
#include "opt_ah.h"
@@ -315,6 +315,7 @@ ar5210WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
/* XXX save bssid for possible re-use on reset */
OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
ahp->ah_associd = assocId;
OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
((assocId & 0x3fff)<<AR_BSS_ID1_AID_S));
@@ -576,8 +577,6 @@ ar5210MibEvent(struct ath_hal *ah, const HAL_NODE_STATS *stats)
{
}
#define AR_DIAG_SW_DIS_CRYPTO (AR_DIAG_SW_DIS_ENC | AR_DIAG_SW_DIS_DEC)
HAL_STATUS
ar5210GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
uint32_t capability, uint32_t *result)
@@ -585,7 +584,11 @@ ar5210GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
switch (type) {
case HAL_CAP_CIPHER: /* cipher handled in hardware */
#if 0
return (capability == HAL_CIPHER_WEP ? HAL_OK : HAL_ENOTSUPP);
#else
return HAL_ENOTSUPP;
#endif
default:
return ath_hal_getcapability(ah, type, capability, result);
}
@@ -608,7 +611,7 @@ ar5210SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
#else
AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */
#endif
OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
ar5210UpdateDiagReg(ah, AH_PRIVATE(ah)->ah_diagreg);
return AH_TRUE;
case HAL_CAP_RXORN_FATAL: /* HAL_INT_RXORN treated as fatal */
return AH_FALSE; /* NB: disallow */
@@ -646,3 +649,55 @@ ar5210GetDiagState(struct ath_hal *ah, int request,
return ath_hal_getdiagstate(ah, request,
args, argsize, result, resultsize);
}
/*
* Return what percentage of the extension channel is busy.
* This is always disabled for AR5210 series NICs.
*/
uint32_t
ar5210Get11nExtBusy(struct ath_hal *ah)
{
return (0);
}
/*
* There's no channel survey support for the AR5210.
*/
HAL_BOOL
ar5210GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample)
{
return (AH_FALSE);
}
void
ar5210SetChainMasks(struct ath_hal *ah, uint32_t txchainmask,
uint32_t rxchainmask)
{
}
void
ar5210EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
{
}
void
ar5210GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
{
}
/*
* Update the diagnostic register.
*
* This merges in the diagnostic register setting with the default
* value, which may or may not involve disabling hardware encryption.
*/
void
ar5210UpdateDiagReg(struct ath_hal *ah, uint32_t val)
{
/* Disable all hardware encryption */
val |= AR_DIAG_SW_DIS_CRYPTO;
OS_REG_WRITE(ah, AR_DIAG_SW, val);
}
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/ar5210_phy.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5210/ar5210_phy.c 191022 2009-04-13 21:01:08Z sam $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/ar5210_power.c
+9 -5
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5210/ar5210_power.c 265112 2014-04-30 02:03:13Z adrian $
*/
#include "opt_ah.h"
@@ -93,7 +93,6 @@ ar5210SetPowerModeSleep(struct ath_hal *ah, int setChip)
HAL_BOOL
ar5210SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)
{
struct ath_hal_5210 *ahp = AH5210(ah);
#ifdef AH_DEBUG
static const char* modes[] = {
"AWAKE",
@@ -105,25 +104,30 @@ ar5210SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)
int status = AH_TRUE;
HALDEBUG(ah, HAL_DEBUG_POWER, "%s: %s -> %s (%s)\n", __func__,
modes[ahp->ah_powerMode], modes[mode],
modes[ah->ah_powerMode], modes[mode],
setChip ? "set chip " : "");
switch (mode) {
case HAL_PM_AWAKE:
if (setChip)
ah->ah_powerMode = mode;
status = ar5210SetPowerModeAwake(ah, setChip);
break;
case HAL_PM_FULL_SLEEP:
ar5210SetPowerModeSleep(ah, setChip);
if (setChip)
ah->ah_powerMode = mode;
break;
case HAL_PM_NETWORK_SLEEP:
ar5210SetPowerModeAuto(ah, setChip);
if (setChip)
ah->ah_powerMode = mode;
break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown power mode %u\n",
__func__, mode);
return AH_FALSE;
}
ahp->ah_powerMode = mode;
return status;
return status;
}
HAL_POWER_MODE
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/ar5210_recv.c
+9 -5
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5210/ar5210_recv.c 243317 2012-11-19 23:42:46Z adrian $
*/
#include "opt_ah.h"
@@ -30,8 +30,10 @@
* Get the RXDP.
*/
uint32_t
ar5210GetRxDP(struct ath_hal *ah)
ar5210GetRxDP(struct ath_hal *ah, HAL_RX_QUEUE qtype)
{
HALASSERT(qtype == HAL_RX_QUEUE_HP);
return OS_REG_READ(ah, AR_RXDP);
}
@@ -39,8 +41,10 @@ ar5210GetRxDP(struct ath_hal *ah)
* Set the RxDP.
*/
void
ar5210SetRxDP(struct ath_hal *ah, uint32_t rxdp)
ar5210SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype)
{
HALASSERT(qtype == HAL_RX_QUEUE_HP);
OS_REG_WRITE(ah, AR_RXDP, rxdp);
}
@@ -82,7 +86,7 @@ ar5210StopDmaReceive(struct ath_hal *ah)
void
ar5210StartPcuReceive(struct ath_hal *ah)
{
OS_REG_WRITE(ah, AR_DIAG_SW,
ar5210UpdateDiagReg(ah,
OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX));
}
@@ -92,7 +96,7 @@ ar5210StartPcuReceive(struct ath_hal *ah)
void
ar5210StopPcuReceive(struct ath_hal *ah)
{
OS_REG_WRITE(ah, AR_DIAG_SW,
ar5210UpdateDiagReg(ah,
OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX);
}
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/ar5210_reset.c
+13 -10
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c 290612 2015-11-09 15:59:42Z adrian $
*/
#include "opt_ah.h"
@@ -69,6 +69,7 @@ static void ar5210SetOperatingMode(struct ath_hal *, int opmode);
HAL_BOOL
ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,
struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
HAL_RESET_TYPE resetType,
HAL_STATUS *status)
{
#define N(a) (sizeof (a) /sizeof (a[0]))
@@ -152,8 +153,12 @@ ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,
/* Restore previous led state */
OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | ledstate);
#if 0
OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
#endif
/* BSSID, association id, ps-poll */
ar5210WriteAssocid(ah, ahp->ah_bssid, ahp->ah_associd);
OS_REG_WRITE(ah, AR_TXDP0, 0);
OS_REG_WRITE(ah, AR_TXDP1, 0);
@@ -190,7 +195,7 @@ ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,
OS_REG_WRITE(ah, AR_CLR_TMASK, 1);
OS_REG_WRITE(ah, AR_TRIG_LEV, 1); /* minimum */
OS_REG_WRITE(ah, AR_DIAG_SW, 0);
ar5210UpdateDiagReg(ah, 0);
OS_REG_WRITE(ah, AR_CFP_PERIOD, 0);
OS_REG_WRITE(ah, AR_TIMER0, 0); /* next beacon time */
@@ -285,7 +290,7 @@ ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,
if (ahp->ah_ctstimeout != (u_int) -1)
ar5210SetCTSTimeout(ah, ahp->ah_ctstimeout);
if (AH_PRIVATE(ah)->ah_diagreg != 0)
OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
ar5210UpdateDiagReg(ah, AH_PRIVATE(ah)->ah_diagreg);
AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */
@@ -454,7 +459,7 @@ ar5210PerCalibrationN(struct ath_hal *ah,
if (ichan == AH_NULL)
return AH_FALSE;
/* Disable tx and rx */
OS_REG_WRITE(ah, AR_DIAG_SW,
ar5210UpdateDiagReg(ah,
OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX));
/* Disable Beacon Enable */
@@ -551,7 +556,7 @@ ar5210PerCalibrationN(struct ath_hal *ah,
}
/* Clear tx and rx disable bit */
OS_REG_WRITE(ah, AR_DIAG_SW,
ar5210UpdateDiagReg(ah,
OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX));
/* Re-enable Beacons */
@@ -594,12 +599,10 @@ ar5210SetResetReg(struct ath_hal *ah, uint32_t resetMask, u_int delay)
if ((resetMask & AR_RC_RMAC) == 0) {
if (isBigEndian()) {
/*
* Set CFG, little-endian for register
* and descriptor accesses.
* Set CFG, little-endian for descriptor accesses.
*/
mask = INIT_CONFIG_STATUS |
AR_CFG_SWTD | AR_CFG_SWRD | AR_CFG_SWRG;
OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask));
mask = INIT_CONFIG_STATUS | AR_CFG_SWTD | AR_CFG_SWRD;
OS_REG_WRITE(ah, AR_CFG, mask);
} else
OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
}
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/ar5210_xmit.c
+41 -3
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5210/ar5210_xmit.c 243174 2012-11-17 02:39:37Z adrian $
*/
#include "opt_ah.h"
@@ -518,7 +518,8 @@ ar5210SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
ads->ds_ctl1 = 0;
if (flags & HAL_TXDESC_RTSENA) {
ads->ds_ctl0 |= AR_RTSCTSEnable;
ads->ds_ctl1 |= rtsctsDuration & AR_RTSDuration;
ads->ds_ctl1 |= (rtsctsDuration << AR_RTSDuration_S)
& AR_RTSDuration;
}
return AH_TRUE;
}
@@ -546,13 +547,17 @@ ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)
HAL_BOOL
ar5210FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, u_int descId,
u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
const struct ath_desc *ds0)
{
struct ar5210_desc *ads = AR5210DESC(ds);
uint32_t segLen = segLenList[0];
HALASSERT((segLen &~ AR_BufLen) == 0);
ds->ds_data = bufAddrList[0];
if (firstSeg) {
/*
* First descriptor, don't clobber xmit control data
@@ -630,3 +635,36 @@ ar5210GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *
{
return AH_FALSE;
}
/*
* Set the TX descriptor link pointer
*/
void
ar5210SetTxDescLink(struct ath_hal *ah, void *ds, uint32_t link)
{
struct ar5210_desc *ads = AR5210DESC(ds);
ads->ds_link = link;
}
/*
* Get the TX descriptor link pointer
*/
void
ar5210GetTxDescLink(struct ath_hal *ah, void *ds, uint32_t *link)
{
struct ar5210_desc *ads = AR5210DESC(ds);
*link = ads->ds_link;
}
/*
* Get a pointer to the TX descriptor link pointer
*/
void
ar5210GetTxDescLinkPtr(struct ath_hal *ah, void *ds, uint32_t **linkptr)
{
struct ar5210_desc *ads = AR5210DESC(ds);
*linkptr = &ads->ds_link;
}
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/ar5210desc.h
+3 -3
View File
@@ -14,13 +14,11 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5210/ar5210desc.h 243173 2012-11-17 02:39:09Z adrian $
*/
#ifndef _DEV_ATH_AR5210DESC_H
#define _DEV_ATH_AR5210DESC_H
#include "ah_desc.h"
/*
* Defintions for the DMA descriptors used by the Atheros
* AR5210/AR5211 and AR5110 Wireless Lan controller parts.
@@ -57,6 +55,7 @@ struct ar5210_desc {
#define AR_ClearDestMask 0x01000000 /* Clear destination mask bit */
#define AR_AntModeXmit 0x02000000 /* TX antenna seslection */
#define AR_FrmType 0x1c000000 /* frame type indication */
#define AR_FrmType_S 26
#define AR_Frm_Normal 0x00000000 /* normal frame */
#define AR_Frm_ATIM 0x04000000 /* ATIM frame */
#define AR_Frm_PSPOLL 0x08000000 /* PS poll frame */
@@ -71,6 +70,7 @@ struct ar5210_desc {
#define AR_EncryptKeyIdx 0x0007e000 /* ecnrypt key table index */
#define AR_EncryptKeyIdx_S 13
#define AR_RTSDuration 0xfff80000 /* lower 13bit of duration */
#define AR_RTSDuration_S 19
/* RX ds_ctl1 */
/* AR_BufLen 0x00000fff data buffer length */
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/ar5210phy.h
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5210/ar5210phy.h 204644 2010-03-03 17:32:32Z rpaulo $
*/
#ifndef _DEV_ATH_AR5210PHY_H
#define _DEV_ATH_AR5210PHY_H
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/ar5210reg.h
+2 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5210/ar5210reg.h 243317 2012-11-19 23:42:46Z adrian $
*/
#ifndef _DEV_ATH_AR5210REG_H
#define _DEV_ATH_AR5210REG_H
@@ -385,6 +385,7 @@
#define AR_DIAG_SW_SCVRAM_SEED 0x0003f800 /* fixed scrambler seed */
#define AR_DIAG_SW_DIS_SEQ_INC 0x00040000 /* seq increment disable */
#define AR_DIAG_SW_FRAME_NV0 0x00080000 /* accept frame vers != 0 */
#define AR_DIAG_SW_DIS_CRYPTO (AR_DIAG_SW_DIS_ENC | AR_DIAG_SW_DIS_DEC)
#define AR_DIAG_SW_BITS \
"\20\1DIS_WEP_ACK\2DIS_ACK\3DIS_CTS\4DIS_ENC\5DIS_DEC\6DIS_TX"\
"\7DIS_RX\10LOOP_BACK\11CORR_FCS\12CHAN_INFO\13EN_SCRAM_SEED"\
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/ar5k_0007.ini
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5210/ar5k_0007.ini 204644 2010-03-03 17:32:32Z rpaulo $
*/
/* crete register init */
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/ar5211.h
+19 -5
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5211/ar5211.h 290612 2015-11-09 15:59:42Z adrian $
*/
#ifndef _ATH_AR5211_H_
#define _ATH_AR5211_H_
@@ -119,7 +119,6 @@ struct ath_hal_5211 {
uint32_t ah_txEolInterruptMask;
uint32_t ah_txUrnInterruptMask;
HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES];
HAL_POWER_MODE ah_powerMode;
HAL_ANT_SETTING ah_diversityControl; /* antenna setting */
uint32_t ah_calibrationTime;
HAL_BOOL ah_bIQCalibration;
@@ -148,6 +147,7 @@ extern void ar5211Detach(struct ath_hal *);
extern HAL_BOOL ar5211Reset(struct ath_hal *, HAL_OPMODE,
struct ieee80211_channel *, HAL_BOOL bChannelChange,
HAL_RESET_TYPE,
HAL_STATUS *);
extern HAL_BOOL ar5211PhyDisable(struct ath_hal *);
extern HAL_BOOL ar5211Disable(struct ath_hal *);
@@ -196,7 +196,8 @@ extern HAL_BOOL ar5211SetupXTxDesc(struct ath_hal *, struct ath_desc *,
u_int txRate2, u_int txRetries2,
u_int txRate3, u_int txRetries3);
extern HAL_BOOL ar5211FillTxDesc(struct ath_hal *, struct ath_desc *,
u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList,
u_int descId, u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
const struct ath_desc *ds0);
extern HAL_STATUS ar5211ProcTxDesc(struct ath_hal *,
struct ath_desc *, struct ath_tx_status *);
@@ -204,9 +205,15 @@ extern void ar5211GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
extern void ar5211IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
extern HAL_BOOL ar5211GetTxCompletionRates(struct ath_hal *ah,
const struct ath_desc *ds0, int *rates, int *tries);
extern void ar5211SetTxDescLink(struct ath_hal *ah, void *ds,
uint32_t link);
extern void ar5211GetTxDescLink(struct ath_hal *ah, void *ds,
uint32_t *link);
extern void ar5211GetTxDescLinkPtr(struct ath_hal *ah, void *ds,
uint32_t **linkptr);
extern uint32_t ar5211GetRxDP(struct ath_hal *);
extern void ar5211SetRxDP(struct ath_hal *, uint32_t rxdp);
extern uint32_t ar5211GetRxDP(struct ath_hal *, HAL_RX_QUEUE);
extern void ar5211SetRxDP(struct ath_hal *, uint32_t rxdp, HAL_RX_QUEUE);
extern void ar5211EnableReceive(struct ath_hal *);
extern HAL_BOOL ar5211StopDmaReceive(struct ath_hal *);
extern void ar5211StartPcuReceive(struct ath_hal *);
@@ -276,6 +283,13 @@ extern HAL_BOOL ar5211SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
extern HAL_BOOL ar5211GetDiagState(struct ath_hal *ah, int request,
const void *args, uint32_t argsize,
void **result, uint32_t *resultsize);
extern uint32_t ar5211Get11nExtBusy(struct ath_hal *);
extern HAL_BOOL ar5211GetMibCycleCounts(struct ath_hal *,
HAL_SURVEY_SAMPLE *);
extern void ar5211SetChainMasks(struct ath_hal *ah, uint32_t, uint32_t);
extern void ar5211EnableDfs(struct ath_hal *, HAL_PHYERR_PARAM *);
extern void ar5211GetDfsThresh(struct ath_hal *, HAL_PHYERR_PARAM *);
extern u_int ar5211GetKeyCacheSize(struct ath_hal *);
extern HAL_BOOL ar5211IsKeyCacheEntryValid(struct ath_hal *, uint16_t);
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/ar5211_attach.c
+27 -8
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5211/ar5211_attach.c 272292 2014-09-30 03:19:29Z adrian $
*/
#include "opt_ah.h"
@@ -33,7 +33,8 @@ static HAL_BOOL ar5211GetChannelEdges(struct ath_hal *ah,
static HAL_BOOL ar5211GetChipPowerLimits(struct ath_hal *ah,
struct ieee80211_channel *chan);
static void ar5211ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
static void ar5211ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
HAL_BOOL power_off);
static void ar5211DisablePCIE(struct ath_hal *ah);
static const struct ath_hal_private ar5211hal = {{
@@ -74,6 +75,9 @@ static const struct ath_hal_private ar5211hal = {{
.ah_getTxIntrQueue = ar5211GetTxIntrQueue,
.ah_reqTxIntrDesc = ar5211IntrReqTxDesc,
.ah_getTxCompletionRates = ar5211GetTxCompletionRates,
.ah_setTxDescLink = ar5211SetTxDescLink,
.ah_getTxDescLink = ar5211GetTxDescLink,
.ah_getTxDescLinkPtr = ar5211GetTxDescLinkPtr,
/* RX Functions */
.ah_getRxDP = ar5211GetRxDP,
@@ -129,8 +133,15 @@ static const struct ath_hal_private ar5211hal = {{
.ah_getAckCTSRate = ar5211GetAckCTSRate,
.ah_setCTSTimeout = ar5211SetCTSTimeout,
.ah_getCTSTimeout = ar5211GetCTSTimeout,
.ah_setDecompMask = ar5211SetDecompMask,
.ah_setCoverageClass = ar5211SetCoverageClass,
.ah_setDecompMask = ar5211SetDecompMask,
.ah_setCoverageClass = ar5211SetCoverageClass,
.ah_get11nExtBusy = ar5211Get11nExtBusy,
.ah_getMibCycleCounts = ar5211GetMibCycleCounts,
.ah_setChainMasks = ar5211SetChainMasks,
.ah_enableDfs = ar5211EnableDfs,
.ah_getDfsThresh = ar5211GetDfsThresh,
/* XXX procRadarEvent */
/* XXX isFastClockEnabled */
/* Key Cache Functions */
.ah_getKeyCacheSize = ar5211GetKeyCacheSize,
@@ -192,7 +203,7 @@ ar5211GetRadioRev(struct ath_hal *ah)
static struct ath_hal *
ar5211Attach(uint16_t devid, HAL_SOFTC sc,
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
HAL_STATUS *status)
HAL_OPS_CONFIG *ah_config, HAL_STATUS *status)
{
#define N(a) (sizeof(a)/sizeof(a[0]))
struct ath_hal_5211 *ahp;
@@ -201,13 +212,13 @@ ar5211Attach(uint16_t devid, HAL_SOFTC sc,
uint16_t eeval;
HAL_STATUS ecode;
HALDEBUG_G(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
__func__, sc, (void*) st, (void*) sh);
/* NB: memory is returned zero'd */
ahp = ath_hal_malloc(sizeof (struct ath_hal_5211));
if (ahp == AH_NULL) {
HALDEBUG_G(AH_NULL, HAL_DEBUG_ANY,
HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
"%s: cannot allocate memory for state block\n", __func__);
ecode = HAL_ENOMEM;
goto bad;
@@ -449,7 +460,7 @@ ar5211GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan)
}
static void
ar5211ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
ar5211ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
{
}
@@ -486,6 +497,8 @@ ar5211FillCapabilityInfo(struct ath_hal *ah)
pCap->halSleepAfterBeaconBroken = AH_TRUE;
pCap->halPSPollBroken = AH_TRUE;
pCap->halVEOLSupport = AH_TRUE;
pCap->halNumMRRetries = 1; /* No hardware MRR support */
pCap->halNumTxMaps = 1; /* Single TX ptr per descr */
pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
pCap->halKeyCacheSize = 128;
@@ -494,6 +507,12 @@ ar5211FillCapabilityInfo(struct ath_hal *ah)
pCap->halChanHalfRate = AH_FALSE;
pCap->halChanQuarterRate = AH_FALSE;
/*
* RSSI uses the combined field; some 11n NICs may use
* the control chain RSSI.
*/
pCap->halUseCombinedRadarRssi = AH_TRUE;
if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
/* NB: enabled by default */
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/ar5211_beacon.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5211/ar5211_beacon.c 225444 2011-09-08 01:23:05Z adrian $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/ar5211_interrupts.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c 192397 2009-05-19 17:35:15Z sam $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/ar5211_keycache.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c 204644 2010-03-03 17:32:32Z rpaulo $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/ar5211_misc.c
+38 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5211/ar5211_misc.c 247286 2013-02-25 22:42:43Z adrian $
*/
#include "opt_ah.h"
@@ -688,3 +688,40 @@ ar5211GetDiagState(struct ath_hal *ah, int request,
}
return AH_FALSE;
}
/*
* Return what percentage of the extension channel is busy.
* This is always disabled for AR5211 series NICs.
*/
uint32_t
ar5211Get11nExtBusy(struct ath_hal *ah)
{
return (0);
}
/*
* There's no channel survey support for the AR5211.
*/
HAL_BOOL
ar5211GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample)
{
return (AH_FALSE);
}
void
ar5211SetChainMasks(struct ath_hal *ah, uint32_t txchainmask,
uint32_t rxchainmask)
{
}
void
ar5211EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
{
}
void
ar5211GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
{
}
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/ar5211_phy.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5211/ar5211_phy.c 191022 2009-04-13 21:01:08Z sam $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/ar5211_power.c
+9 -5
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5211/ar5211_power.c 265112 2014-04-30 02:03:13Z adrian $
*/
#include "opt_ah.h"
@@ -95,7 +95,6 @@ ar5211SetPowerModeNetworkSleep(struct ath_hal *ah, int setChip)
HAL_BOOL
ar5211SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)
{
struct ath_hal_5211 *ahp = AH5211(ah);
#ifdef AH_DEBUG
static const char* modes[] = {
"AWAKE",
@@ -107,25 +106,30 @@ ar5211SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)
int status = AH_TRUE;
HALDEBUG(ah, HAL_DEBUG_POWER, "%s: %s -> %s (%s)\n", __func__,
modes[ahp->ah_powerMode], modes[mode],
modes[ah->ah_powerMode], modes[mode],
setChip ? "set chip " : "");
switch (mode) {
case HAL_PM_AWAKE:
if (setChip)
ah->ah_powerMode = mode;
status = ar5211SetPowerModeAwake(ah, setChip);
break;
case HAL_PM_FULL_SLEEP:
ar5211SetPowerModeSleep(ah, setChip);
if (setChip)
ah->ah_powerMode = mode;
break;
case HAL_PM_NETWORK_SLEEP:
ar5211SetPowerModeNetworkSleep(ah, setChip);
if (setChip)
ah->ah_powerMode = mode;
break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown power mode %u\n",
__func__, mode);
return AH_FALSE;
}
ahp->ah_powerMode = mode;
return status;
return status;
}
HAL_POWER_MODE
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/ar5211_recv.c
+7 -3
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5211/ar5211_recv.c 238278 2012-07-09 07:19:11Z adrian $
*/
#include "opt_ah.h"
@@ -30,8 +30,10 @@
* Get the RXDP.
*/
uint32_t
ar5211GetRxDP(struct ath_hal *ah)
ar5211GetRxDP(struct ath_hal *ah, HAL_RX_QUEUE qtype)
{
HALASSERT(qtype == HAL_RX_QUEUE_HP);
return OS_REG_READ(ah, AR_RXDP);
}
@@ -39,8 +41,10 @@ ar5211GetRxDP(struct ath_hal *ah)
* Set the RxDP.
*/
void
ar5211SetRxDP(struct ath_hal *ah, uint32_t rxdp)
ar5211SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype)
{
HALASSERT(qtype == HAL_RX_QUEUE_HP);
OS_REG_WRITE(ah, AR_RXDP, rxdp);
HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
}
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/ar5211_reset.c
+6 -7
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5211/ar5211_reset.c 298939 2016-05-02 19:56:48Z pfg $
*/
#include "opt_ah.h"
@@ -154,6 +154,7 @@ static void ar5211SetOperatingMode(struct ath_hal *, int opmode);
HAL_BOOL
ar5211Reset(struct ath_hal *ah, HAL_OPMODE opmode,
struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
HAL_RESET_TYPE resetType,
HAL_STATUS *status)
{
uint32_t softLedCfg, softLedState;
@@ -764,12 +765,10 @@ ar5211SetResetReg(struct ath_hal *ah, uint32_t resetMask)
if ((resetMask & AR_RC_MAC) == 0) {
if (isBigEndian()) {
/*
* Set CFG, little-endian for register
* and descriptor accesses.
* Set CFG, little-endian for descriptor accesses.
*/
mask = INIT_CONFIG_STATUS |
AR_CFG_SWTD | AR_CFG_SWRD | AR_CFG_SWRG;
OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask));
mask = INIT_CONFIG_STATUS | AR_CFG_SWTD | AR_CFG_SWRD;
OS_REG_WRITE(ah, AR_CFG, mask);
} else
OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
}
@@ -914,7 +913,7 @@ getNoiseFloorThresh(struct ath_hal *ah, const struct ieee80211_channel *chan,
}
/*
* Read the NF and check it against the noise floor threshhold
* Read the NF and check it against the noise floor threshold
*
* Returns: TRUE if the NF is good
*/
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/ar5211_xmit.c
+30 -2
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c 239051 2012-08-05 10:12:27Z adrian $
*/
#include "opt_ah.h"
@@ -577,10 +577,14 @@ ar5211IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)
HAL_BOOL
ar5211FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, u_int qcuId,
u_int descId, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
const struct ath_desc *ds0)
{
struct ar5211_desc *ads = AR5211DESC(ds);
uint32_t segLen = segLenList[0];
ds->ds_data = bufAddrList[0];
HALASSERT((segLen &~ AR_BufLen) == 0);
@@ -671,3 +675,27 @@ ar5211GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *
return AH_FALSE;
}
void
ar5211SetTxDescLink(struct ath_hal *ah, void *ds, uint32_t link)
{
struct ar5211_desc *ads = AR5211DESC(ds);
ads->ds_link = link;
}
void
ar5211GetTxDescLink(struct ath_hal *ah, void *ds, uint32_t *link)
{
struct ar5211_desc *ads = AR5211DESC(ds);
*link = ads->ds_link;
}
void
ar5211GetTxDescLinkPtr(struct ath_hal *ah, void *ds, uint32_t **linkptr)
{
struct ar5211_desc *ads = AR5211DESC(ds);
*linkptr = &ads->ds_link;
}
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/ar5211desc.h
+1 -3
View File
@@ -14,13 +14,11 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5211/ar5211desc.h 243249 2012-11-18 20:41:46Z adrian $
*/
#ifndef _DEV_ATH_AR5211DESC_H
#define _DEV_ATH_AR5211DESC_H
#include "ah_desc.h"
/*
* Defintions for the DMA descriptors used by the Atheros
* AR5211 and AR5110 Wireless Lan controller parts.
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/ar5211phy.h
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5211/ar5211phy.h 204644 2010-03-03 17:32:32Z rpaulo $
*/
#ifndef _DEV_ATH_AR5211PHY_H
#define _DEV_ATH_AR5211PHY_H
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/ar5211reg.h
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5211/ar5211reg.h 228980 2011-12-30 02:58:37Z dim $
*/
#ifndef _DEV_ATH_AR5211REG_H
#define _DEV_ATH_AR5211REG_H
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/boss.ini
Executable → Regular
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5211/boss.ini 245952 2013-01-26 22:08:21Z pfg $
*/
/* Auto Generated PCI Register Writes. Created: 09/12/02 */
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar2316.c
+3 -3
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar2316.c 298939 2016-05-02 19:56:48Z pfg $
*/
#include "opt_ah.h"
@@ -373,9 +373,9 @@ ar2316getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
* change pwr_I_0 to signed 5-bits.
*/
int16_t Pmin_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
/* to accomodate -ve power levels later on. */
/* to accommodate -ve power levels later on. */
int16_t Pmax_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
/* to accomodate -ve power levels later on */
/* to accommodate -ve power levels later on */
uint16_t numVpd = 0;
uint16_t Vpd_step;
int16_t tmpVal ;
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar2317.c
+3 -3
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar2317.c 298939 2016-05-02 19:56:48Z pfg $
*/
#include "opt_ah.h"
@@ -351,9 +351,9 @@ ar2317getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
* change pwr_I_0 to signed 5-bits.
*/
int16_t Pmin_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
/* to accomodate -ve power levels later on. */
/* to accommodate -ve power levels later on. */
int16_t Pmax_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
/* to accomodate -ve power levels later on */
/* to accommodate -ve power levels later on */
uint16_t numVpd = 0;
uint16_t Vpd_step;
int16_t tmpVal ;
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar2413.c
+3 -3
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar2413.c 298939 2016-05-02 19:56:48Z pfg $
*/
#include "opt_ah.h"
@@ -367,9 +367,9 @@ ar2413getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
* change pwr_I_0 to signed 5-bits.
*/
int16_t Pmin_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
/* to accomodate -ve power levels later on. */
/* to accommodate -ve power levels later on. */
int16_t Pmax_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
/* to accomodate -ve power levels later on */
/* to accommodate -ve power levels later on */
uint16_t numVpd = 0;
uint16_t Vpd_step;
int16_t tmpVal ;
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar2425.c
+3 -3
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar2425.c 298939 2016-05-02 19:56:48Z pfg $
*/
#include "opt_ah.h"
@@ -372,9 +372,9 @@ ar2425getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
* change pwr_I_0 to signed 5-bits.
*/
static int16_t Pmin_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
/* to accomodate -ve power levels later on. */
/* to accommodate -ve power levels later on. */
static int16_t Pmax_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
/* to accomodate -ve power levels later on */
/* to accommodate -ve power levels later on */
uint16_t numVpd = 0;
uint16_t Vpd_step;
int16_t tmpVal ;
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5111.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5111.c 187831 2009-01-28 18:00:22Z sam $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5112.c
+2 -2
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5112.c 225883 2011-09-30 05:17:57Z adrian $
*/
#include "opt_ah.h"
@@ -611,7 +611,7 @@ getFullPwrTable(uint16_t numPcdacs, uint16_t *pcdacs, int16_t *power, int16_t ma
uint16_t idxR = 1;
if (numPcdacs < 2) {
HALDEBUG_G(AH_NULL, HAL_DEBUG_ANY,
HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
"%s: at least 2 pcdac values needed [%d]\n",
__func__, numPcdacs);
return AH_FALSE;
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212.h
+36 -8
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212.h 290612 2015-11-09 15:59:42Z adrian $
*/
#ifndef _ATH_AR5212_H_
#define _ATH_AR5212_H_
@@ -200,6 +200,7 @@ struct ar5212AniState {
#define HAL_ANI_ENA 0x00000001 /* ANI operation enabled */
#define HAL_RSSI_ANI_ENA 0x00000002 /* rssi-based processing ena'd*/
#if 0
struct ar5212Stats {
uint32_t ast_ani_niup; /* ANI increased noise immunity */
uint32_t ast_ani_nidown; /* ANI decreased noise immunity */
@@ -219,6 +220,7 @@ struct ar5212Stats {
HAL_MIB_STATS ast_mibstats; /* MIB counter stats */
HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */
};
#endif
/*
* NF Cal history buffer
@@ -252,12 +254,13 @@ struct ath_hal_5212 {
uint8_t ah_macaddr[IEEE80211_ADDR_LEN];
uint8_t ah_bssid[IEEE80211_ADDR_LEN];
uint8_t ah_bssidmask[IEEE80211_ADDR_LEN];
uint16_t ah_assocId;
/*
* Runtime state.
*/
uint32_t ah_maskReg; /* copy of AR_IMR */
struct ar5212Stats ah_stats; /* various statistics */
HAL_ANI_STATS ah_stats; /* various statistics */
RF_HAL_FUNCS *ah_rfHal;
uint32_t ah_txDescMask; /* mask for TXDESC */
uint32_t ah_txOkInterruptMask;
@@ -269,7 +272,6 @@ struct ath_hal_5212 {
uint32_t ah_intrTxqs; /* tx q interrupt state */
/* decomp mask array */
uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE];
HAL_POWER_MODE ah_powerMode;
HAL_ANT_SETTING ah_antControl; /* antenna setting */
HAL_BOOL ah_diversity; /* fast diversity setting */
enum {
@@ -333,6 +335,19 @@ struct ath_hal_5212 {
uint8_t ah_txTrigLev; /* current Tx trigger level */
uint8_t ah_maxTxTrigLev; /* max tx trigger level */
/*
* Channel Tx, Rx, Rx Clear State
*/
uint32_t ah_cycleCount;
uint32_t ah_ctlBusy;
uint32_t ah_rxBusy;
uint32_t ah_txBusy;
uint32_t ah_rx_chainmask;
uint32_t ah_tx_chainmask;
/* Used to return ANI statistics to the diagnostic API */
HAL_ANI_STATS ext_ani_stats;
};
#define AH5212(_ah) ((struct ath_hal_5212 *)(_ah))
@@ -509,14 +524,17 @@ extern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request,
void **result, uint32_t *resultsize);
extern HAL_STATUS ar5212SetQuiet(struct ath_hal *ah, uint32_t period,
uint32_t duration, uint32_t nextStart, HAL_QUIET_FLAG flag);
extern HAL_BOOL ar5212GetMibCycleCounts(struct ath_hal *,
HAL_SURVEY_SAMPLE *);
extern void ar5212SetChainMasks(struct ath_hal *, uint32_t, uint32_t);
extern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,
int setChip);
extern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah);
extern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah);
extern uint32_t ar5212GetRxDP(struct ath_hal *ath);
extern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp);
extern uint32_t ar5212GetRxDP(struct ath_hal *ath, HAL_RX_QUEUE);
extern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE);
extern void ar5212EnableReceive(struct ath_hal *ah);
extern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah);
extern void ar5212StartPcuReceive(struct ath_hal *ah);
@@ -535,7 +553,7 @@ extern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *,
extern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
HAL_STATUS *status);
HAL_RESET_TYPE, HAL_STATUS *status);
extern HAL_BOOL ar5212SetChannel(struct ath_hal *,
const struct ieee80211_channel *);
extern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode);
@@ -590,7 +608,8 @@ extern HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *,
u_int txRate2, u_int txRetries2,
u_int txRate3, u_int txRetries3);
extern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList,
u_int descId, u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
const struct ath_desc *ds0);
extern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah,
struct ath_desc *, struct ath_tx_status *);
@@ -598,6 +617,12 @@ extern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
extern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
extern HAL_BOOL ar5212GetTxCompletionRates(struct ath_hal *ah,
const struct ath_desc *ds0, int *rates, int *tries);
extern void ar5212SetTxDescLink(struct ath_hal *ah, void *ds,
uint32_t link);
extern void ar5212GetTxDescLink(struct ath_hal *ah, void *ds,
uint32_t *link);
extern void ar5212GetTxDescLinkPtr(struct ath_hal *ah, void *ds,
uint32_t **linkptr);
extern const HAL_RATE_TABLE *ar5212GetRateTable(struct ath_hal *, u_int mode);
@@ -605,7 +630,7 @@ extern void ar5212AniAttach(struct ath_hal *, const struct ar5212AniParams *,
const struct ar5212AniParams *, HAL_BOOL ena);
extern void ar5212AniDetach(struct ath_hal *);
extern struct ar5212AniState *ar5212AniGetCurrentState(struct ath_hal *);
extern struct ar5212Stats *ar5212AniGetCurrentStats(struct ath_hal *);
extern HAL_ANI_STATS *ar5212AniGetCurrentStats(struct ath_hal *);
extern HAL_BOOL ar5212AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param);
extern HAL_BOOL ar5212AniSetParams(struct ath_hal *,
const struct ar5212AniParams *, const struct ar5212AniParams *);
@@ -622,10 +647,13 @@ extern void ar5212AniReset(struct ath_hal *, const struct ieee80211_channel *,
extern HAL_BOOL ar5212IsNFCalInProgress(struct ath_hal *ah);
extern HAL_BOOL ar5212WaitNFCalComplete(struct ath_hal *ah, int i);
extern void ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
extern HAL_BOOL ar5212GetDfsDefaultThresh(struct ath_hal *ah,
HAL_PHYERR_PARAM *pe);
extern void ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
extern HAL_BOOL ar5212ProcessRadarEvent(struct ath_hal *ah,
struct ath_rx_status *rxs, uint64_t fulltsf, const char *buf,
HAL_DFS_EVENT *event);
extern HAL_BOOL ar5212IsFastClockEnabled(struct ath_hal *ah);
extern uint32_t ar5212Get11nExtBusy(struct ath_hal *ah);
#endif /* _ATH_AR5212_H_ */
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212.ini
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212.ini 204644 2010-03-03 17:32:32Z rpaulo $
*/
/* Auto Generated PCI Register Writes. Created: 09/01/04 */
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_ani.c
+49 -18
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212_ani.c 280940 2015-04-01 03:42:46Z adrian $
*/
#include "opt_ah.h"
@@ -110,7 +110,7 @@ ar5212AniGetCurrentState(struct ath_hal *ah)
/*
* Return the current statistics.
*/
struct ar5212Stats *
HAL_ANI_STATS *
ar5212AniGetCurrentStats(struct ath_hal *ah)
{
struct ath_hal_5212 *ahp = AH5212(ah);
@@ -865,16 +865,31 @@ static int32_t
ar5212AniGetListenTime(struct ath_hal *ah)
{
struct ath_hal_5212 *ahp = AH5212(ah);
struct ar5212AniState *aniState;
uint32_t txFrameCount, rxFrameCount, cycleCount;
int32_t listenTime;
struct ar5212AniState *aniState = NULL;
int32_t listenTime = 0;
int good;
HAL_SURVEY_SAMPLE hs;
txFrameCount = OS_REG_READ(ah, AR_TFCNT);
rxFrameCount = OS_REG_READ(ah, AR_RFCNT);
cycleCount = OS_REG_READ(ah, AR_CCCNT);
/*
* We shouldn't see ah_curchan be NULL, but just in case..
*/
if (AH_PRIVATE(ah)->ah_curchan == AH_NULL) {
ath_hal_printf(ah, "%s: ah_curchan = NULL?\n", __func__);
return (0);
}
aniState = ahp->ah_curani;
if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
/*
* Fetch the current statistics, squirrel away the current
* sample, bump the sequence/sample counter.
*/
OS_MEMZERO(&hs, sizeof(hs));
good = ar5212GetMibCycleCounts(ah, &hs);
ath_hal_survey_add_sample(ah, &hs);
if (ANI_ENA(ah))
aniState = ahp->ah_curani;
if (good == AH_FALSE) {
/*
* Cycle counter wrap (or initial call); it's not possible
* to accurately calculate a value because the registers
@@ -882,15 +897,29 @@ ar5212AniGetListenTime(struct ath_hal *ah)
*/
listenTime = 0;
ahp->ah_stats.ast_ani_lzero++;
} else {
int32_t ccdelta = cycleCount - aniState->cycleCount;
int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
int32_t tfdelta = txFrameCount - aniState->txFrameCount;
} else if (ANI_ENA(ah)) {
/*
* Only calculate and update the cycle count if we have
* an ANI state.
*/
int32_t ccdelta =
AH5212(ah)->ah_cycleCount - aniState->cycleCount;
int32_t rfdelta =
AH5212(ah)->ah_rxBusy - aniState->rxFrameCount;
int32_t tfdelta =
AH5212(ah)->ah_txBusy - aniState->txFrameCount;
listenTime = (ccdelta - rfdelta - tfdelta) / CLOCK_RATE;
}
aniState->cycleCount = cycleCount;
aniState->txFrameCount = txFrameCount;
aniState->rxFrameCount = rxFrameCount;
/*
* Again, only update ANI state if we have it.
*/
if (ANI_ENA(ah)) {
aniState->cycleCount = AH5212(ah)->ah_cycleCount;
aniState->rxFrameCount = AH5212(ah)->ah_rxBusy;
aniState->txFrameCount = AH5212(ah)->ah_txBusy;
}
return listenTime;
}
@@ -956,13 +985,15 @@ ar5212AniPoll(struct ath_hal *ah, const struct ieee80211_channel *chan)
const struct ar5212AniParams *params;
int32_t listenTime;
/* Always update from the MIB, for statistics gathering */
listenTime = ar5212AniGetListenTime(ah);
/* XXX can aniState be null? */
if (aniState == AH_NULL)
return;
if (!ANI_ENA(ah))
return;
listenTime = ar5212AniGetListenTime(ah);
if (listenTime < 0) {
ahp->ah_stats.ast_ani_lneg++;
/* restart ANI period if listenTime is invalid */
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_attach.c
+52 -13
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c 305614 2016-09-08 15:05:25Z pfg $
*/
#include "opt_ah.h"
@@ -29,7 +29,8 @@
#define AH_5212_COMMON
#include "ar5212/ar5212.ini"
static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
static void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
HAL_BOOL power_off);
static void ar5212DisablePCIE(struct ath_hal *ah);
static const struct ath_hal_private ar5212hal = {{
@@ -70,6 +71,9 @@ static const struct ath_hal_private ar5212hal = {{
.ah_getTxIntrQueue = ar5212GetTxIntrQueue,
.ah_reqTxIntrDesc = ar5212IntrReqTxDesc,
.ah_getTxCompletionRates = ar5212GetTxCompletionRates,
.ah_setTxDescLink = ar5212SetTxDescLink,
.ah_getTxDescLink = ar5212GetTxDescLink,
.ah_getTxDescLinkPtr = ar5212GetTxDescLinkPtr,
/* RX Functions */
.ah_getRxDP = ar5212GetRxDP,
@@ -107,6 +111,7 @@ static const struct ath_hal_private ar5212hal = {{
.ah_gpioSetIntr = ar5212GpioSetIntr,
.ah_getTsf32 = ar5212GetTsf32,
.ah_getTsf64 = ar5212GetTsf64,
.ah_setTsf64 = ar5212SetTsf64,
.ah_resetTsf = ar5212ResetTsf,
.ah_detectCardPresent = ar5212DetectCardPresent,
.ah_updateMibCounters = ar5212UpdateMibCounters,
@@ -125,15 +130,19 @@ static const struct ath_hal_private ar5212hal = {{
.ah_getAckCTSRate = ar5212GetAckCTSRate,
.ah_setCTSTimeout = ar5212SetCTSTimeout,
.ah_getCTSTimeout = ar5212GetCTSTimeout,
.ah_setDecompMask = ar5212SetDecompMask,
.ah_setCoverageClass = ar5212SetCoverageClass,
.ah_setDecompMask = ar5212SetDecompMask,
.ah_setCoverageClass = ar5212SetCoverageClass,
.ah_setQuiet = ar5212SetQuiet,
.ah_getMibCycleCounts = ar5212GetMibCycleCounts,
.ah_setChainMasks = ar5212SetChainMasks,
/* DFS Functions */
.ah_enableDfs = ar5212EnableDfs,
.ah_getDfsThresh = ar5212GetDfsThresh,
.ah_getDfsDefaultThresh = ar5212GetDfsDefaultThresh,
.ah_procRadarEvent = ar5212ProcessRadarEvent,
.ah_isFastClockEnabled = ar5212IsFastClockEnabled,
.ah_get11nExtBusy = ar5212Get11nExtBusy,
/* Key Cache Functions */
.ah_getKeyCacheSize = ar5212GetKeyCacheSize,
@@ -261,8 +270,8 @@ ar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc,
ahp->ah_acktimeout = (u_int) -1;
ahp->ah_ctstimeout = (u_int) -1;
ahp->ah_sifstime = (u_int) -1;
ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD,
ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD,
ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD;
ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD;
OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN);
#undef N
@@ -308,7 +317,7 @@ ar5212IsMacSupported(uint8_t macVersion, uint8_t macRev)
static struct ath_hal *
ar5212Attach(uint16_t devid, HAL_SOFTC sc,
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
HAL_STATUS *status)
HAL_OPS_CONFIG *ah_config, HAL_STATUS *status)
{
#define AH_EEPROM_PROTECT(ah) \
(AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT)
@@ -319,13 +328,13 @@ ar5212Attach(uint16_t devid, HAL_SOFTC sc,
uint16_t eeval;
HAL_STATUS ecode;
HALDEBUG_G(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
__func__, sc, (void*) st, (void*) sh);
/* NB: memory is returned zero'd */
ahp = ath_hal_malloc(sizeof (struct ath_hal_5212));
if (ahp == AH_NULL) {
HALDEBUG_G(AH_NULL, HAL_DEBUG_ANY,
HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
"%s: cannot allocate memory for state block\n", __func__);
*status = HAL_ENOMEM;
return AH_NULL;
@@ -368,7 +377,7 @@ ar5212Attach(uint16_t devid, HAL_SOFTC sc,
if (AH_PRIVATE(ah)->ah_ispcie) {
/* XXX: build flag to disable this? */
ath_hal_configPCIE(ah, AH_FALSE);
ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE);
}
if (!ar5212ChipTest(ah)) {
@@ -664,7 +673,7 @@ ar5212GetChannelEdges(struct ath_hal *ah,
* XXX Clean up the magic numbers.
*/
static void
ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
{
OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
@@ -779,7 +788,29 @@ ar5212FillCapabilityInfo(struct ath_hal *ah)
else
pCap->halHigh2GhzChan = 2732;
pCap->halLow5GhzChan = 4915;
/*
* For AR5111 version < 4, the lowest centre frequency supported is
* 5130MHz. For AR5111 version 4, the 4.9GHz channels are supported
* but only in 10MHz increments.
*
* In addition, the programming method is wrong - it uses the IEEE
* channel number to calculate the frequency, rather than the
* channel centre. Since half/quarter rates re-use some of the
* 5GHz channel IEEE numbers, this will result in a badly programmed
* synth.
*
* Until the relevant support is written, just limit lower frequency
* support for AR5111 so things aren't incorrectly programmed.
*
* XXX It's also possible this code doesn't correctly limit the
* centre frequencies of potential channels; this is very important
* for half/quarter rate!
*/
if (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR) {
pCap->halLow5GhzChan = 5120; /* XXX lowest centre = 5130MHz */
} else {
pCap->halLow5GhzChan = 4915;
}
pCap->halHigh5GhzChan = 6100;
pCap->halCipherCkipSupport = AH_FALSE;
@@ -818,6 +849,8 @@ ar5212FillCapabilityInfo(struct ath_hal *ah)
pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G;
pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */
pCap->halNumMRRetries = 4; /* Hardware supports 4 MRR */
pCap->halNumTxMaps = 1; /* Single TX ptr per descr */
pCap->halVEOLSupport = AH_TRUE;
pCap->halBssIdMaskSupport = AH_TRUE;
pCap->halMcastKeySrchSupport = AH_TRUE;
@@ -839,6 +872,12 @@ ar5212FillCapabilityInfo(struct ath_hal *ah)
pCap->halChanHalfRate = AH_TRUE;
pCap->halChanQuarterRate = AH_TRUE;
/*
* RSSI uses the combined field; some 11n NICs may use
* the control chain RSSI.
*/
pCap->halUseCombinedRadarRssi = AH_TRUE;
if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
/* NB: enabled by default */
@@ -846,7 +885,7 @@ ar5212FillCapabilityInfo(struct ath_hal *ah)
pCap->halRfSilentSupport = AH_TRUE;
}
/* NB: this is a guess, noone seems to know the answer */
/* NB: this is a guess, no one seems to know the answer */
ahpriv->ah_rxornIsFatal =
(AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE);
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_beacon.c
+16 -5
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212_beacon.c 243588 2012-11-27 02:18:41Z adrian $
*/
#include "opt_ah.h"
@@ -44,11 +44,21 @@ ar5212GetNextTBTT(struct ath_hal *ah)
void
ar5212SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
{
struct ath_hal_5212 *ahp = AH5212(ah);
OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);
OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);
OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);
OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);
/*
* Limit the timers to their specific resolutions:
*
* + Timer 0 - 0..15 0xffff TU
* + Timer 1 - 0..18 0x7ffff TU/8
* + Timer 2 - 0..24 0x1ffffff TU/8
* + Timer 3 - 0..15 0xffff TU
*/
OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt & 0xffff);
OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba & 0x7ffff);
OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba & 0x1ffffff);
/* XXX force nextatim to be non-zero? */
OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim & 0xffff);
/*
* Set the Beacon register after setting all timers.
*/
@@ -65,6 +75,7 @@ ar5212SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_RESET_TSF);
}
OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
ahp->ah_beaconInterval = (bt->bt_intval & HAL_BEACON_PERIOD);
}
/*
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_eeprom.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212_eeprom.c 204644 2010-03-03 17:32:32Z rpaulo $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_gpio.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c 188974 2009-02-24 00:12:16Z sam $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_interrupts.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c 201758 2010-01-07 21:01:37Z mbr $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_keycache.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c 218483 2011-02-09 15:23:16Z adrian $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_misc.c
+240 -15
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c 281128 2015-04-06 01:12:53Z adrian $
*/
#include "opt_ah.h"
@@ -218,8 +218,9 @@ ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
{
struct ath_hal_5212 *ahp = AH5212(ah);
/* XXX save bssid for possible re-use on reset */
/* save bssid for possible re-use on reset */
OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
ahp->ah_assocId = assocId;
OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
((assocId & 0x3fff)<<AR_BSS_ID1_AID_S));
@@ -842,6 +843,10 @@ ar5212GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
return HAL_OK;
case 1: /* current setting */
return ahp->ah_diversity ? HAL_OK : HAL_ENXIO;
case HAL_CAP_STRONG_DIV:
*result = OS_REG_READ(ah, AR_PHY_RESTART);
*result = MS(*result, AR_PHY_RESTART_DIV_GC);
return HAL_OK;
}
return HAL_EINVAL;
case HAL_CAP_DIAG:
@@ -949,16 +954,34 @@ ar5212SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
return AH_TRUE;
case HAL_CAP_DIVERSITY:
if (ahp->ah_phyPowerOn) {
v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
if (setting)
v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
else
v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
switch (capability) {
case 0:
return AH_FALSE;
case 1: /* setting */
if (ahp->ah_phyPowerOn) {
if (capability == HAL_CAP_STRONG_DIV) {
v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
if (setting)
v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
else
v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
}
}
ahp->ah_diversity = (setting != 0);
return AH_TRUE;
case HAL_CAP_STRONG_DIV:
if (! ahp->ah_phyPowerOn)
return AH_FALSE;
v = OS_REG_READ(ah, AR_PHY_RESTART);
v &= ~AR_PHY_RESTART_DIV_GC;
v |= SM(setting, AR_PHY_RESTART_DIV_GC);
OS_REG_WRITE(ah, AR_PHY_RESTART, v);
return AH_TRUE;
default:
return AH_FALSE;
}
ahp->ah_diversity = (setting != 0);
return AH_TRUE;
case HAL_CAP_DIAG: /* hardware diagnostic support */
/*
* NB: could split this up into virtual capabilities,
@@ -1029,6 +1052,7 @@ ar5212GetDiagState(struct ath_hal *ah, int request,
void **result, uint32_t *resultsize)
{
struct ath_hal_5212 *ahp = AH5212(ah);
HAL_ANI_STATS *astats;
(void) ahp;
if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))
@@ -1060,9 +1084,16 @@ ar5212GetDiagState(struct ath_hal *ah, int request,
0 : sizeof(struct ar5212AniState);
return AH_TRUE;
case HAL_DIAG_ANI_STATS:
*result = ar5212AniGetCurrentStats(ah);
*resultsize = (*result == AH_NULL) ?
0 : sizeof(struct ar5212Stats);
OS_MEMZERO(&ahp->ext_ani_stats, sizeof(ahp->ext_ani_stats));
astats = ar5212AniGetCurrentStats(ah);
if (astats == NULL) {
*result = NULL;
*resultsize = 0;
} else {
OS_MEMCPY(&ahp->ext_ani_stats, astats, sizeof(HAL_ANI_STATS));
*result = &ahp->ext_ani_stats;
*resultsize = sizeof(ahp->ext_ani_stats);
}
return AH_TRUE;
case HAL_DIAG_ANI_CMD:
if (argsize != 2*sizeof(uint32_t))
@@ -1089,6 +1120,7 @@ ar5212GetDiagState(struct ath_hal *ah, int request,
return AH_FALSE;
return ar5212AniSetParams(ah, args, args);
}
break;
}
return AH_FALSE;
}
@@ -1154,7 +1186,120 @@ ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
val &= ~AR_PHY_RADAR_0_INBAND;
val |= SM(pe->pe_inband, AR_PHY_RADAR_0_INBAND);
}
OS_REG_WRITE(ah, AR_PHY_RADAR_0, val | AR_PHY_RADAR_0_ENA);
if (pe->pe_enabled)
val |= AR_PHY_RADAR_0_ENA;
else
val &= ~ AR_PHY_RADAR_0_ENA;
if (IS_5413(ah)) {
if (pe->pe_blockradar == 1)
OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
AR_PHY_RADAR_2_BLOCKOFDMWEAK);
else
OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
AR_PHY_RADAR_2_BLOCKOFDMWEAK);
if (pe->pe_en_relstep_check == 1)
OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
AR_PHY_RADAR_2_ENRELSTEPCHK);
else
OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
AR_PHY_RADAR_2_ENRELSTEPCHK);
if (pe->pe_usefir128 == 1)
OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
AR_PHY_RADAR_2_USEFIR128);
else
OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
AR_PHY_RADAR_2_USEFIR128);
if (pe->pe_enmaxrssi == 1)
OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
AR_PHY_RADAR_2_ENMAXRSSI);
else
OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
AR_PHY_RADAR_2_ENMAXRSSI);
if (pe->pe_enrelpwr == 1)
OS_REG_SET_BIT(ah, AR_PHY_RADAR_2,
AR_PHY_RADAR_2_ENRELPWRCHK);
else
OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2,
AR_PHY_RADAR_2_ENRELPWRCHK);
if (pe->pe_relpwr != HAL_PHYERR_PARAM_NOVAL)
OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,
AR_PHY_RADAR_2_RELPWR, pe->pe_relpwr);
if (pe->pe_relstep != HAL_PHYERR_PARAM_NOVAL)
OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,
AR_PHY_RADAR_2_RELSTEP, pe->pe_relstep);
if (pe->pe_maxlen != HAL_PHYERR_PARAM_NOVAL)
OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2,
AR_PHY_RADAR_2_MAXLEN, pe->pe_maxlen);
}
OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
}
/*
* Parameters for the AR5212 PHY.
*/
#define AR5212_DFS_FIRPWR -35
#define AR5212_DFS_RRSSI 20
#define AR5212_DFS_HEIGHT 14
#define AR5212_DFS_PRSSI 6
#define AR5212_DFS_INBAND 4
/*
* Default parameters for the AR5413 PHY.
*/
#define AR5413_DFS_FIRPWR -34
#define AR5413_DFS_RRSSI 20
#define AR5413_DFS_HEIGHT 10
#define AR5413_DFS_PRSSI 15
#define AR5413_DFS_INBAND 6
#define AR5413_DFS_RELPWR 8
#define AR5413_DFS_RELSTEP 31
#define AR5413_DFS_MAXLEN 255
HAL_BOOL
ar5212GetDfsDefaultThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
{
if (IS_5413(ah)) {
pe->pe_firpwr = AR5413_DFS_FIRPWR;
pe->pe_rrssi = AR5413_DFS_RRSSI;
pe->pe_height = AR5413_DFS_HEIGHT;
pe->pe_prssi = AR5413_DFS_PRSSI;
pe->pe_inband = AR5413_DFS_INBAND;
pe->pe_relpwr = AR5413_DFS_RELPWR;
pe->pe_relstep = AR5413_DFS_RELSTEP;
pe->pe_maxlen = AR5413_DFS_MAXLEN;
pe->pe_usefir128 = 0;
pe->pe_blockradar = 1;
pe->pe_enmaxrssi = 1;
pe->pe_enrelpwr = 1;
pe->pe_en_relstep_check = 0;
} else {
pe->pe_firpwr = AR5212_DFS_FIRPWR;
pe->pe_rrssi = AR5212_DFS_RRSSI;
pe->pe_height = AR5212_DFS_HEIGHT;
pe->pe_prssi = AR5212_DFS_PRSSI;
pe->pe_inband = AR5212_DFS_INBAND;
pe->pe_relpwr = 0;
pe->pe_relstep = 0;
pe->pe_maxlen = 0;
pe->pe_usefir128 = 0;
pe->pe_blockradar = 0;
pe->pe_enmaxrssi = 0;
pe->pe_enrelpwr = 0;
pe->pe_en_relstep_check = 0;
}
return (AH_TRUE);
}
void
@@ -1171,11 +1316,31 @@ ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
pe->pe_height = MS(val, AR_PHY_RADAR_0_HEIGHT);
pe->pe_prssi = MS(val, AR_PHY_RADAR_0_PRSSI);
pe->pe_inband = MS(val, AR_PHY_RADAR_0_INBAND);
pe->pe_enabled = !! (val & AR_PHY_RADAR_0_ENA);
pe->pe_relpwr = 0;
pe->pe_relstep = 0;
pe->pe_maxlen = 0;
pe->pe_usefir128 = 0;
pe->pe_blockradar = 0;
pe->pe_enmaxrssi = 0;
pe->pe_enrelpwr = 0;
pe->pe_en_relstep_check = 0;
pe->pe_extchannel = AH_FALSE;
if (IS_5413(ah)) {
val = OS_REG_READ(ah, AR_PHY_RADAR_2);
pe->pe_relpwr = !! MS(val, AR_PHY_RADAR_2_RELPWR);
pe->pe_relstep = !! MS(val, AR_PHY_RADAR_2_RELSTEP);
pe->pe_maxlen = !! MS(val, AR_PHY_RADAR_2_MAXLEN);
pe->pe_usefir128 = !! (val & AR_PHY_RADAR_2_USEFIR128);
pe->pe_blockradar = !! (val & AR_PHY_RADAR_2_BLOCKOFDMWEAK);
pe->pe_enmaxrssi = !! (val & AR_PHY_RADAR_2_ENMAXRSSI);
pe->pe_enrelpwr = !! (val & AR_PHY_RADAR_2_ENRELPWRCHK);
pe->pe_en_relstep_check =
!! (val & AR_PHY_RADAR_2_ENRELSTEPCHK);
}
}
/*
@@ -1232,3 +1397,63 @@ ar5212IsFastClockEnabled(struct ath_hal *ah)
{
return AH_FALSE;
}
/*
* Return what percentage of the extension channel is busy.
* This is always disabled for AR5212 series NICs.
*/
uint32_t
ar5212Get11nExtBusy(struct ath_hal *ah)
{
return 0;
}
/*
* Channel survey support.
*/
HAL_BOOL
ar5212GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample)
{
struct ath_hal_5212 *ahp = AH5212(ah);
u_int32_t good = AH_TRUE;
/* XXX freeze/unfreeze mib counters */
uint32_t rc = OS_REG_READ(ah, AR_RCCNT);
uint32_t rf = OS_REG_READ(ah, AR_RFCNT);
uint32_t tf = OS_REG_READ(ah, AR_TFCNT);
uint32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */
if (ahp->ah_cycleCount == 0 || ahp->ah_cycleCount > cc) {
/*
* Cycle counter wrap (or initial call); it's not possible
* to accurately calculate a value because the registers
* right shift rather than wrap--so punt and return 0.
*/
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: cycle counter wrap. ExtBusy = 0\n", __func__);
good = AH_FALSE;
} else {
hsample->cycle_count = cc - ahp->ah_cycleCount;
hsample->chan_busy = rc - ahp->ah_ctlBusy;
hsample->ext_chan_busy = 0;
hsample->rx_busy = rf - ahp->ah_rxBusy;
hsample->tx_busy = tf - ahp->ah_txBusy;
}
/*
* Keep a copy of the MIB results so the next sample has something
* to work from.
*/
ahp->ah_cycleCount = cc;
ahp->ah_rxBusy = rf;
ahp->ah_ctlBusy = rc;
ahp->ah_txBusy = tf;
return (good);
}
void
ar5212SetChainMasks(struct ath_hal *ah, uint32_t tx_chainmask,
uint32_t rx_chainmask)
{
}
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_phy.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212_phy.c 191022 2009-04-13 21:01:08Z sam $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_power.c
+9 -5
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212_power.c 298939 2016-05-02 19:56:48Z pfg $
*/
#include "opt_ah.h"
@@ -51,7 +51,7 @@ ar5212SetPowerModeAwake(struct ath_hal *ah, int setChip)
* which when blindly written back with OS_REG_RMW_FIELD
* enables the MIB interrupt for the sleep performance
* counters. This can result in an interrupt storm when
* ANI is in operation as noone knows to turn off the MIB
* ANI is in operation as no one knows to turn off the MIB
* interrupt cause.
*/
scr = OS_REG_READ(ah, AR_SCR);
@@ -119,7 +119,6 @@ ar5212SetPowerModeNetworkSleep(struct ath_hal *ah, int setChip)
HAL_BOOL
ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)
{
struct ath_hal_5212 *ahp = AH5212(ah);
#ifdef AH_DEBUG
static const char* modes[] = {
"AWAKE",
@@ -131,24 +130,29 @@ ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)
int status = AH_TRUE;
HALDEBUG(ah, HAL_DEBUG_POWER, "%s: %s -> %s (%s)\n", __func__,
modes[ahp->ah_powerMode], modes[mode],
modes[ah->ah_powerMode], modes[mode],
setChip ? "set chip " : "");
switch (mode) {
case HAL_PM_AWAKE:
if (setChip)
ah->ah_powerMode = mode;
status = ar5212SetPowerModeAwake(ah, setChip);
break;
case HAL_PM_FULL_SLEEP:
ar5212SetPowerModeSleep(ah, setChip);
if (setChip)
ah->ah_powerMode = mode;
break;
case HAL_PM_NETWORK_SLEEP:
ar5212SetPowerModeNetworkSleep(ah, setChip);
if (setChip)
ah->ah_powerMode = mode;
break;
default:
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown power mode %u\n",
__func__, mode);
return AH_FALSE;
}
ahp->ah_powerMode = mode;
return status;
}
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_recv.c
+22 -7
View File
@@ -14,12 +14,13 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212_recv.c 243169 2012-11-17 02:02:36Z adrian $
*/
#include "opt_ah.h"
#include "ah.h"
#include "ah_internal.h"
#include "ah_desc.h"
#include "ar5212/ar5212.h"
#include "ar5212/ar5212reg.h"
@@ -29,8 +30,10 @@
* Get the RXDP.
*/
uint32_t
ar5212GetRxDP(struct ath_hal *ath)
ar5212GetRxDP(struct ath_hal *ath, HAL_RX_QUEUE qtype)
{
HALASSERT(qtype == HAL_RX_QUEUE_HP);
return OS_REG_READ(ath, AR_RXDP);
}
@@ -38,8 +41,10 @@ ar5212GetRxDP(struct ath_hal *ath)
* Set the RxDP.
*/
void
ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp)
ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype)
{
HALASSERT(qtype == HAL_RX_QUEUE_HP);
OS_REG_WRITE(ah, AR_RXDP, rxdp);
HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
}
@@ -272,6 +277,14 @@ ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
rs->rs_antenna = MS(ads->ds_rxstatus0, AR_RcvAntenna);
rs->rs_more = (ads->ds_rxstatus0 & AR_More) ? 1 : 0;
/*
* The AR5413 (at least) sometimes sets both AR_CRCErr and
* AR_PHYErr when reporting radar pulses. In this instance
* set HAL_RXERR_PHY as well as HAL_RXERR_CRC and
* let the driver layer figure out what to do.
*
* See PR kern/169362.
*/
if ((ads->ds_rxstatus1 & AR_FrmRcvOK) == 0) {
/*
* These four bits should not be set together. The
@@ -282,9 +295,7 @@ ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
* Consequently we filter them out here so we don't
* confuse and/or complicate drivers.
*/
if (ads->ds_rxstatus1 & AR_CRCErr)
rs->rs_status |= HAL_RXERR_CRC;
else if (ads->ds_rxstatus1 & AR_PHYErr) {
if (ads->ds_rxstatus1 & AR_PHYErr) {
u_int phyerr;
rs->rs_status |= HAL_RXERR_PHY;
@@ -293,7 +304,11 @@ ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
if (!AH5212(ah)->ah_hasHwPhyCounters &&
phyerr != HAL_PHYERR_RADAR)
ar5212AniPhyErrReport(ah, rs);
} else if (ads->ds_rxstatus1 & AR_DecryptCRCErr)
}
if (ads->ds_rxstatus1 & AR_CRCErr)
rs->rs_status |= HAL_RXERR_CRC;
else if (ads->ds_rxstatus1 & AR_DecryptCRCErr)
rs->rs_status |= HAL_RXERR_DECRYPT;
else if (ads->ds_rxstatus1 & AR_MichaelErr)
rs->rs_status |= HAL_RXERR_MIC;
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_reset.c
+167 -12
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c 298939 2016-05-02 19:56:48Z pfg $
*/
#include "opt_ah.h"
@@ -95,6 +95,16 @@ write_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
#define IS_DISABLE_FAST_ADC_CHAN(x) (((x) == 2462) || ((x) == 2467))
/*
* XXX NDIS 5.x code had MAX_RESET_WAIT set to 2000 for AP code
* and 10 for Client code
*/
#define MAX_RESET_WAIT 10
#define TX_QUEUEPEND_CHECK 1
#define TX_ENABLE_CHECK 2
#define RX_ENABLE_CHECK 4
/*
* Places the device in and out of reset and then places sane
* values in the registers based on EEPROM config, initialization
@@ -106,7 +116,9 @@ write_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
HAL_BOOL
ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
struct ieee80211_channel *chan,
HAL_BOOL bChannelChange, HAL_STATUS *status)
HAL_BOOL bChannelChange,
HAL_RESET_TYPE resetType,
HAL_STATUS *status)
{
#define N(a) (sizeof (a) / sizeof (a[0]))
#define FAIL(_code) do { ecode = _code; goto bad; } while (0)
@@ -185,6 +197,10 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM);
} else
saveFrameSeqCount = 0; /* NB: silence compiler */
/* Blank the channel survey statistics */
ath_hal_survey_clear(ah);
#if 0
/*
* XXX disable for now; this appears to sometimes cause OFDM
@@ -428,9 +444,10 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
/* Restore previous antenna */
OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
/* then our BSSID */
/* then our BSSID and associate id */
OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) |
(ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S);
/* Restore bmiss rssi & count thresholds */
OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
@@ -1104,6 +1121,76 @@ ar5212ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan)
return AH_TRUE;
}
/**************************************************************
* ar5212MacStop
*
* Disables all active QCUs and ensure that the mac is in a
* quiessence state.
*/
static HAL_BOOL
ar5212MacStop(struct ath_hal *ah)
{
HAL_BOOL status;
uint32_t count;
uint32_t pendFrameCount;
uint32_t macStateFlag;
uint32_t queue;
status = AH_FALSE;
/* Disable Rx Operation ***********************************/
OS_REG_SET_BIT(ah, AR_CR, AR_CR_RXD);
/* Disable TX Operation ***********************************/
#ifdef NOT_YET
ar5212SetTxdpInvalid(ah);
#endif
OS_REG_SET_BIT(ah, AR_Q_TXD, AR_Q_TXD_M);
/* Polling operation for completion of disable ************/
macStateFlag = TX_ENABLE_CHECK | RX_ENABLE_CHECK;
for (count = 0; count < MAX_RESET_WAIT; count++) {
if (macStateFlag & RX_ENABLE_CHECK) {
if (!OS_REG_IS_BIT_SET(ah, AR_CR, AR_CR_RXE)) {
macStateFlag &= ~RX_ENABLE_CHECK;
}
}
if (macStateFlag & TX_ENABLE_CHECK) {
if (!OS_REG_IS_BIT_SET(ah, AR_Q_TXE, AR_Q_TXE_M)) {
macStateFlag &= ~TX_ENABLE_CHECK;
macStateFlag |= TX_QUEUEPEND_CHECK;
}
}
if (macStateFlag & TX_QUEUEPEND_CHECK) {
pendFrameCount = 0;
for (queue = 0; queue < AR_NUM_DCU; queue++) {
pendFrameCount += OS_REG_READ(ah,
AR_Q0_STS + (queue * 4)) &
AR_Q_STS_PEND_FR_CNT;
}
if (pendFrameCount == 0) {
macStateFlag &= ~TX_QUEUEPEND_CHECK;
}
}
if (macStateFlag == 0) {
status = AH_TRUE;
break;
}
OS_DELAY(50);
}
if (status != AH_TRUE) {
HALDEBUG(ah, HAL_DEBUG_RESET,
"%s:Failed to stop the MAC state 0x%x\n",
__func__, macStateFlag);
}
return status;
}
/*
* Write the given reset bit mask into the reset register
*/
@@ -1113,12 +1200,75 @@ ar5212SetResetReg(struct ath_hal *ah, uint32_t resetMask)
uint32_t mask = resetMask ? resetMask : ~0;
HAL_BOOL rt;
/* XXX ar5212MacStop & co. */
/* Never reset the PCIE core */
if (AH_PRIVATE(ah)->ah_ispcie) {
resetMask &= ~AR_RC_PCI;
}
if (resetMask & (AR_RC_MAC | AR_RC_PCI)) {
/*
* To ensure that the driver can reset the
* MAC, wake up the chip
*/
rt = ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE);
if (rt != AH_TRUE) {
return rt;
}
/*
* Disable interrupts
*/
OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
OS_REG_READ(ah, AR_IER);
if (ar5212MacStop(ah) != AH_TRUE) {
/*
* Failed to stop the MAC gracefully; let's be more forceful then
*/
/* need some delay before flush any pending MMR writes */
OS_DELAY(15);
OS_REG_READ(ah, AR_RXDP);
resetMask |= AR_RC_MAC | AR_RC_BB;
/* _Never_ reset PCI Express core */
if (! AH_PRIVATE(ah)->ah_ispcie) {
resetMask |= AR_RC_PCI;
}
#if 0
/*
* Flush the park address of the PCI controller
*/
/* Read PCI slot information less than Hainan revision */
if (AH_PRIVATE(ah)->ah_bustype == HAL_BUS_TYPE_PCI) {
if (!IS_5112_REV5_UP(ah)) {
#define PCI_COMMON_CONFIG_STATUS 0x06
u_int32_t i;
u_int16_t reg16;
for (i = 0; i < 32; i++) {
ath_hal_read_pci_config_space(ah,
PCI_COMMON_CONFIG_STATUS,
&reg16, sizeof(reg16));
}
}
#undef PCI_COMMON_CONFIG_STATUS
}
#endif
} else {
/*
* MAC stopped gracefully; no need to warm-reset the PCI bus
*/
resetMask &= ~AR_RC_PCI;
/* need some delay before flush any pending MMR writes */
OS_DELAY(15);
OS_REG_READ(ah, AR_RXDP);
}
}
(void) OS_REG_READ(ah, AR_RXDP);/* flush any pending MMR writes */
OS_REG_WRITE(ah, AR_RC, resetMask);
OS_DELAY(15); /* need to wait at least 128 clocks
@@ -1129,14 +1279,13 @@ ar5212SetResetReg(struct ath_hal *ah, uint32_t resetMask)
if ((resetMask & AR_RC_MAC) == 0) {
if (isBigEndian()) {
/*
* Set CFG, little-endian for register
* and descriptor accesses.
* Set CFG, little-endian for descriptor accesses.
*/
mask = INIT_CONFIG_STATUS | AR_CFG_SWRD | AR_CFG_SWRG;
mask = INIT_CONFIG_STATUS | AR_CFG_SWRD;
#ifndef AH_NEED_DESC_SWAP
mask |= AR_CFG_SWTD;
#endif
OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask));
OS_REG_WRITE(ah, AR_CFG, mask);
} else
OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
if (ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
@@ -1236,7 +1385,7 @@ ar5212GetNfHistMid(const int16_t calData[AR512_NF_CAL_HIST_MAX])
}
/*
* Read the NF and check it against the noise floor threshhold
* Read the NF and check it against the noise floor threshold
*/
int16_t
ar5212GetNf(struct ath_hal *ah, struct ieee80211_channel *chan)
@@ -2459,6 +2608,12 @@ ar5212GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan,
powInfo[ixlo].twicePwr54, powInfo[ixhi].twicePwr54);
}
static uint32_t
udiff(uint32_t u, uint32_t v)
{
return (u >= v ? u - v : v - u);
}
/*
* Search a list for a specified value v that is within
* EEP_DELTA of the search values. Return the closest
@@ -2493,7 +2648,7 @@ ar5212GetLowerUpperValues(uint16_t v, uint16_t *lp, uint16_t listSize,
* If value is close to the current value of the list
* then target is not between values, it is one of the values
*/
if (abs(lp[0] * EEP_SCALE - target) < EEP_DELTA) {
if (udiff(lp[0] * EEP_SCALE, target) < EEP_DELTA) {
*vlo = *vhi = lp[0];
return;
}
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_rfgain.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212_rfgain.c 188197 2009-02-05 21:13:31Z sam $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212_xmit.c
+71 -10
View File
@@ -14,12 +14,13 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c 243169 2012-11-17 02:02:36Z adrian $
*/
#include "opt_ah.h"
#include "ah.h"
#include "ah_internal.h"
#include "ah_desc.h"
#include "ar5212/ar5212.h"
#include "ar5212/ar5212reg.h"
@@ -263,6 +264,7 @@ ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q)
* Assumes:
* phwChannel has been set to point to the current channel
*/
#define TU_TO_USEC(_tu) ((_tu) << 10)
HAL_BOOL
ar5212ResetTxQueue(struct ath_hal *ah, u_int q)
{
@@ -270,7 +272,7 @@ ar5212ResetTxQueue(struct ath_hal *ah, u_int q)
HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
HAL_TX_QUEUE_INFO *qi;
uint32_t cwMin, chanCwMin, value, qmisc, dmisc;
uint32_t cwMin, chanCwMin, qmisc, dmisc;
if (q >= pCap->halTotalQueues) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
@@ -409,17 +411,40 @@ ar5212ResetTxQueue(struct ath_hal *ah, u_int q)
| AR_Q_MISC_CBR_INCR_DIS1
| AR_Q_MISC_CBR_INCR_DIS0;
if (!qi->tqi_readyTime) {
if (qi->tqi_readyTime) {
HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
"%s: using tqi_readyTime\n", __func__);
OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT) |
AR_Q_RDYTIMECFG_ENA);
} else {
int value;
/*
* NB: don't set default ready time if driver
* has explicitly specified something. This is
* here solely for backwards compatibility.
*/
value = (ahp->ah_beaconInterval
/*
* XXX for now, hard-code a CAB interval of 70%
* XXX of the total beacon interval.
*/
value = (ahp->ah_beaconInterval * 70 / 100)
- (ah->ah_config.ah_sw_beacon_response_time -
ah->ah_config.ah_dma_beacon_response_time)
- ah->ah_config.ah_additional_swba_backoff) * 1024;
OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_ENA);
+ ah->ah_config.ah_dma_beacon_response_time)
- ah->ah_config.ah_additional_swba_backoff;
/*
* XXX Ensure it isn't too low - nothing lower
* XXX than 10 TU
*/
if (value < 10)
value = 10;
HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
"%s: defaulting to rdytime = %d uS\n",
__func__, value);
OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
SM(TU_TO_USEC(value), AR_Q_RDYTIMECFG_INT) |
AR_Q_RDYTIMECFG_ENA);
}
dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
AR_D_MISC_ARB_LOCKOUT_CNTRL);
@@ -481,6 +506,7 @@ ar5212ResetTxQueue(struct ath_hal *ah, u_int q)
return AH_TRUE;
}
#undef TU_TO_USEC
/*
* Get the TXDP for the specified queue
@@ -777,13 +803,17 @@ ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)
HAL_BOOL
ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, u_int qcuId,
u_int descId, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
const struct ath_desc *ds0)
{
struct ar5212_desc *ads = AR5212DESC(ds);
uint32_t segLen = segLenList[0];
HALASSERT((segLen &~ AR_BufLen) == 0);
ds->ds_data = bufAddrList[0];
if (firstSeg) {
/*
* First descriptor, don't clobber xmit control data
@@ -796,12 +826,14 @@ ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
* copy the multi-rate transmit parameters from
* the first frame for processing on completion.
*/
ads->ds_ctl0 = 0;
ads->ds_ctl1 = segLen;
#ifdef AH_NEED_DESC_SWAP
ads->ds_ctl0 = __bswap32(AR5212DESC_CONST(ds0)->ds_ctl0)
& AR_TxInterReq;
ads->ds_ctl2 = __bswap32(AR5212DESC_CONST(ds0)->ds_ctl2);
ads->ds_ctl3 = __bswap32(AR5212DESC_CONST(ds0)->ds_ctl3);
#else
ads->ds_ctl0 = AR5212DESC_CONST(ds0)->ds_ctl0 & AR_TxInterReq;
ads->ds_ctl2 = AR5212DESC_CONST(ds0)->ds_ctl2;
ads->ds_ctl3 = AR5212DESC_CONST(ds0)->ds_ctl3;
#endif
@@ -809,7 +841,12 @@ ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
/*
* Intermediate descriptor in a multi-descriptor frame.
*/
ads->ds_ctl0 = 0;
#ifdef AH_NEED_DESC_SWAP
ads->ds_ctl0 = __bswap32(AR5212DESC_CONST(ds0)->ds_ctl0)
& AR_TxInterReq;
#else
ads->ds_ctl0 = AR5212DESC_CONST(ds0)->ds_ctl0 & AR_TxInterReq;
#endif
ads->ds_ctl1 = segLen | AR_More;
ads->ds_ctl2 = 0;
ads->ds_ctl3 = 0;
@@ -939,3 +976,27 @@ ar5212GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *
return AH_TRUE;
}
void
ar5212SetTxDescLink(struct ath_hal *ah, void *ds, uint32_t link)
{
struct ar5212_desc *ads = AR5212DESC(ds);
ads->ds_link = link;
}
void
ar5212GetTxDescLink(struct ath_hal *ah, void *ds, uint32_t *link)
{
struct ar5212_desc *ads = AR5212DESC(ds);
*link = ads->ds_link;
}
void
ar5212GetTxDescLinkPtr(struct ath_hal *ah, void *ds, uint32_t **linkptr)
{
struct ar5212_desc *ads = AR5212DESC(ds);
*linkptr = &ads->ds_link;
}
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212desc.h
+1 -2
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212desc.h 243168 2012-11-17 02:00:33Z adrian $
*/
#ifndef _ATH_AR5212_DESC_H_
#define _ATH_AR5212_DESC_H_
@@ -22,7 +22,6 @@
/*
* Hardware-specific descriptor structures.
*/
#include "ah_desc.h"
/*
* AR5212-specific tx/rx descriptor definition.
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212phy.h
+14 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212phy.h 239801 2012-08-29 03:58:13Z adrian $
*/
#ifndef _DEV_ATH_AR5212PHY_H_
#define _DEV_ATH_AR5212PHY_H_
@@ -221,6 +221,19 @@
#define AR_PHY_RADAR_0_FIRPWR 0x7F000000 /* Radar firpwr threshold */
#define AR_PHY_RADAR_0_FIRPWR_S 24
/* ar5413 specific */
#define AR_PHY_RADAR_2 0x9958 /* radar detection settings */
#define AR_PHY_RADAR_2_ENRELSTEPCHK 0x00002000 /* Enable using max rssi */
#define AR_PHY_RADAR_2_ENMAXRSSI 0x00004000 /* Enable using max rssi */
#define AR_PHY_RADAR_2_BLOCKOFDMWEAK 0x00008000 /* En block OFDM weak sig as radar */
#define AR_PHY_RADAR_2_USEFIR128 0x00400000 /* En measuring pwr over 128 cycles */
#define AR_PHY_RADAR_2_ENRELPWRCHK 0x00800000 /* Enable using max rssi */
#define AR_PHY_RADAR_2_MAXLEN 0x000000FF /* Max Pulse duration threshold */
#define AR_PHY_RADAR_2_MAXLEN_S 0
#define AR_PHY_RADAR_2_RELSTEP 0x00001F00 /* Pulse relative step threshold */
#define AR_PHY_RADAR_2_RELSTEP_S 8
#define AR_PHY_RADAR_2_RELPWR 0x003F0000 /* pulse relative power threshold */
#define AR_PHY_RADAR_2_RELPWR_S 16
#define AR_PHY_SIGMA_DELTA 0x996C /* AR5312 only */
#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5212reg.h
+3 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5212reg.h 226489 2011-10-18 03:17:06Z adrian $
*/
#ifndef _DEV_ATH_AR5212REG_H_
#define _DEV_ATH_AR5212REG_H_
@@ -94,7 +94,9 @@
#define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2))
#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */
#define AR_Q_TXE_M 0x000003FF /* Mask for TXE (QCU 0-9) */
#define AR_Q_TXD 0x0880 /* MAC Transmit Queue disable */
#define AR_Q_TXD_M 0x000003FF /* Mask for TXD (QCU 0-9) */
#define AR_Q0_CBRCFG 0x08c0 /* MAC CBR configuration */
#define AR_Q1_CBRCFG 0x08c4 /* MAC CBR configuration */
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5311reg.h
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5311reg.h 204644 2010-03-03 17:32:32Z rpaulo $
*/
#ifndef _DEV_ATH_AR5311REG_H_
#define _DEV_ATH_AR5311REG_H_
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/ar5413.c
+3 -3
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5212/ar5413.c 298939 2016-05-02 19:56:48Z pfg $
*/
#include "opt_ah.h"
@@ -411,9 +411,9 @@ ar5413getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel,
* change pwr_I_0 to signed 5-bits.
*/
int16_t Pmin_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
/* to accomodate -ve power levels later on. */
/* to accommodate -ve power levels later on. */
int16_t Pmax_t2[MAX_NUM_PDGAINS_PER_CHANNEL];
/* to accomodate -ve power levels later on */
/* to accommodate -ve power levels later on */
uint16_t numVpd = 0;
uint16_t Vpd_step;
int16_t tmpVal ;
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5312/ar5312.h
+5 -3
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5312/ar5312.h 290612 2015-11-09 15:59:42Z adrian $
*/
#ifndef _ATH_AR5312_H_
#define _ATH_AR5312_H_
@@ -62,8 +62,10 @@ extern void ar5312SetupClock(struct ath_hal *ah, HAL_OPMODE opmode);
extern void ar5312RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode);
extern void ar5312DumpState(struct ath_hal *ah);
extern HAL_BOOL ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
struct ieee80211_channel *chan,
HAL_BOOL bChannelChange, HAL_STATUS *status);
struct ieee80211_channel *chan,
HAL_BOOL bChannelChange,
HAL_RESET_TYPE resetType,
HAL_STATUS *status);
extern HAL_BOOL ar5312ChipReset(struct ath_hal *ah,
struct ieee80211_channel *chan);
extern HAL_BOOL ar5312SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5312/ar5312_attach.c
+4 -4
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5312/ar5312_attach.c 272292 2014-09-30 03:19:29Z adrian $
*/
#include "opt_ah.h"
@@ -62,7 +62,7 @@ ar5312AniSetup(struct ath_hal *ah)
static struct ath_hal *
ar5312Attach(uint16_t devid, HAL_SOFTC sc,
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
HAL_STATUS *status)
HAL_OPS_CONFIG *ah_config, HAL_STATUS *status)
{
struct ath_hal_5212 *ahp = AH_NULL;
struct ath_hal *ah;
@@ -71,13 +71,13 @@ ar5312Attach(uint16_t devid, HAL_SOFTC sc,
uint16_t eeval;
HAL_STATUS ecode;
HALDEBUG_G(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
__func__, sc, st, (void*) sh);
/* NB: memory is returned zero'd */
ahp = ath_hal_malloc(sizeof (struct ath_hal_5212));
if (ahp == AH_NULL) {
HALDEBUG_G(AH_NULL, HAL_DEBUG_ANY,
HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
"%s: cannot allocate memory for state block\n", __func__);
*status = HAL_ENOMEM;
return AH_NULL;
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5312/ar5312_eeprom.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5312/ar5312_eeprom.c 204644 2010-03-03 17:32:32Z rpaulo $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5312/ar5312_gpio.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c 188974 2009-02-24 00:12:16Z sam $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5312/ar5312_interrupts.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5312/ar5312_interrupts.c 204644 2010-03-03 17:32:32Z rpaulo $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5312/ar5312_misc.c
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5312/ar5312_misc.c 204644 2010-03-03 17:32:32Z rpaulo $
*/
#include "opt_ah.h"
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5312/ar5312_power.c
+3 -4
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5312/ar5312_power.c 262969 2014-03-10 06:03:35Z adrian $
*/
#include "opt_ah.h"
@@ -71,7 +71,6 @@ ar5312SetPowerModeNetworkSleep(struct ath_hal *ah, int setChip)
HAL_BOOL
ar5312SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)
{
struct ath_hal_5212 *ahp = AH5212(ah);
#ifdef AH_DEBUG
static const char* modes[] = {
"AWAKE",
@@ -83,7 +82,7 @@ ar5312SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)
int status = AH_TRUE;
HALDEBUG(ah, HAL_DEBUG_POWER, "%s: %s -> %s (%s)\n", __func__,
modes[ahp->ah_powerMode], modes[mode],
modes[ah->ah_powerMode], modes[mode],
setChip ? "set chip " : "");
switch (mode) {
case HAL_PM_AWAKE:
@@ -100,7 +99,7 @@ ar5312SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)
__func__, mode);
return AH_FALSE;
}
ahp->ah_powerMode = mode;
ah->ah_powerMode = mode;
return status;
}
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5312/ar5312_reset.c
+5 -4
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5312/ar5312_reset.c 290612 2015-11-09 15:59:42Z adrian $
*/
#include "opt_ah.h"
@@ -88,7 +88,9 @@ write_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
HAL_BOOL
ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
struct ieee80211_channel *chan,
HAL_BOOL bChannelChange, HAL_STATUS *status)
HAL_BOOL bChannelChange,
HAL_RESET_TYPE resetType,
HAL_STATUS *status)
{
#define N(a) (sizeof (a) / sizeof (a[0]))
#define FAIL(_code) do { ecode = _code; goto bad; } while (0)
@@ -740,8 +742,7 @@ ar5312SetResetReg(struct ath_hal *ah, uint32_t resetMask)
if ((resetMask & AR_RC_MAC) == 0) {
if (isBigEndian()) {
/*
* Set CFG, little-endian for register
* and descriptor accesses.
* Set CFG, little-endian for descriptor accesses.
*/
#ifdef AH_NEED_DESC_SWAP
mask = INIT_CONFIG_STATUS | AR_CFG_SWRD;
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5312/ar5312phy.h
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5312/ar5312phy.h 204644 2010-03-03 17:32:32Z rpaulo $
*/
#ifndef _DEV_ATH_AR5312PHY_H_
#define _DEV_ATH_AR5312PHY_H_
src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5312/ar5312reg.h
+1 -1
View File
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
* $FreeBSD: releng/11.1/sys/dev/ath/ath_hal/ar5312/ar5312reg.h 204644 2010-03-03 17:32:32Z rpaulo $
*/
#ifndef _DEV_ATH_AR5312REG_H_
#define _DEV_ATH_AR5312REG_H_

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