Added fifo watermark/burst-size programming for NV11 on their secondary heads. This fixes the 'vertical distortion stripes' occuring in 32bit color using secondary TVout modes: NV11 is just perfect here now :). Modified TNT2-M64 fifo watermark/burst-size programming to be executed independant of being coldstarted, which is more 'all-round'. It's upto users to confirm/deny my strong suspision this is fully OK to do (already tested on 3 cards over here). Bumped version to 0.62.

git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14884 a95241bf-73f2-0310-859d-f6bbb57e9c96

src/add-ons/accelerants/nvidia/SetDisplayMode.c

@@ -304,6 +304,7 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
 
 	/* update FIFO data fetching according to mode */
 	nv_crtc_update_fifo();
+	if (si->ps.secondary_head) nv_crtc2_update_fifo();
 
 	/* set up acceleration for this mode */
 	/* note:

src/add-ons/accelerants/nvidia/engine/nv_crtc.c

@@ -14,8 +14,9 @@ status_t nv_crtc_update_fifo()
 	uint8 bytes_per_pixel = 1;
 	uint32 drain;
 
-	/* we are only using this on coldstarted cards which really need this */
-	if ((si->settings.usebios) || (si->ps.card_type != NV05M64)) return B_OK;
+	/* we are only using this on >>coldstarted<< cards which really need this */
+	//fixme: re-enable or remove after general user confirmation of behaviour...
+	if (/*(si->settings.usebios) ||*/ (si->ps.card_type != NV05M64)) return B_OK;
 
 	/* enable access to primary head */
 	set_crtc_owner(0);

src/add-ons/accelerants/nvidia/engine/nv_crtc2.c

@@ -7,6 +7,82 @@
 
 #include "nv_std.h"
 
+/* doing general fail-safe default setup here */
+//fixme: this is a _very_ basic setup, and it's preliminary...
+status_t nv_crtc2_update_fifo()
+{
+	uint8 bytes_per_pixel = 1;
+	uint32 drain;
+
+	/* we are only using this on >>coldstarted<< cards which really need this */
+	//fixme: re-enable or remove after general user confirmation of behaviour...
+	if (/*(si->settings.usebios) ||*/ (si->ps.card_type != NV11)) return B_OK;
+
+	/* enable access to primary head */
+	set_crtc_owner(1);
+
+	/* set CRTC FIFO low watermark according to memory drain */
+	switch(si->dm.space)
+	{
+	case B_CMAP8:
+		bytes_per_pixel = 1;
+		break;
+	case B_RGB15_LITTLE:
+	case B_RGB16_LITTLE:
+		bytes_per_pixel = 2;
+		break;
+	case B_RGB24_LITTLE:
+		bytes_per_pixel = 3;
+		break;
+	case B_RGB32_LITTLE:
+		bytes_per_pixel = 4;
+		break;
+	}
+	/* fixme:
+	 * - I should probably include the refreshrate as well;
+	 * - and the memory clocking speed, core clocking speed, RAM buswidth.. */
+	drain = si->dm.timing.h_display * si->dm.timing.v_display * bytes_per_pixel;
+
+	/* Doesn't work for other than 32bit space (yet?) */
+	if (si->dm.space != B_RGB32_LITTLE)
+	{
+		/* BIOS defaults */
+		CRTC2W(FIFO, 0x03);
+		CRTC2W(FIFO_LWM, 0x20);
+		LOG(4,("CRTC2: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n"));
+		return B_OK;
+	}
+
+	if (drain > (((uint32)1280) * 1024 * 4))
+	{
+		/* set CRTC FIFO burst size for 'smaller' bursts */
+		CRTC2W(FIFO, 0x01);
+		/* Instruct CRTC to fetch new data 'earlier' */
+		CRTC2W(FIFO_LWM, 0x40);
+		LOG(4,("CRTC2: FIFO low-watermark set to $40, burst size 64\n"));
+	}
+	else
+	{
+		if (drain > (((uint32)1024) * 768 * 4))
+		{
+			/* BIOS default */
+			CRTC2W(FIFO, 0x02);
+			/* Instruct CRTC to fetch new data 'earlier' */
+			CRTC2W(FIFO_LWM, 0x40);
+			LOG(4,("CRTC2: FIFO low-watermark set to $40, burst size 128\n"));
+		}
+		else
+		{
+			/* BIOS defaults */
+			CRTC2W(FIFO, 0x03);
+			CRTC2W(FIFO_LWM, 0x20);
+			LOG(4,("CRTC2: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n"));
+		}
+	}
+
+	return B_OK;
+}
+
 /* Adjust passed parameters to a valid mode line */
 status_t nv_crtc2_validate_timing(
 	uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht,

src/add-ons/accelerants/nvidia/engine/nv_general.c

@@ -91,7 +91,7 @@ status_t nv_general_powerup()
 {
 	status_t status;
 
-	LOG(1,("POWERUP: Haiku nVidia Accelerant 0.61 running.\n"));
+	LOG(1,("POWERUP: Haiku nVidia Accelerant 0.62 running.\n"));
 
 	/* log VBLANK INT usability status */
 	if (si->ps.int_assigned)

src/add-ons/accelerants/nvidia/engine/nv_proto.h

@@ -85,6 +85,7 @@ status_t nv_crtc_stop_tvout(void);
 status_t nv_crtc_start_tvout(void);
 
 /* CRTC2 functions */
+status_t nv_crtc2_update_fifo(void);
 status_t nv_crtc2_validate_timing(
 	uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht,
 	uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt);