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openBeOS_Nvidia_V0.07_src

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@5509 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
shatty
2003-12-01 04:34:28 +00:00
parent b4c4470198
commit aa1e552f77
7 changed files with 299 additions and 97 deletions
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headers/private/graphics/nvidia/nv_macros.h
+29 -2
View File
@@ -586,6 +586,33 @@
#define NVGRPHX_MISC 0x06
#define NVGRPHX_BITMASK 0x08
/* Nvidia BES (Back End Scaler) registers (< NV10, including NV03, so RIVA128(ZX)) */
#define NVBES_NV04_INTE 0x00680140
#define NVBES_NV04_ISCALVH 0x00680200
#define NVBES_NV04_CTRL_V 0x00680204
#define NVBES_NV04_CTRL_H 0x00680208
#define NVBES_NV04_OE_STATE 0x00680224
#define NVBES_NV04_SU_STATE 0x00680228
#define NVBES_NV04_RM_STATE 0x0068022c
#define NVBES_NV04_DSTREF 0x00680230
#define NVBES_NV04_DSTSIZE 0x00680234
#define NVBES_NV04_FIFOTHRS 0x00680238
#define NVBES_NV04_FIFOBURL 0x0068023c
#define NVBES_NV04_COLKEY 0x00680240
#define NVBES_NV04_GENCTRL 0x00680244
#define NVBES_NV04_RED_AMP 0x00680280
#define NVBES_NV04_GRN_AMP 0x00680284
#define NVBES_NV04_BLU_AMP 0x00680288
#define NVBES_NV04_SAT 0x0068028c
/* buffer 0 */
#define NVBES_NV04_0BUFADR 0x0068020c
#define NVBES_NV04_0SRCPTCH 0x00680214
#define NVBES_NV04_0OFFSET 0x0068021c
/* buffer 1 */
#define NVBES_NV04_1BUFADR 0x00680210
#define NVBES_NV04_1SRCPTCH 0x00680218
#define NVBES_NV04_1OFFSET 0x00680220
/* Nvidia BES (Back End Scaler) registers (>= NV10) */
#define NVBES_NV10_INTE 0x00008140
#define NVBES_NV10_BUFSEL 0x00008700
@@ -596,7 +623,7 @@
#define NVBES_NV10_0MEMMASK 0x00008908
#define NVBES_NV10_0BRICON 0x00008910
#define NVBES_NV10_0SAT 0x00008918
#define NVBES_NV10_0WHAT 0x00008920
#define NVBES_NV10_0OFFSET 0x00008920
#define NVBES_NV10_0SRCSIZE 0x00008928
#define NVBES_NV10_0SRCREF 0x00008930
#define NVBES_NV10_0ISCALH 0x00008938
@@ -609,7 +636,7 @@
#define NVBES_NV10_1MEMMASK 0x0000890c
#define NVBES_NV10_1BRICON 0x00008914
#define NVBES_NV10_1SAT 0x0000891c
#define NVBES_NV10_1WHAT 0x00008924
#define NVBES_NV10_1OFFSET 0x00008924
#define NVBES_NV10_1SRCSIZE 0x0000892c
#define NVBES_NV10_1SRCREF 0x00008934
#define NVBES_NV10_1ISCALH 0x0000893c
src/add-ons/accelerants/nvidia/GetAccelerantHook.c
+3 -3
View File
@@ -4,7 +4,7 @@
Other authors:
Mark Watson,
Rudolf Cornelissen 10/2002-9/2003
Rudolf Cornelissen 10/2002-10/2003
*/
#define MODULE_BIT 0x08000000
@@ -170,8 +170,8 @@ status_t check_overlay_capability(uint32 feature)
break;
}
/* fixme: setup NV4 overlay also... */
if (si->ps.card_arch > NV04A)
/* all supported cards have a bes... */
if (si->ps.card_arch >= NV04A)
{
/* export video overlay functions */
LOG(4, ("Overlay: Exporting hook %s.\n", msg));
src/add-ons/accelerants/nvidia/Overlay.c
+29 -11
View File
@@ -1,4 +1,4 @@
/* Written by Rudolf Cornelissen 05-2002/09-2003 */
/* Written by Rudolf Cornelissen 05-2002/10-2003 */
/* Note on 'missing features' in BeOS 5.0.3 and DANO:
* BeOS needs to define more colorspaces! It would be nice if BeOS would support the FourCC 'definitions'
@@ -96,21 +96,22 @@ const overlay_buffer *ALLOCATE_OVERLAY_BUFFER(color_space cs, uint16 width, uint
switch (cs)
{
case B_YCbCr422:
/* check if slopspace is needed: GeForce need ~0x001f. */
/* fixme:
* update needed for GF DVDmax support to adhere to CRTC2 constraints?? */
if (width == (width & ~0x001f))
if (si->ps.card_arch < NV10A)
{
si->overlay.myBuffer[offset].width = width;
/* check if slopspace is needed: RIVA128 and TNT need ~0x000f. */
si->overlay.myBuffer[offset].width = ((width + 0x000f) & ~0x000f);
}
else
{
si->overlay.myBuffer[offset].width = (width & ~0x001f) + 0x0020;
/* check if slopspace is needed: GeForce need ~0x001f. */
/* fixme:
* update needed for GF DVDmax support to adhere to CRTC2 constraints?? */
si->overlay.myBuffer[offset].width = ((width + 0x001f) & ~0x001f);
}
si->overlay.myBuffer[offset].bytes_per_row = 2 * si->overlay.myBuffer[offset].width;
/* check if the requested horizontal pitch is supported: */
//fixme: tune for GF...
//fixme: tune for GF and TNT...
if (si->overlay.myBuffer[offset].width > 4088)
{
LOG(4,("Overlay: Sorry, requested buffer pitch not supported, aborted\n"));
@@ -386,9 +387,18 @@ status_t GET_OVERLAY_CONSTRAINTS
switch (ob->space)
{
case B_YCbCr422:
/* GeForce need 31.
* Note: this has to be in sync with the slopspace setup during buffer allocation.. */
oc->view.width_alignment = 31;
if (si->ps.card_arch < NV10A)
{
/* RIVA128 and TNT need 15.
* Note: this has to be in sync with the slopspace setup during buffer allocation.. */
oc->view.width_alignment = 15;
}
else
{
/* GeForce need 31.
* Note: this has to be in sync with the slopspace setup during buffer allocation.. */
oc->view.width_alignment = 31;
}
break;
default:
/* we should not be here, but set the worst-case value just to be safe anyway */
@@ -409,6 +419,7 @@ status_t GET_OVERLAY_CONSTRAINTS
oc->window.height_alignment = 0;
oc->window.width.min = 2;
/* GeForce cards can output upto and including 2046 pixels in width */
//fixme: how about TNT?
if (dm->virtual_width > 2046)
{
oc->window.width.max = 2046;
@@ -419,6 +430,7 @@ status_t GET_OVERLAY_CONSTRAINTS
}
oc->window.height.min = 2;
/* GeForce cards can output upto and including 2046 pixels in height */
//fixme: how about TNT?
if (dm->virtual_height > 2046)
{
oc->window.height.max = 2046;
@@ -431,12 +443,18 @@ status_t GET_OVERLAY_CONSTRAINTS
/* GeForce scaling restrictions */
switch (si->ps.card_arch)
{
case NV04A:
/* Riva128-TNT2 series have an old BES engine... */
oc->h_scale.min = 1.0;
oc->v_scale.min = 1.0;
break;
case NV30A:
/* GeForceFX series have a new BES engine... */
oc->h_scale.min = 0.5;
oc->v_scale.min = 0.5;
break;
default:
/* the rest in between... */
oc->h_scale.min = 0.125;
oc->v_scale.min = 0.125;
break;
src/add-ons/accelerants/nvidia/SetDisplayMode.c
+1 -1
View File
@@ -388,7 +388,7 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
/* set up acceleration for this mode */
nv_acc_init();
/* set up overlay unit for this mode */
if (si->ps.card_arch > NV04A) nv_bes_init();
nv_bes_init();
MSG(("SETMODE: booted since %f mS\n", system_time()/1000.0));
src/add-ons/accelerants/nvidia/engine/nv_bes.c
+234 -79
View File
@@ -1,4 +1,4 @@
/* Nvidia GeForce Back End Scaler functions */
/* Nvidia TNT and GeForce Back End Scaler functions */
/* Written by Rudolf Cornelissen 05/2002-10/2003 */
#define MODULE_BIT 0x00000200
@@ -10,18 +10,44 @@
status_t nv_bes_init()
{
/* disable overlay ints (b0 = buffer 0, b4 = buffer 1) */
BESW(NV10_INTE, 0x00000000);
/* shut off GeForce4MX MPEG2 decoder */
BESW(DEC_GENCTRL, 0x00000000);
/* setup BES memory-range mask */
BESW(NV10_0MEMMASK, ((si->ps.memory_size << 20) - 1));
/* unknown, but needed */
BESW(NV10_0WHAT, 0x00000000);
if (si->ps.card_arch < NV10A)
{
/* disable overlay ints (b0 = buffer 0, b4 = buffer 1) */
BESW(NV04_INTE, 0x00000000);
/* setup brightness, contrast and saturation to be 'neutral' */
BESW(NV10_0BRICON, ((0x1000 << 16) | 0x1000));
BESW(NV10_0SAT, ((0x0000 << 16) | 0x1000));
/* setup saturation to be 'neutral' */
BESW(NV04_SAT, 0x00000000);
/* setup RGB brightness to be 'neutral' */
BESW(NV04_RED_AMP, 0x00000069);
BESW(NV04_GRN_AMP, 0x0000003e);
BESW(NV04_BLU_AMP, 0x00000089);
/* setup fifo for fetching data */
BESW(NV04_FIFOBURL, 0x00000003);
BESW(NV04_FIFOTHRS, 0x00000038);
/* unknown, but needed (registers only have b0 implemented) */
/* (program both buffers to prevent sync distortions) */
BESW(NV04_0OFFSET, 0x00000000);
BESW(NV04_1OFFSET, 0x00000000);
}
else
{
/* >= NV10A */
/* disable overlay ints (b0 = buffer 0, b4 = buffer 1) */
BESW(NV10_INTE, 0x00000000);
/* shut off GeForce4MX MPEG2 decoder */
BESW(DEC_GENCTRL, 0x00000000);
/* setup BES memory-range mask */
BESW(NV10_0MEMMASK, ((si->ps.memory_size << 20) - 1));
/* unknown, but needed */
BESW(NV10_0OFFSET, 0x00000000);
/* setup brightness, contrast and saturation to be 'neutral' */
BESW(NV10_0BRICON, ((0x1000 << 16) | 0x1000));
BESW(NV10_0SAT, ((0x0000 << 16) | 0x1000));
}
return B_OK;
}
@@ -250,14 +276,25 @@ status_t nv_configure_bes
LOG(4,("Overlay: horizontal scaling factor is %f\n", (float)65536 / ifactor));
/* check scaling factor (and modify if needed) to be within scaling limits */
if (((((uint32)my_ov.width) << 16) / 16384) > hiscalv)
/* (assuming) all cards have a upscaling limit of 8.0 */
if (hiscalv < 0x00002000)
{
/* (non-inverse) factor too large, set factor to max. valid value */
hiscalv = ((((uint32)my_ov.width) << 16) / 16384);
hiscalv = 0x00002000;
LOG(4,("Overlay: horizontal scaling factor too large, clamping at %f\n", (float)65536 / hiscalv));
}
switch (si->ps.card_arch)
{
case NV04A:
/* Riva128-TNT2 series have a 'downscaling' limit of 1.000489
* (16bit register with 0.11 format value) */
if (hiscalv > 0x0000ffff)
{
/* (non-inverse) factor too small, set factor to min. valid value */
hiscalv = 0x0000ffff;
LOG(4,("Overlay: horizontal scaling factor too small, clamping at %f\n", (float)2048 / (hiscalv >> 5)));
}
break;
case NV30A:
/* GeForceFX series have a downscaling limit of 0.5 */
if (hiscalv > (2 << 16))
@@ -268,6 +305,7 @@ status_t nv_configure_bes
}
break;
default:
/* the rest has a downscaling limit of 0.125 */
if (hiscalv > (8 << 16))
{
/* (non-inverse) factor too small, set factor to min. valid value */
@@ -364,14 +402,25 @@ status_t nv_configure_bes
viscalv = ifactor;
/* check scaling factor (and modify if needed) to be within scaling limits */
if (((((uint32)my_ov.height) << 16) / 16384) > viscalv)
/* (assuming) all cards have a upscaling limit of 8.0 */
if (viscalv < 0x00002000)
{
/* (non-inverse) factor too large, set factor to max. valid value */
viscalv = ((((uint32)my_ov.height) << 16) / 16384);
viscalv = 0x00002000;
LOG(4,("Overlay: vertical scaling factor too large, clamping at %f\n", (float)65536 / viscalv));
}
switch (si->ps.card_arch)
{
case NV04A:
/* Riva128-TNT2 series have a 'downscaling' limit of 1.000489
* (16bit register with 0.11 format value) */
if (viscalv > 0x0000ffff)
{
/* (non-inverse) factor too small, set factor to min. valid value */
viscalv = 0x0000ffff;
LOG(4,("Overlay: vertical scaling factor too small, clamping at %f\n", (float)2048 / (viscalv >> 5)));
}
break;
case NV30A:
/* GeForceFX series have a downscaling limit of 0.5 */
if (viscalv > (2 << 16))
@@ -382,6 +431,7 @@ status_t nv_configure_bes
}
break;
default:
/* the rest has a downscaling limit of 0.125 */
if (viscalv > (8 << 16))
{
/* (non-inverse) factor too small, set factor to min. valid value */
@@ -394,6 +444,10 @@ status_t nv_configure_bes
viscalv &= 0x001ffffc;
/* calculate inputbitmap origin adress */
a1orgv = (uint32)((vuint32 *)ob->buffer);
a1orgv -= (uint32)((vuint32 *)si->framebuffer);
/* do vertical clipping... */
/* Setup vertical source start: first (sub)pixel contributing to output picture. */
/* Note:
@@ -414,23 +468,32 @@ status_t nv_configure_bes
/* increase 'number of clipping pixels' with 'fixed value':
* 'total height - 2' of dest. picture in pixels * inverse scaling factor */
v1srcstv = (ow->height - 2) * ifactor;
/* on pre-NV10 we need to do clipping in the source
* bitmap because no seperate clipping registers exist... */
if (si->ps.card_arch < NV10A)
a1orgv += ((v1srcstv >> 16) * ob->bytes_per_row);
}
else
{
/* increase 'first contributing pixel' with:
* number of destination picture clipping pixels * inverse scaling factor */
v1srcstv = (crtc_vstart - ow->v_start) * ifactor;
/* on pre-NV10 we need to do clipping in the source
* bitmap because no seperate clipping registers exist... */
if (si->ps.card_arch < NV10A)
a1orgv += ((v1srcstv >> 16) * ob->bytes_per_row);
}
LOG(4,("Overlay: clipping at top...\n"));
}
/* take zoom into account */
v1srcstv += (((uint32)my_ov.v_start) << 16);
if (si->ps.card_arch < NV10A)
{
a1orgv += (my_ov.v_start * ob->bytes_per_row);
LOG(4,("Overlay: 'contributing part of buffer' origin is (cardRAM offset) $%08x\n", a1orgv));
}
LOG(4,("Overlay: first vert. (sub)pixel of input bitmap contributing %f\n", v1srcstv / (float)65536));
/* calculate inputbitmap origin adress */
a1orgv = (uint32)((vuint32 *)ob->buffer);
a1orgv -= (uint32)((vuint32 *)si->framebuffer);
/* AND below is probably required by hardware. */
/* Buffer A topleft corner of field 1 (origin)(field 1 contains our full frames) */
a1orgv &= 0xfffffff0;
@@ -467,66 +530,150 @@ status_t nv_configure_bes
*** actually program the registers ***
**************************************/
/* We only use buffer buffer 0: select it. (0x01 = buffer 0, 0x10 = buffer 1) */
BESW(NV10_BUFSEL, 0x00000001);
/* setup buffer origin: GeForce uses subpixel precise clipping on left and top! (12.4 values) */
BESW(NV10_0SRCREF, ((v1srcstv << 4) & 0xffff0000) | ((hsrcstv >> 12) & 0x0000ffff));
/* setup buffersize */
BESW(NV10_0SRCSIZE, ((ob->height << 16) | ob->width));
/* setup source pitch including slopspace (in bytes),
* b16: select YUY2 (0 = YV12), b20: use colorkey, b24: no iturbt_709 */
/* Note:
* source pitch granularity = 32 pixels on GeForce cards!! */
BESW(NV10_0SRCPTCH, (((ob->width * 2) & 0x0000ffff) | (1 << 16) | (1 << 20) | (0 << 24)));
/* setup output window position */
BESW(NV10_0DSTREF, ((vcoordv & 0xffff0000) | ((hcoordv & 0xffff0000) >> 16)));
/* setup output window size */
BESW(NV10_0DSTSIZE, (
(((vcoordv & 0x0000ffff) - ((vcoordv & 0xffff0000) >> 16) + 1) << 16) |
((hcoordv & 0x0000ffff) - ((hcoordv & 0xffff0000) >> 16) + 1)
));
/* setup horizontal scaling */
BESW(NV10_0ISCALH, (hiscalv << 4));
/* setup vertical scaling */
BESW(NV10_0ISCALV, (viscalv << 4));
/* setup (unclipped!) buffer startadress in RAM */
BESW(NV10_0BUFADR, a1orgv);
/* enable BES (b0 = 0) */
BESW(NV10_GENCTRL, 0x00000000);
/**************************
*** setup color keying ***
**************************/
/* setup colorkeying */
switch(si->dm.space)
if (si->ps.card_arch < NV10A)
{
case B_RGB15_LITTLE:
BESW(NV10_COLKEY, (
((ow->blue.value & ow->blue.mask) << 0) |
((ow->green.value & ow->green.mask) << 5) |
((ow->red.value & ow->red.mask) << 10) |
((ow->alpha.value & ow->alpha.mask) << 15)
/* unknown, but needed (otherwise high-res distortions and only half the frames */
BESW(NV04_OE_STATE, 0x00000000);
/* select buffer 0 as active (b16) */
BESW(NV04_SU_STATE, 0x00000000);
/* unknown (no effect?) */
BESW(NV04_RM_STATE, 0x00000000);
/* setup clipped(!) buffer startadress in RAM */
/* RIVA128 - TNT bes doesn't have clipping registers, so no subpixelprecise clipping
* either. We do pixelprecise vertical and 'two pixel' precise horizontal clipping here. */
/* (program both buffers to prevent sync distortions) */
/* first include 'pixel precise' left clipping... (top clipping was already included) */
a1orgv += ((hsrcstv >> 16) * 2);
/* we need to step in 4-byte (2 pixel) granularity due to the nature of yuy2 */
BESW(NV04_0BUFADR, (a1orgv & ~0x03));
BESW(NV04_1BUFADR, (a1orgv & ~0x03));
/* setup buffer source pitch including slopspace (in bytes).
* Note:
* source pitch granularity = 16 pixels on the RIVA128 - TNT (so pre-NV10) bes */
/* (program both buffers to prevent sync distortions) */
BESW(NV04_0SRCPTCH, (ob->width * 2));
BESW(NV04_1SRCPTCH, (ob->width * 2));
/* setup output window position */
BESW(NV04_DSTREF, ((vcoordv & 0xffff0000) | ((hcoordv & 0xffff0000) >> 16)));
/* setup output window size */
BESW(NV04_DSTSIZE, (
(((vcoordv & 0x0000ffff) - ((vcoordv & 0xffff0000) >> 16) + 1) << 16) |
((hcoordv & 0x0000ffff) - ((hcoordv & 0xffff0000) >> 16) + 1)
));
break;
case B_RGB16_LITTLE:
BESW(NV10_COLKEY, (
((ow->blue.value & ow->blue.mask) << 0) |
((ow->green.value & ow->green.mask) << 5) |
((ow->red.value & ow->red.mask) << 11)
/* this space has no alpha bits */
/* setup horizontal and vertical scaling */
BESW(NV04_ISCALVH, (((viscalv << 16) >> 5) | (hiscalv >> 5)));
/* enable vertical filtering (b0) */
BESW(NV04_CTRL_V, 0x00000001);
/* enable horizontal filtering (no effect?) */
BESW(NV04_CTRL_H, 0x00000111);
/* enable BES (b0), enable colorkeying (b4), format yuy2 (b8: 0 = ccir) */
BESW(NV04_GENCTRL, 0x00000111);
/* select buffer 1 as active (b16) */
BESW(NV04_SU_STATE, 0x00010000);
/**************************
*** setup color keying ***
**************************/
/* setup colorkeying */
switch(si->dm.space)
{
case B_RGB15_LITTLE:
BESW(NV04_COLKEY, (
((ow->blue.value & ow->blue.mask) << 0) |
((ow->green.value & ow->green.mask) << 5) |
((ow->red.value & ow->red.mask) << 10) |
((ow->alpha.value & ow->alpha.mask) << 15)
));
break;
case B_RGB16_LITTLE:
BESW(NV04_COLKEY, (
((ow->blue.value & ow->blue.mask) << 0) |
((ow->green.value & ow->green.mask) << 5) |
((ow->red.value & ow->red.mask) << 11)
/* this space has no alpha bits */
));
break;
case B_CMAP8:
case B_RGB32_LITTLE:
default:
BESW(NV04_COLKEY, (
((ow->blue.value & ow->blue.mask) << 0) |
((ow->green.value & ow->green.mask) << 8) |
((ow->red.value & ow->red.mask) << 16) |
((ow->alpha.value & ow->alpha.mask) << 24)
));
break;
}
}
else
{
/* >= NV10A */
/* setup buffer origin: GeForce uses subpixel precise clipping on left and top! (12.4 values) */
BESW(NV10_0SRCREF, ((v1srcstv << 4) & 0xffff0000) | ((hsrcstv >> 12) & 0x0000ffff));
/* setup buffersize */
//fixme if needed: width must be even officially...
BESW(NV10_0SRCSIZE, ((ob->height << 16) | ob->width));
/* setup source pitch including slopspace (in bytes),
* b16: select YUY2 (0 = YV12), b20: use colorkey, b24: no iturbt_709 (do iturbt_601) */
/* Note:
* source pitch granularity = 32 pixels on GeForce cards!! */
BESW(NV10_0SRCPTCH, (((ob->width * 2) & 0x0000ffff) | (1 << 16) | (1 << 20) | (0 << 24)));
/* setup output window position */
BESW(NV10_0DSTREF, ((vcoordv & 0xffff0000) | ((hcoordv & 0xffff0000) >> 16)));
/* setup output window size */
BESW(NV10_0DSTSIZE, (
(((vcoordv & 0x0000ffff) - ((vcoordv & 0xffff0000) >> 16) + 1) << 16) |
((hcoordv & 0x0000ffff) - ((hcoordv & 0xffff0000) >> 16) + 1)
));
break;
case B_CMAP8:
case B_RGB32_LITTLE:
default:
BESW(NV10_COLKEY, (
((ow->blue.value & ow->blue.mask) << 0) |
((ow->green.value & ow->green.mask) << 8) |
((ow->red.value & ow->red.mask) << 16) |
((ow->alpha.value & ow->alpha.mask) << 24)
));
break;
/* setup horizontal scaling */
BESW(NV10_0ISCALH, (hiscalv << 4));
/* setup vertical scaling */
BESW(NV10_0ISCALV, (viscalv << 4));
/* setup (unclipped!) buffer startadress in RAM */
BESW(NV10_0BUFADR, a1orgv);
/* enable BES (b0 = 0) */
BESW(NV10_GENCTRL, 0x00000000);
/* We only use buffer buffer 0: select it. (0x01 = buffer 0, 0x10 = buffer 1) */
/* This also triggers activation of programmed values (double buffered registers feature) */
BESW(NV10_BUFSEL, 0x00000001);
/**************************
*** setup color keying ***
**************************/
/* setup colorkeying */
switch(si->dm.space)
{
case B_RGB15_LITTLE:
BESW(NV10_COLKEY, (
((ow->blue.value & ow->blue.mask) << 0) |
((ow->green.value & ow->green.mask) << 5) |
((ow->red.value & ow->red.mask) << 10) |
((ow->alpha.value & ow->alpha.mask) << 15)
));
break;
case B_RGB16_LITTLE:
BESW(NV10_COLKEY, (
((ow->blue.value & ow->blue.mask) << 0) |
((ow->green.value & ow->green.mask) << 5) |
((ow->red.value & ow->red.mask) << 11)
/* this space has no alpha bits */
));
break;
case B_CMAP8:
case B_RGB32_LITTLE:
default:
BESW(NV10_COLKEY, (
((ow->blue.value & ow->blue.mask) << 0) |
((ow->green.value & ow->green.mask) << 8) |
((ow->red.value & ow->red.mask) << 16) |
((ow->alpha.value & ow->alpha.mask) << 24)
));
break;
}
}
return B_OK;
@@ -534,8 +681,16 @@ status_t nv_configure_bes
status_t nv_release_bes()
{
/* setup BES control: disable scaler (b0 = 1) */
BESW(NV10_GENCTRL, 0x00000001);
if (si->ps.card_arch < NV10A)
{
/* setup BES control: disable scaler (b0 = 0) */
BESW(NV04_GENCTRL, 0x00000000);
}
else
{
/* setup BES control: disable scaler (b0 = 1) */
BESW(NV10_GENCTRL, 0x00000001);
}
return B_OK;
}
src/add-ons/accelerants/nvidia/engine/nv_general.c
+2 -1
View File
@@ -81,7 +81,7 @@ status_t nv_general_powerup()
{
status_t status;
LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.06 running.\n"));
LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.07 running.\n"));
/* preset no laptop */
si->ps.laptop = false;
@@ -271,6 +271,7 @@ status_t nv_general_powerup()
break;
case 0x025010de: /* Nvidia GeForce4 Ti 4600 */
case 0x025110de: /* Nvidia GeForce4 Ti 4400 */
case 0x025210de: /* Nvidia GeForce4 Ti 4600 */
case 0x025310de: /* Nvidia GeForce4 Ti 4200 */
si->ps.card_type = NV25;
si->ps.card_arch = NV20A;
src/add-ons/kernel/drivers/graphics/nvidia/driver.c
+1
View File
@@ -148,6 +148,7 @@ static uint16 nvidia_device_list[] = {
0x0203, /* Nvidia Quadro DCC */
0x0250, /* Nvidia GeForce4 Ti 4600 */
0x0251, /* Nvidia GeForce4 Ti 4400 */
0x0252, /* Nvidia GeForce4 Ti 4600 */
0x0253, /* Nvidia GeForce4 Ti 4200 */
0x0258, /* Nvidia Quadro4 900 XGL */
0x0259, /* Nvidia Quadro4 750 XGL */