* Move to common MMIO function set to make card subsystem access easier
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42159 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
@@ -82,6 +82,13 @@ struct register_info {
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#define HEAD_MODE_CLONE 0x03
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#define HEAD_MODE_LVDS_PANEL 0x08
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// register MMIO modes
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#define OUT 0x1 // direct MMIO calls
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#define CRT 0x2 // crt controler calls
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#define VGA 0x3 // vga calls
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#define PLL 0x4 // PLL calls
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#define MC 0x5 // Memory Controler calls
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extern accelerant_info *gInfo;
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extern register_info *gRegister;
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@@ -92,100 +99,164 @@ status_t init_registers(uint8 crtid);
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// register access
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inline uint32
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read32(uint32 offset)
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_read32(uint32 offset)
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{
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return *(volatile uint32 *)(gInfo->regs + offset);
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}
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inline void
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write32(uint32 offset, uint32 value)
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_write32(uint32 offset, uint32 value)
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{
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*(volatile uint32 *)(gInfo->regs + offset) = value;
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}
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inline void
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write32AtMask(uint32 offset, uint32 value, uint32 mask)
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{
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uint32 temp = read32(offset);
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temp &= ~mask;
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temp |= value & mask;
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write32(offset, temp);
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}
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inline uint32
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read32MC(uint32 offset)
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_read32MC(uint32 offset)
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{
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radeon_shared_info &info = *gInfo->shared_info;
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if (info.device_chipset == RADEON_R600) {
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write32(RS600_MC_INDEX, ((offset & RS600_MC_INDEX_ADDR_MASK)
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_write32(RS600_MC_INDEX, ((offset & RS600_MC_INDEX_ADDR_MASK)
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| RS600_MC_INDEX_CITF_ARB0));
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return read32(RS600_MC_DATA);
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return _read32(RS600_MC_DATA);
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} else if (info.device_chipset == (RADEON_R600 & 0x90)
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|| info.device_chipset == (RADEON_R700 & 0x40)) {
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write32(RS690_MC_INDEX, (offset & RS690_MC_INDEX_ADDR_MASK));
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return read32(RS690_MC_DATA);
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_write32(RS690_MC_INDEX, (offset & RS690_MC_INDEX_ADDR_MASK));
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return _read32(RS690_MC_DATA);
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} else if (info.device_chipset == (RADEON_R700 & 0x80)
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|| info.device_chipset == (RADEON_R800 & 0x80)) {
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write32(RS780_MC_INDEX, offset & RS780_MC_INDEX_ADDR_MASK);
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return read32(RS780_MC_DATA);
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_write32(RS780_MC_INDEX, offset & RS780_MC_INDEX_ADDR_MASK);
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return _read32(RS780_MC_DATA);
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}
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// eh.
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return read32(offset);
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return _read32(offset);
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}
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inline void
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write32MC(uint32 offset, uint32 data)
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_write32MC(uint32 offset, uint32 data)
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{
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radeon_shared_info &info = *gInfo->shared_info;
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if (info.device_chipset == RADEON_R600) {
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write32(RS600_MC_INDEX, ((offset & RS600_MC_INDEX_ADDR_MASK)
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_write32(RS600_MC_INDEX, ((offset & RS600_MC_INDEX_ADDR_MASK)
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| RS600_MC_INDEX_CITF_ARB0 | RS600_MC_INDEX_WR_EN));
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write32(RS600_MC_DATA, data);
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_write32(RS600_MC_DATA, data);
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} else if (info.device_chipset == (RADEON_R600 & 0x90)
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|| info.device_chipset == (RADEON_R700 & 0x40)) {
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write32(RS690_MC_INDEX, ((offset & RS690_MC_INDEX_ADDR_MASK)
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_write32(RS690_MC_INDEX, ((offset & RS690_MC_INDEX_ADDR_MASK)
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| RS690_MC_INDEX_WR_EN));
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write32(RS690_MC_DATA, data);
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write32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
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_write32(RS690_MC_DATA, data);
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_write32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
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} else if (info.device_chipset == (RADEON_R700 & 0x80)
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|| info.device_chipset == (RADEON_R800 & 0x80)) {
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write32(RS780_MC_INDEX, ((offset & RS780_MC_INDEX_ADDR_MASK)
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_write32(RS780_MC_INDEX, ((offset & RS780_MC_INDEX_ADDR_MASK)
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| RS780_MC_INDEX_WR_EN));
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write32(RS780_MC_DATA, data);
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_write32(RS780_MC_DATA, data);
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}
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}
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inline uint32
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read32PLL(uint16 offset)
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_read32PLL(uint16 offset)
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{
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write32(CLOCK_CNTL_INDEX, offset & PLL_ADDR);
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return read32(CLOCK_CNTL_DATA);
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_write32(CLOCK_CNTL_INDEX, offset & PLL_ADDR);
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return _read32(CLOCK_CNTL_DATA);
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}
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inline void
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write32PLL(uint16 offset, uint32 data)
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_write32PLL(uint16 offset, uint32 data)
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{
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write32(CLOCK_CNTL_INDEX, (offset & PLL_ADDR) | PLL_WR_EN);
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write32(CLOCK_CNTL_DATA, data);
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_write32(CLOCK_CNTL_INDEX, (offset & PLL_ADDR) | PLL_WR_EN);
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_write32(CLOCK_CNTL_DATA, data);
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}
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inline uint32
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Read32(uint32 subsystem, uint32 offset)
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{
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switch (subsystem) {
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default:
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case OUT:
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case VGA:
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return _read32(offset);
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case CRT:
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return _read32(offset);
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case PLL:
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return _read32PLL(offset);
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case MC:
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return _read32MC(offset);
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};
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}
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inline void
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write32PLLAtMask(uint16 offset, uint32 value, uint32 mask)
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Write32(uint32 subsystem, uint32 offset, uint32 value)
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{
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uint32 temp = read32PLL(offset);
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switch (subsystem) {
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default:
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case OUT:
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case VGA:
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_write32(offset, value);
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return;
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case CRT:
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_write32(offset, value);
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return;
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case PLL:
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_write32PLL(offset, value);
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return;
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case MC:
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_write32MC(offset, value);
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return;
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};
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}
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inline void
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Write32Mask(uint32 subsystem, uint32 offset, uint32 value, uint32 mask)
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{
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uint32 temp;
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switch (subsystem) {
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default:
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case OUT:
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case VGA:
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temp = _read32(offset);
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break;
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case CRT:
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temp = _read32(offset);
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break;
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case PLL:
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temp = _read32PLL(offset);
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break;
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case MC:
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temp = _read32MC(offset);
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break;
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};
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// only effect mask
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temp &= ~mask;
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temp |= value & mask;
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write32PLL(offset, temp);
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switch (subsystem) {
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default:
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case OUT:
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case VGA:
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_write32(offset, temp);
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return;
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case CRT:
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_write32(offset, temp);
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return;
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case PLL:
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_write32PLL(offset, temp);
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return;
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case MC:
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_write32MC(offset, temp);
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return;
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};
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}
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@@ -89,7 +89,7 @@ UINT32
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CailReadATIRegister(VOID* CAIL, UINT32 idx)
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{
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TRACE("AtomBios callback %s, idx (0x%X)\n", __func__, idx << 2);
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return read32(idx << 2);
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return Read32(OUT, idx << 2);
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}
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@@ -100,7 +100,7 @@ CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data)
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// TODO : save MMIO via atomSaveRegisters in CailWriteATIRegister
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// atomSaveRegisters((atomBiosHandlePtr)CAIL, atomRegisterMMIO, idx << 2);
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write32(idx << 2, data);
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Write32(OUT, idx << 2, data);
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}
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@@ -131,7 +131,7 @@ ULONG
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CailReadPLL(VOID *CAIL, ULONG address)
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{
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TRACE("AtomBios callback %s, addr (0x%X)\n", __func__, address);
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return read32PLL(address);
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return Read32(PLL, address);
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}
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@@ -143,7 +143,7 @@ CailWritePLL(VOID *CAIL, ULONG address, ULONG data)
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// TODO : save PLL registers
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// atomSaveRegisters((atomBiosHandlePtr)CAIL, atomRegisterPLL, address);
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// TODO : Assumed screen index 0
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write32PLL(address, data);
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Write32(PLL, address, data);
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}
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@@ -186,7 +186,7 @@ CailReadFBData(VOID* CAIL, UINT32 idx)
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// If we have a physical offset for our frame buffer, use it
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if (fbLocation > 0)
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ret = read32(fbLocation + idx);
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ret = Read32(PLL, fbLocation + idx);
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else {
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TRACE("%s: ERROR: Frame Buffer offset not defined\n",
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__func__);
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@@ -209,7 +209,7 @@ CailWriteFBData(VOID *CAIL, UINT32 idx, UINT32 data)
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// If we have a physical offset for our frame buffer, use it
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if (fbLocation > 0)
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write32(fbLocation + idx, data);
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Write32(OUT, fbLocation + idx, data);
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else
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TRACE("%s: ERROR: Frame Buffer offset not defined\n",
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__func__);
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@@ -134,8 +134,8 @@ CardBlankSet(bool blank)
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blackColorReg = D1CRTC_BLACK_COLOR;
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blankControlReg = D1CRTC_BLANK_CONTROL;
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write32(blackColorReg, 0);
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write32AtMask(blankControlReg, blank ? 1 << 8 : 0, 1 << 8);
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Write32(CRT, blackColorReg, 0);
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Write32Mask(CRT, blankControlReg, blank ? 1 << 8 : 0, 1 << 8);
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}
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@@ -149,39 +149,39 @@ CardFBSet(display_mode *mode)
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get_color_space_format(*mode, colorMode, bytesPerRow, bitsPerPixel);
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// Disable VGA mode to enable Radeon extended registers
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write32AtMask(VGA_RENDER_CONTROL, 0, 0x00030000);
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write32AtMask(VGA_MODE_CONTROL, 0, 0x00000030);
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write32AtMask(VGA_HDP_CONTROL, 0x00010010, 0x00010010);
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write32AtMask(gRegister->vgaControl, 0, D1VGA_MODE_ENABLE
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Write32Mask(VGA, VGA_RENDER_CONTROL, 0, 0x00030000);
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Write32Mask(VGA, VGA_MODE_CONTROL, 0, 0x00000030);
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Write32Mask(VGA, VGA_HDP_CONTROL, 0x00010010, 0x00010010);
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Write32Mask(VGA, gRegister->vgaControl, 0, D1VGA_MODE_ENABLE
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| D1VGA_TIMING_SELECT | D1VGA_SYNC_POLARITY_SELECT);
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// disable R/B swap, disable tiling, disable 16bit alpha, etc.
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write32AtMask(gRegister->grphEnable, 1, 0x00000001);
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write32(gRegister->grphControl, 0);
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Write32Mask(CRT, gRegister->grphEnable, 1, 0x00000001);
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Write32(CRT, gRegister->grphControl, 0);
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// set color mode on video card
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switch (mode->space) {
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case B_CMAP8:
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write32AtMask(gRegister->grphControl,
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Write32Mask(CRT, gRegister->grphControl,
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0, 0x00000703);
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break;
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case B_RGB15_LITTLE:
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write32AtMask(gRegister->grphControl,
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Write32Mask(CRT, gRegister->grphControl,
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0x000001, 0x00000703);
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break;
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case B_RGB16_LITTLE:
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write32AtMask(gRegister->grphControl,
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Write32Mask(CRT, gRegister->grphControl,
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0x000101, 0x00000703);
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break;
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case B_RGB24_LITTLE:
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case B_RGB32_LITTLE:
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default:
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write32AtMask(gRegister->grphControl,
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Write32Mask(CRT, gRegister->grphControl,
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0x000002, 0x00000703);
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break;
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}
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write32(gRegister->grphSwapControl, 0);
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Write32(CRT, gRegister->grphSwapControl, 0);
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// only for chipsets > r600
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// R5xx - RS690 case is GRPH_CONTROL bit 16
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@@ -191,27 +191,27 @@ CardFBSet(display_mode *mode)
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// Tell GPU which frame buffer address to draw from
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if (gInfo->shared_info->device_chipset >= (uint16)(RADEON_R700 & 0x70)) {
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write32(gRegister->grphPrimarySurfaceAddrHigh,
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Write32(CRT, gRegister->grphPrimarySurfaceAddrHigh,
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(fbAddress >> 32) & 0xf);
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write32(gRegister->grphSecondarySurfaceAddrHigh,
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Write32(CRT, gRegister->grphSecondarySurfaceAddrHigh,
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(fbAddress >> 32) & 0xf);
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}
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write32(gRegister->grphPrimarySurfaceAddr,
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Write32(CRT, gRegister->grphPrimarySurfaceAddr,
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fbAddress & 0xffffffff);
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write32(gRegister->grphSecondarySurfaceAddr,
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Write32(CRT, gRegister->grphSecondarySurfaceAddr,
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fbAddress & 0xffffffff);
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write32(gRegister->grphPitch, bytesPerRow / 4);
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write32(gRegister->grphSurfaceOffsetX, 0);
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write32(gRegister->grphSurfaceOffsetY, 0);
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write32(gRegister->grphXStart, 0);
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write32(gRegister->grphYStart, 0);
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write32(gRegister->grphXEnd, mode->virtual_width);
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write32(gRegister->grphYEnd, mode->virtual_height);
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Write32(CRT, gRegister->grphPitch, bytesPerRow / 4);
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Write32(CRT, gRegister->grphSurfaceOffsetX, 0);
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Write32(CRT, gRegister->grphSurfaceOffsetY, 0);
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Write32(CRT, gRegister->grphXStart, 0);
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Write32(CRT, gRegister->grphYStart, 0);
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Write32(CRT, gRegister->grphXEnd, mode->virtual_width);
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Write32(CRT, gRegister->grphYEnd, mode->virtual_height);
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/* D1Mode registers */
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write32(gRegister->modeDesktopHeight, mode->virtual_height);
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Write32(CRT, gRegister->modeDesktopHeight, mode->virtual_height);
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// update shared info
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gInfo->shared_info->bytes_per_row = bytesPerRow;
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@@ -229,10 +229,10 @@ CardModeSet(display_mode *mode)
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__func__, displayTiming.h_display, displayTiming.v_display);
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// enable read requests
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write32AtMask(gRegister->grphControl, 0, 0x01000000);
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Write32Mask(CRT, gRegister->grphControl, 0, 0x01000000);
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// *** Horizontal
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write32(gRegister->crtHTotal,
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Write32(CRT, gRegister->crtHTotal,
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displayTiming.h_total - 1);
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#if 0
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@@ -240,89 +240,89 @@ CardModeSet(display_mode *mode)
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uint16 blankStart = displayTiming.h_display;
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uint16 blankEnd = displayTiming.h_total;
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write32(gRegister->crtHBlank,
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Write32(CRT, gRegister->crtHBlank,
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blankStart | (blankEnd << 16));
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#endif
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write32(gRegister->crtHSync,
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Write32(CRT, gRegister->crtHSync,
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(displayTiming.h_sync_end - displayTiming.h_sync_start) << 16);
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// set flag for neg. H sync. M76 Register Reference Guide 2-256
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write32AtMask(gRegister->crtHPolarity,
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Write32Mask(CRT, gRegister->crtHPolarity,
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displayTiming.flags & B_POSITIVE_HSYNC ? 0 : 1, 0x1);
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// *** Vertical
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write32(gRegister->crtVTotal,
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Write32(CRT, gRegister->crtVTotal,
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displayTiming.v_total - 1);
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#if 0
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blankStart = displayTiming.v_display;
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blankEnd = displayTiming.v_total;
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write32(gRegister->crtVBlank,
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Write32(CRT, gRegister->crtVBlank,
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blankStart | (blankEnd << 16));
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#endif
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// Set Interlace if specified within mode line
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if (displayTiming.flags & B_TIMING_INTERLACED) {
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write32(gRegister->crtInterlace, 0x1);
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write32(gRegister->modeDataFormat, 0x1);
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Write32(CRT, gRegister->crtInterlace, 0x1);
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Write32(CRT, gRegister->modeDataFormat, 0x1);
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} else {
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write32(gRegister->crtInterlace, 0x0);
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write32(gRegister->modeDataFormat, 0x0);
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Write32(CRT, gRegister->crtInterlace, 0x0);
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Write32(CRT, gRegister->modeDataFormat, 0x0);
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}
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write32(gRegister->crtVSync,
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Write32(CRT, gRegister->crtVSync,
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(displayTiming.v_sync_end - displayTiming.v_sync_start) << 16);
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// set flag for neg. V sync. M76 Register Reference Guide 2-258
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// we don't need a mask here as this is the only param for Vertical
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write32(gRegister->crtVPolarity,
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Write32(CRT, gRegister->crtVPolarity,
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displayTiming.flags & B_POSITIVE_VSYNC ? 0 : 1);
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/* set D1CRTC_HORZ_COUNT_BY2_EN to 0;
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should only be set to 1 on 30bpp DVI modes
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*/
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write32AtMask(gRegister->crtCountControl, 0x0, 0x1);
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Write32Mask(CRT, gRegister->crtCountControl, 0x0, 0x1);
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}
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static void
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CardModeScale(display_mode *mode)
|
||||
{
|
||||
write32(gRegister->viewportSize,
|
||||
Write32(CRT, gRegister->viewportSize,
|
||||
mode->timing.v_display | (mode->timing.h_display << 16));
|
||||
write32(gRegister->viewportStart, 0);
|
||||
Write32(CRT, gRegister->viewportStart, 0);
|
||||
|
||||
// For now, no overscan support
|
||||
write32(D1MODE_EXT_OVERSCAN_LEFT_RIGHT,
|
||||
Write32(CRT, D1MODE_EXT_OVERSCAN_LEFT_RIGHT,
|
||||
(0 << 16) | 0); // LEFT | RIGHT
|
||||
write32(D1MODE_EXT_OVERSCAN_TOP_BOTTOM,
|
||||
Write32(CRT, D1MODE_EXT_OVERSCAN_TOP_BOTTOM,
|
||||
(0 << 16) | 0); // TOP | BOTTOM
|
||||
|
||||
// No scaling
|
||||
write32(gRegister->sclUpdate, (1<<16)); // Lock
|
||||
write32(gRegister->sclEnable, 0);
|
||||
write32(gRegister->sclTapControl, 0);
|
||||
write32(gRegister->modeCenter, 0);
|
||||
write32(gRegister->sclUpdate, 0); // Unlock
|
||||
Write32(CRT, gRegister->sclUpdate, (1<<16));// Lock
|
||||
Write32(CRT, gRegister->sclEnable, 0);
|
||||
Write32(CRT, gRegister->sclTapControl, 0);
|
||||
Write32(CRT, gRegister->modeCenter, 0);
|
||||
Write32(CRT, gRegister->sclUpdate, 0); // Unlock
|
||||
|
||||
#if 0
|
||||
// Auto scale keeping aspect ratio
|
||||
write32(regOffset + D1MODE_CENTER, 1);
|
||||
Write32(CRT, regOffset + D1MODE_CENTER, 1);
|
||||
|
||||
write32(regOffset + D1SCL_UPDATE, 0);
|
||||
write32(regOffset + D1SCL_FLIP_CONTROL, 0);
|
||||
Write32(CRT, regOffset + D1SCL_UPDATE, 0);
|
||||
Write32(CRT, regOffset + D1SCL_FLIP_CONTROL, 0);
|
||||
|
||||
write32(regOffset + D1SCL_ENABLE, 1);
|
||||
write32(regOffset + D1SCL_HVSCALE, 0x00010001);
|
||||
Write32(CRT, regOffset + D1SCL_ENABLE, 1);
|
||||
Write32(CRT, regOffset + D1SCL_HVSCALE, 0x00010001);
|
||||
|
||||
write32(regOffset + D1SCL_TAP_CONTROL, 0x00000101);
|
||||
Write32(CRT, regOffset + D1SCL_TAP_CONTROL, 0x00000101);
|
||||
|
||||
write32(regOffset + D1SCL_HFILTER, 0x00030100);
|
||||
write32(regOffset + D1SCL_VFILTER, 0x00030100);
|
||||
Write32(CRT, regOffset + D1SCL_HFILTER, 0x00030100);
|
||||
Write32(CRT, regOffset + D1SCL_VFILTER, 0x00030100);
|
||||
|
||||
write32(regOffset + D1SCL_DITHER, 0x00001010);
|
||||
Write32(CRT, regOffset + D1SCL_DITHER, 0x00001010);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -343,7 +343,7 @@ radeon_set_display_mode(display_mode *mode)
|
||||
DACPower(0, RHD_POWER_ON);
|
||||
CardBlankSet(false);
|
||||
|
||||
int32 crtstatus = read32(D1CRTC_STATUS);
|
||||
int32 crtstatus = Read32(CRT, D1CRTC_STATUS);
|
||||
TRACE("CRT0 Status: 0x%X\n", crtstatus);
|
||||
|
||||
return B_OK;
|
||||
|
||||
@@ -149,7 +149,7 @@ PLLPower(uint8 pllIndex, int command)
|
||||
if (hasDccg)
|
||||
DCCGCLKSet(pllIndex, RV620_DCCGCLK_RESET);
|
||||
|
||||
write32PLLAtMask(pllControlReg, 0, 0x02);
|
||||
Write32Mask(PLL, pllControlReg, 0, 0x02);
|
||||
// Power On
|
||||
snooze(2);
|
||||
PLLCalibrate(pllIndex);
|
||||
@@ -166,10 +166,10 @@ PLLPower(uint8 pllIndex, int command)
|
||||
if (hasDccg)
|
||||
DCCGCLKSet(pllIndex, RV620_DCCGCLK_RELEASE);
|
||||
|
||||
write32PLLAtMask(pllControlReg, 0x01, 0x01);
|
||||
Write32Mask(PLL, pllControlReg, 0x01, 0x01);
|
||||
// Reset
|
||||
snooze(2);
|
||||
write32PLLAtMask(pllControlReg, 0, 0x02);
|
||||
Write32Mask(PLL, pllControlReg, 0, 0x02);
|
||||
// Power On
|
||||
snooze(2);
|
||||
return B_OK;
|
||||
@@ -182,14 +182,14 @@ PLLPower(uint8 pllIndex, int command)
|
||||
if (hasDccg)
|
||||
DCCGCLKSet(pllIndex, RV620_DCCGCLK_RELEASE);
|
||||
|
||||
write32PLLAtMask(pllControlReg, 0x01, 0x01);
|
||||
Write32Mask(PLL, pllControlReg, 0x01, 0x01);
|
||||
// Reset
|
||||
snooze(2);
|
||||
|
||||
// Sometimes we have to keep an unused PLL running. Xorg Bug #18016
|
||||
if ((read32PLL(RV620_EXT1_DIFF_POST_DIV_CNTL)
|
||||
if ((Read32(PLL, RV620_EXT1_DIFF_POST_DIV_CNTL)
|
||||
& RV62_EXT1_DIFF_DRIVER_ENABLE) == 0) {
|
||||
write32PLLAtMask(pllControlReg, 0x02, 0x02);
|
||||
Write32Mask(PLL, pllControlReg, 0x02, 0x02);
|
||||
// Power Down
|
||||
} else {
|
||||
TRACE("%s: PHYA differential clock driver not disabled\n",
|
||||
@@ -198,7 +198,7 @@ PLLPower(uint8 pllIndex, int command)
|
||||
|
||||
snooze(200);
|
||||
|
||||
write32PLLAtMask(pllControlReg, 0x2000, 0x2000);
|
||||
Write32Mask(PLL, pllControlReg, 0x2000, 0x2000);
|
||||
// Reset anti-glitch?
|
||||
}
|
||||
|
||||
@@ -247,15 +247,15 @@ PLLSet(uint8 pllIndex, uint32 pixelClock)
|
||||
uint16 pllPostDividerSrcReg
|
||||
= (pllIndex == 1) ? EXT2_PPLL_POST_DIV_SRC : EXT1_PPLL_POST_DIV_SRC;
|
||||
|
||||
write32PLLAtMask(pllIntSSControlReg, 0, 0x00000001);
|
||||
Write32Mask(PLL, pllIntSSControlReg, 0, 0x00000001);
|
||||
// Disable Spread Spectrum
|
||||
|
||||
uint32 referenceDivider = reference;
|
||||
|
||||
uint32 feedbackDivider = read32PLL(pllFeedbackDividerReg) & ~0x07FF003F;
|
||||
uint32 feedbackDivider = Read32(PLL, pllFeedbackDividerReg) & ~0x07FF003F;
|
||||
feedbackDivider |= ((feedback << 16) | 0x0030) & 0x07FF003F;
|
||||
|
||||
uint32 postDivider = read32PLL(pllPostDividerReg) & ~0x0000007F;
|
||||
uint32 postDivider = Read32(PLL, pllPostDividerReg) & ~0x0000007F;
|
||||
postDivider |= post & 0x0000007F;
|
||||
|
||||
uint32 control;
|
||||
@@ -267,54 +267,54 @@ PLLSet(uint8 pllIndex, uint32 pixelClock)
|
||||
uint8 symPostDiv = post & 0x0000007F;
|
||||
|
||||
/* switch to external */
|
||||
write32PLL(pllPostDividerSrcReg, 0);
|
||||
write32PLLAtMask(pllDisplayClockControlReg, 0x00000200, 0x00000300);
|
||||
write32PLLAtMask(pllPostDividerReg, 0, 0x00000100);
|
||||
Write32(PLL, pllPostDividerSrcReg, 0);
|
||||
Write32Mask(PLL, pllDisplayClockControlReg, 0x00000200, 0x00000300);
|
||||
Write32Mask(PLL, pllPostDividerReg, 0, 0x00000100);
|
||||
|
||||
write32PLLAtMask(pllControlReg, 0x00000001, 0x00000001);
|
||||
Write32Mask(PLL, pllControlReg, 0x00000001, 0x00000001);
|
||||
// reset
|
||||
snooze(2);
|
||||
write32PLLAtMask(pllControlReg, 0x00000002, 0x00000002);
|
||||
Write32Mask(PLL, pllControlReg, 0x00000002, 0x00000002);
|
||||
// power down
|
||||
snooze(10);
|
||||
write32PLLAtMask(pllControlReg, 0x00002000, 0x00002000);
|
||||
Write32Mask(PLL, pllControlReg, 0x00002000, 0x00002000);
|
||||
// reset antiglitch
|
||||
|
||||
write32PLL(pllExtControlReg, control);
|
||||
Write32(PLL, pllExtControlReg, control);
|
||||
|
||||
write32PLLAtMask(pllDisplayClockControlReg, 2, 0x0000003F);
|
||||
Write32Mask(PLL, pllDisplayClockControlReg, 2, 0x0000003F);
|
||||
// Scalar Divider 2
|
||||
|
||||
write32PLL(pllLockReg, 1);
|
||||
Write32(PLL, pllLockReg, 1);
|
||||
// Lock PLL
|
||||
|
||||
/* Write PLL clocks */
|
||||
write32PLL(pllPostDividerSrcReg, 0x00000001);
|
||||
write32PLL(pllReferenceDividerReg, referenceDivider);
|
||||
write32PLL(pllFeedbackDividerReg, feedbackDivider);
|
||||
write32PLLAtMask(pllPostDividerReg, postDivider, 0x0000007F);
|
||||
write32PLLAtMask(pplPostDividerSymReg, symPostDiv, 0x0000007F);
|
||||
Write32(PLL, pllPostDividerSrcReg, 0x00000001);
|
||||
Write32(PLL, pllReferenceDividerReg, referenceDivider);
|
||||
Write32(PLL, pllFeedbackDividerReg, feedbackDivider);
|
||||
Write32Mask(PLL, pllPostDividerReg, postDivider, 0x0000007F);
|
||||
Write32Mask(PLL, pplPostDividerSymReg, symPostDiv, 0x0000007F);
|
||||
|
||||
snooze(10);
|
||||
|
||||
write32PLL(pllLockReg, 0);
|
||||
Write32(PLL, pllLockReg, 0);
|
||||
// Unlock PLL
|
||||
|
||||
write32PLLAtMask(pllControlReg, 0, 0x00000002);
|
||||
Write32Mask(PLL, pllControlReg, 0, 0x00000002);
|
||||
// power up
|
||||
snooze(10);
|
||||
|
||||
write32PLLAtMask(pllControlReg, 0, 0x00002000);
|
||||
Write32Mask(PLL, pllControlReg, 0, 0x00002000);
|
||||
// undo reset antiglitch
|
||||
|
||||
PLLCalibrate(pllIndex);
|
||||
|
||||
/* Switch back to PLL */
|
||||
write32PLLAtMask(pllDisplayClockControlReg, 0, 0x00000300);
|
||||
write32PLLAtMask(pplPostDividerSymReg, 0x00000100, 0x00000100);
|
||||
write32PLL(pllPostDividerSrcReg, 0x00000001);
|
||||
Write32Mask(PLL, pllDisplayClockControlReg, 0, 0x00000300);
|
||||
Write32Mask(PLL, pplPostDividerSymReg, 0x00000100, 0x00000100);
|
||||
Write32(PLL, pllPostDividerSrcReg, 0x00000001);
|
||||
|
||||
write32PLLAtMask(pllControlReg, 0, 0x80000000);
|
||||
Write32Mask(PLL, pllControlReg, 0, 0x80000000);
|
||||
// needed and undocumented
|
||||
|
||||
// TODO : If CRT2 ah-la R500PLLCRTCGrab
|
||||
@@ -334,24 +334,24 @@ PLLCalibrate(uint8 pllIndex)
|
||||
|
||||
uint16 pllControlReg = (pllIndex == 1) ? P2PLL_CNTL : P1PLL_CNTL;
|
||||
|
||||
write32PLLAtMask(pllControlReg, 1, 0x01);
|
||||
Write32Mask(PLL, pllControlReg, 1, 0x01);
|
||||
// PLL Reset
|
||||
|
||||
snooze(2);
|
||||
|
||||
write32PLLAtMask(pllControlReg, 0, 0x01);
|
||||
Write32Mask(PLL, pllControlReg, 0, 0x01);
|
||||
// PLL Set
|
||||
|
||||
int i;
|
||||
|
||||
for (i = 0; i < PLL_CALIBRATE_WAIT; i++)
|
||||
if (((read32PLL(pllControlReg) >> 20) & 0x03) == 0x03)
|
||||
if (((Read32(PLL, pllControlReg) >> 20) & 0x03) == 0x03)
|
||||
break;
|
||||
|
||||
if (i >= PLL_CALIBRATE_WAIT) {
|
||||
if (read32PLL(pllControlReg) & 0x00100000) /* Calibration done? */
|
||||
if (Read32(PLL, pllControlReg) & 0x00100000) /* Calibration done? */
|
||||
TRACE("%s: Calibration Failed\n", __func__);
|
||||
if (read32PLL(pllControlReg) & 0x00200000) /* PLL locked? */
|
||||
if (Read32(PLL, pllControlReg) & 0x00200000) /* PLL locked? */
|
||||
TRACE("%s: Locking Failed\n", __func__);
|
||||
TRACE("%s: We encountered a problem calibrating the PLL.\n", __func__);
|
||||
return B_ERROR;
|
||||
@@ -368,35 +368,35 @@ PLLCRTCGrab(uint8 pllIndex, bool crt2)
|
||||
bool pll2IsCurrent;
|
||||
|
||||
if (!crt2) {
|
||||
pll2IsCurrent = read32PLL(PCLK_CRTC1_CNTL) & 0x00010000;
|
||||
pll2IsCurrent = Read32(PLL, PCLK_CRTC1_CNTL) & 0x00010000;
|
||||
|
||||
write32PLLAtMask(PCLK_CRTC1_CNTL, (pllIndex == 1) ? 0x00010000 : 0,
|
||||
Write32Mask(PLL, PCLK_CRTC1_CNTL, (pllIndex == 1) ? 0x00010000 : 0,
|
||||
0x00010000);
|
||||
} else {
|
||||
pll2IsCurrent = read32PLL(PCLK_CRTC2_CNTL) & 0x00010000;
|
||||
pll2IsCurrent = Read32(PLL, PCLK_CRTC2_CNTL) & 0x00010000;
|
||||
|
||||
write32PLLAtMask(PCLK_CRTC2_CNTL, (pllIndex == 1) ? 0x00010000 : 0,
|
||||
Write32Mask(PLL, PCLK_CRTC2_CNTL, (pllIndex == 1) ? 0x00010000 : 0,
|
||||
0x00010000);
|
||||
}
|
||||
|
||||
/* if the current pll is not active, then poke it just enough to flip
|
||||
* owners */
|
||||
if (!pll2IsCurrent) {
|
||||
uint32 stored = read32PLL(P1PLL_CNTL);
|
||||
uint32 stored = Read32(PLL, P1PLL_CNTL);
|
||||
|
||||
if (stored & 0x03) {
|
||||
write32PLLAtMask(P1PLL_CNTL, 0, 0x03);
|
||||
Write32Mask(PLL, P1PLL_CNTL, 0, 0x03);
|
||||
snooze(10);
|
||||
write32PLLAtMask(P1PLL_CNTL, stored, 0x03);
|
||||
Write32Mask(PLL, P1PLL_CNTL, stored, 0x03);
|
||||
}
|
||||
|
||||
} else {
|
||||
uint32 stored = read32PLL(P2PLL_CNTL);
|
||||
uint32 stored = Read32(PLL, P2PLL_CNTL);
|
||||
|
||||
if (stored & 0x03) {
|
||||
write32PLLAtMask(P2PLL_CNTL, 0, 0x03);
|
||||
Write32Mask(PLL, P2PLL_CNTL, 0, 0x03);
|
||||
snooze(10);
|
||||
write32PLLAtMask(P2PLL_CNTL, stored, 0x03);
|
||||
Write32Mask(PLL, P2PLL_CNTL, stored, 0x03);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -407,7 +407,7 @@ PLLCRTCGrab(uint8 pllIndex, bool crt2)
|
||||
bool
|
||||
DCCGCLKAvailable(uint8 pllIndex)
|
||||
{
|
||||
uint32 dccg = read32PLL(DCCG_DISP_CLK_SRCSEL) & 0x03;
|
||||
uint32 dccg = Read32(PLL, DCCG_DISP_CLK_SRCSEL) & 0x03;
|
||||
|
||||
if (dccg & 0x02)
|
||||
return true;
|
||||
@@ -429,41 +429,41 @@ DCCGCLKSet(uint8 pllIndex, int set)
|
||||
switch(set) {
|
||||
case RV620_DCCGCLK_GRAB:
|
||||
if (pllIndex == 0)
|
||||
write32PLLAtMask(DCCG_DISP_CLK_SRCSEL, 0, 0x00000003);
|
||||
Write32Mask(PLL, DCCG_DISP_CLK_SRCSEL, 0, 0x00000003);
|
||||
else if (pllIndex == 1)
|
||||
write32PLLAtMask(DCCG_DISP_CLK_SRCSEL, 1, 0x00000003);
|
||||
Write32Mask(PLL, DCCG_DISP_CLK_SRCSEL, 1, 0x00000003);
|
||||
else
|
||||
write32PLLAtMask(DCCG_DISP_CLK_SRCSEL, 3, 0x00000003);
|
||||
Write32Mask(PLL, DCCG_DISP_CLK_SRCSEL, 3, 0x00000003);
|
||||
break;
|
||||
case RV620_DCCGCLK_RELEASE:
|
||||
buffer = read32PLL(DCCG_DISP_CLK_SRCSEL) & 0x03;
|
||||
buffer = Read32(PLL, DCCG_DISP_CLK_SRCSEL) & 0x03;
|
||||
|
||||
if ((pllIndex == 0) && (buffer == 0)) {
|
||||
/* set to other PLL or external */
|
||||
buffer = read32PLL(P2PLL_CNTL);
|
||||
buffer = Read32(PLL, P2PLL_CNTL);
|
||||
// if powered and not in reset, and calibrated and locked
|
||||
if (!(buffer & 0x03) && ((buffer & 0x00300000) == 0x00300000))
|
||||
write32PLLAtMask(DCCG_DISP_CLK_SRCSEL, 1, 0x00000003);
|
||||
Write32Mask(PLL, DCCG_DISP_CLK_SRCSEL, 1, 0x00000003);
|
||||
else
|
||||
write32PLLAtMask(DCCG_DISP_CLK_SRCSEL, 3, 0x00000003);
|
||||
Write32Mask(PLL, DCCG_DISP_CLK_SRCSEL, 3, 0x00000003);
|
||||
|
||||
} else if ((pllIndex == 1) && (buffer == 1)) {
|
||||
/* set to other PLL or external */
|
||||
buffer = read32PLL(P1PLL_CNTL);
|
||||
buffer = Read32(PLL, P1PLL_CNTL);
|
||||
// if powered and not in reset, and calibrated and locked
|
||||
if (!(buffer & 0x03) && ((buffer & 0x00300000) == 0x00300000))
|
||||
write32PLLAtMask(DCCG_DISP_CLK_SRCSEL, 0, 0x00000003);
|
||||
Write32Mask(PLL, DCCG_DISP_CLK_SRCSEL, 0, 0x00000003);
|
||||
else
|
||||
write32PLLAtMask(DCCG_DISP_CLK_SRCSEL, 3, 0x00000003);
|
||||
Write32Mask(PLL, DCCG_DISP_CLK_SRCSEL, 3, 0x00000003);
|
||||
|
||||
} // no other action needed
|
||||
break;
|
||||
case RV620_DCCGCLK_RESET:
|
||||
buffer = read32PLL(DCCG_DISP_CLK_SRCSEL) & 0x03;
|
||||
buffer = Read32(PLL, DCCG_DISP_CLK_SRCSEL) & 0x03;
|
||||
|
||||
if (((pllIndex == 0) && (buffer == 0))
|
||||
|| ((pllIndex == 1) && (buffer == 1)))
|
||||
write32PLLAtMask(DCCG_DISP_CLK_SRCSEL, 3, 0x00000003);
|
||||
Write32Mask(PLL, DCCG_DISP_CLK_SRCSEL, 3, 0x00000003);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
@@ -481,14 +481,14 @@ DACPower(uint8 dacIndex, int mode)
|
||||
case RHD_POWER_ON:
|
||||
// TODO : SensedType Detection?
|
||||
powerdown = 0;
|
||||
write32(dacOffset + DACA_ENABLE, 1);
|
||||
write32(dacOffset + DACA_POWERDOWN, 0);
|
||||
Write32(OUT, dacOffset + DACA_ENABLE, 1);
|
||||
Write32(OUT, dacOffset + DACA_POWERDOWN, 0);
|
||||
snooze(14);
|
||||
write32AtMask(dacOffset + DACA_POWERDOWN, powerdown, 0xFFFFFF00);
|
||||
Write32Mask(OUT, dacOffset + DACA_POWERDOWN, powerdown, 0xFFFFFF00);
|
||||
snooze(2);
|
||||
write32(dacOffset + DACA_FORCE_OUTPUT_CNTL, 0);
|
||||
write32AtMask(dacOffset + DACA_SYNC_SELECT, 0, 0x00000101);
|
||||
write32(dacOffset + DACA_SYNC_TRISTATE_CONTROL, 0);
|
||||
Write32(OUT, dacOffset + DACA_FORCE_OUTPUT_CNTL, 0);
|
||||
Write32Mask(OUT, dacOffset + DACA_SYNC_SELECT, 0, 0x00000101);
|
||||
Write32(OUT, dacOffset + DACA_SYNC_TRISTATE_CONTROL, 0);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user