arm64: Configure maximum PA size to the maximum supported by the HW.
* If this was set too small by EFI, some MMIO addresses could end up out of range and trigger Address Size Faults. Change-Id: I29280e1f536cfd64c4711b3b702418cd43699278 Reviewed-on: https://review.haiku-os.org/c/haiku/+/8357 Haiku-Format: Haiku-format Bot <[email protected]> Reviewed-by: Fredrik Holmqvist <[email protected]> Reviewed-by: waddlesplash <[email protected]>
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waddlesplash
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617be7bcdc
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add4a0b683
@@ -189,6 +189,8 @@ static constexpr uint64 TxSZ_MASK = (1 << 6) - 1;
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static constexpr uint64 T0SZ_MASK = TxSZ_MASK;
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static constexpr uint64 T1SZ_MASK = TxSZ_MASK << TCR_T1SZ_SHIFT;
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static constexpr uint64 IPS_MASK = 0x7UL << TCR_IPS_SHIFT;
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static constexpr uint64 TCR_EPD1_DISABLE = (1 << 23);
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static inline uint32 arch_mmu_user_address_bits()
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@@ -122,6 +122,16 @@ void arch_mmu_setup_EL1(uint64 tcr) {
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// TODO: Compiler dependency?
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tcr |= TCR_T1SZ(__builtin_popcountl(KERNEL_BASE));
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// Set the maximum PA size to the maximum supported by the hardware.
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uint64_t pa_size = READ_SPECIALREG(ID_AA64MMFR0_EL1) & ID_AA64MMFR0_PA_RANGE_MASK;
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// PA size of 4 petabytes required 64KB paging granules, which
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// we don't support, so clamp the maximum to 256 terabytes.
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if (pa_size == ID_AA64MMFR0_PA_RANGE_4P)
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pa_size = ID_AA64MMFR0_PA_RANGE_256T;
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tcr &= ~IPS_MASK;
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tcr |= pa_size << TCR_IPS_SHIFT;
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// Flush the cache so that we don't receive unexpected writebacks later.
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_arch_cache_clean_poc();
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