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intel_extreme: Fix DPLL mode selection on gen 3

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* Gen 3 chipsets also have this DPLL mode. 0 is reserved.
This commit is contained in:
Alexander von Gluck IV
2016-01-03 14:50:23 -06:00
parent d35a52e8e2
commit af0dad4771
1 changed files with 2 additions and 2 deletions
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src/add-ons/accelerants/intel_extreme/Ports.cpp
+2 -2
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@@ -302,7 +302,7 @@ AnalogPort::SetDisplayMode(display_mode* target, uint32 colorMode)
compute_pll_divisors(target, &divisors, false);
uint32 extraPLLFlags = 0;
if (gInfo->shared_info->device_type.Generation() >= 4)
if (gInfo->shared_info->device_type.Generation() >= 3)
extraPLLFlags |= DISPLAY_PLL_MODE_NORMAL;
write32(_PortRegister(), (read32(_PortRegister())
@@ -735,7 +735,7 @@ DigitalPort::SetDisplayMode(display_mode* target, uint32 colorMode)
compute_pll_divisors(target, &divisors, false);
uint32 extraPLLFlags = 0;
if (gInfo->shared_info->device_type.Generation() >= 4)
if (gInfo->shared_info->device_type.Generation() >= 3)
extraPLLFlags |= DISPLAY_PLL_MODE_NORMAL;
// Program pipe PLL's