intel_extreme: Add more Tigerlake PCI IDs

* Added all Tigerlake PCI IDs from Intel documentation with all possible
host bridge configurations.
* Tested on 0x9a78 with 0x9A02 host bridge.
* Fixed uppercase letters in PCI IDs to lowercase to match existing code

Change-Id: I5ac8b857b952a2daa93364d9b1c640621d680f5d
Reviewed-on: https://review.haiku-os.org/c/haiku/+/8156
Tested-by: Commit checker robot <[email protected]>
Reviewed-by: Adrien Destugues <[email protected]>
This commit is contained in:
Ilmari "ilzu" Siiteri
2024-09-12 17:41:42 +00:00
committed by Adrien Destugues
parent fbf5967e67
commit afa8cd9c31
2 changed files with 17 additions and 0 deletions
@@ -223,7 +223,19 @@ const struct supported_device {
{0x4e26, 0x4e71, INTEL_MODEL_JSLM, "JasperLake"},
{0x4e28, 0x4e71, INTEL_MODEL_JSLM, "JasperLake"},
{0x9a12, 0x9a49, INTEL_MODEL_TGLM, "TigerLake-LP GT2"},
{0x9a12, 0x9a78, INTEL_MODEL_TGLM, "TigerLake-LP GT2"},
{0x9a02, 0x9a49, INTEL_MODEL_TGLM, "TigerLake-LP GT2"},
{0x9a02, 0x9a78, INTEL_MODEL_TGLM, "TigerLake-LP GT2"},
{0x9a14, 0x9a49, INTEL_MODEL_TGLM, "TigerLake-LP GT2"},
{0x9a14, 0x9a78, INTEL_MODEL_TGLM, "TigerLake-LP GT2"},
{0x9a04, 0x9a49, INTEL_MODEL_TGLM, "TigerLake-LP GT2"},
{0x9a04, 0x9a78, INTEL_MODEL_TGLM, "TigerLake-LP GT2"},
{0x9a1a, 0x9a49, INTEL_MODEL_TGLM, "TigerLake-LP GT2"},
{0x9a36, 0x9a60, INTEL_MODEL_TGLM, "TigerLake-LP GT1"},
{0x9a36, 0x9a68, INTEL_MODEL_TGLM, "TigerLake-LP GT1"},
{0x9a26, 0x9a60, INTEL_MODEL_TGLM, "TigerLake-LP GT1"},
{0x9a26, 0x9a68, INTEL_MODEL_TGLM, "TigerLake-LP GT1"},
};
struct intel_info {
@@ -202,6 +202,11 @@ const struct supported_device {
{0x4e71, INTEL_MODEL_JSLM, "JasperLake"},
{0x9a49, INTEL_MODEL_TGLM, "TigerLake"},
{0x9a78, INTEL_MODEL_TGLM, "TigerLake"},
{0x9a40, INTEL_MODEL_TGLM, "TigerLake"},
{0x9a60, INTEL_MODEL_TGLM, "TigerLake"},
{0x9a68, INTEL_MODEL_TGLM, "TigerLake"},
{0x9a70, INTEL_MODEL_TGLM, "TigerLake"},
};
int32 api_version = B_CUR_DRIVER_API_VERSION;