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ARM: Break apart ARMv5 and older dsb/dmb

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* Add isb just because.
* pdziepak pointed out that ARMv5 and before
  had different barrier support.
* pdziepak also mentioned that dsb was too strong
  for __sync_synchronize
This commit is contained in:
Alexander von Gluck IV
2014-02-26 13:17:21 -06:00
parent a21611e439
commit b6994f96c0
2 changed files with 11 additions and 3 deletions
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headers/private/kernel/arch/arm/arch_atomic.h
+10 -2
View File
@@ -9,12 +9,20 @@
#define _KERNEL_ARCH_ARM_ATOMIC_H #define _KERNEL_ARCH_ARM_ATOMIC_H
#if __ARM_ARCH__ <= 6 #if __ARM_ARCH__ <= 5
#define isb() __asm__ __volatile__("" : : : "memory")
#define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \
: : "r" (0) : "memory")
#define dmb() __asm__ __volatile__("" : : : "memory")
#elif __ARM_ARCH__ == 6
#define isb() __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 4" \
: : "r" (0) : "memory")
#define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \ #define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \
: : "r" (0) : "memory") : : "r" (0) : "memory")
#define dmb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \ #define dmb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \
: : "r" (0) : "memory") : : "r" (0) : "memory")
#else #else /* ARMv7+ */
#define isb() __asm__ __volatile__("isb" : : : "memory")
#define dsb() __asm__ __volatile__("dsb" : : : "memory") #define dsb() __asm__ __volatile__("dsb" : : : "memory")
#define dmb() __asm__ __volatile__("dmb" : : : "memory") #define dmb() __asm__ __volatile__("dmb" : : : "memory")
#endif #endif
src/system/libroot/os/arch/arm/thread.c
+1 -1
View File
@@ -27,5 +27,5 @@ find_thread(const char *name)
void void
__sync_synchronize(void) __sync_synchronize(void)
{ {
dsb(); dmb();
} }