Fix SandyBridge support.

This reverts commit 4f2b258c32.
This reverts commit c86f3dba23.
This reverts commit 61fbdb0667.
This reverts commit b3f14fb7c7.

headers/private/graphics/intel_extreme/intel_extreme.h

@@ -520,18 +520,18 @@ struct intel_free_graphics_memory {
 
 #define INTEL_DISPLAY_OFFSET			0x1000
 
-#define INTEL_DISPLAY_A_HTOTAL			(0x0000 | REGS_NORTH_PIPE_AND_PORT)
-#define INTEL_DISPLAY_A_HBLANK			(0x0004 | REGS_NORTH_PIPE_AND_PORT)
-#define INTEL_DISPLAY_A_HSYNC			(0x0008 | REGS_NORTH_PIPE_AND_PORT)
-#define INTEL_DISPLAY_A_VTOTAL			(0x000c | REGS_NORTH_PIPE_AND_PORT)
-#define INTEL_DISPLAY_A_VBLANK			(0x0010 | REGS_NORTH_PIPE_AND_PORT)
-#define INTEL_DISPLAY_A_VSYNC			(0x0014 | REGS_NORTH_PIPE_AND_PORT)
-#define INTEL_DISPLAY_B_HTOTAL			(0x1000 | REGS_NORTH_PIPE_AND_PORT)
-#define INTEL_DISPLAY_B_HBLANK			(0x1004 | REGS_NORTH_PIPE_AND_PORT)
-#define INTEL_DISPLAY_B_HSYNC			(0x1008 | REGS_NORTH_PIPE_AND_PORT)
-#define INTEL_DISPLAY_B_VTOTAL			(0x100c | REGS_NORTH_PIPE_AND_PORT)
-#define INTEL_DISPLAY_B_VBLANK			(0x1010 | REGS_NORTH_PIPE_AND_PORT)
-#define INTEL_DISPLAY_B_VSYNC			(0x1014 | REGS_NORTH_PIPE_AND_PORT)
+#define INTEL_DISPLAY_A_HTOTAL			(0x0000 | REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_DISPLAY_A_HBLANK			(0x0004 | REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_DISPLAY_A_HSYNC			(0x0008 | REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_DISPLAY_A_VTOTAL			(0x000c | REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_DISPLAY_A_VBLANK			(0x0010 | REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_DISPLAY_A_VSYNC			(0x0014 | REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_DISPLAY_B_HTOTAL			(0x1000 | REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_DISPLAY_B_HBLANK			(0x1004 | REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_DISPLAY_B_HSYNC			(0x1008 | REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_DISPLAY_B_VTOTAL			(0x100c | REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_DISPLAY_B_VBLANK			(0x1010 | REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_DISPLAY_B_VSYNC			(0x1014 | REGS_SOUTH_TRANSCODER_PORT)
 
 #define INTEL_DISPLAY_A_IMAGE_SIZE		(0x001c | REGS_NORTH_PIPE_AND_PORT)
 #define INTEL_DISPLAY_B_IMAGE_SIZE		(0x101c | REGS_NORTH_PIPE_AND_PORT)

src/add-ons/accelerants/intel_extreme/Pipes.cpp

@@ -182,31 +182,31 @@ Pipe::ConfigureTimings(display_mode* target)
 		return;
 	}
 
-	// update timing (fPipeOffset bumps the DISPLAY_A to B when needed)
-	write32(INTEL_DISPLAY_A_HTOTAL + fPipeOffset,
+	// update timing parameters
+	write32(INTEL_DISPLAY_A_HTOTAL,
 		((uint32)(target->timing.h_total - 1) << 16)
 		| ((uint32)target->timing.h_display - 1));
-	write32(INTEL_DISPLAY_A_HBLANK + fPipeOffset,
+	write32(INTEL_DISPLAY_A_HBLANK,
 		((uint32)(target->timing.h_total - 1) << 16)
 		| ((uint32)target->timing.h_display - 1));
-	write32(INTEL_DISPLAY_A_HSYNC + fPipeOffset,
+	write32(INTEL_DISPLAY_A_HSYNC,
 		((uint32)(target->timing.h_sync_end - 1) << 16)
 		| ((uint32)target->timing.h_sync_start - 1));
 
-	write32(INTEL_DISPLAY_A_VTOTAL + fPipeOffset,
+	write32(INTEL_DISPLAY_A_VTOTAL,
 		((uint32)(target->timing.v_total - 1) << 16)
 		| ((uint32)target->timing.v_display - 1));
-	write32(INTEL_DISPLAY_A_VBLANK + fPipeOffset,
+	write32(INTEL_DISPLAY_A_VBLANK,
 		((uint32)(target->timing.v_total - 1) << 16)
 		| ((uint32)target->timing.v_display - 1));
-	write32(INTEL_DISPLAY_A_VSYNC + fPipeOffset,
+	write32(INTEL_DISPLAY_A_VSYNC,
 		((uint32)(target->timing.v_sync_end - 1) << 16)
 		| ((uint32)target->timing.v_sync_start - 1));
 
 	// XXX: Is it ok to do these on non-digital?
 
 	write32(INTEL_DISPLAY_A_POS + fPipeOffset, 0);
-	write32(INTEL_DISPLAY_A_IMAGE_SIZE + fPipeOffset,
+	write32(INTEL_DISPLAY_A_IMAGE_SIZE,
 		((uint32)(target->virtual_width - 1) << 16)
 			| ((uint32)target->virtual_height - 1));
 
@@ -245,8 +245,8 @@ Pipe::ConfigureClocks(const pll_divisors& divisors, uint32 pixelClock,
 	float refFreq = gInfo->shared_info->pll_info.reference_frequency / 1000.0f;
 
 	if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x)) {
-		float adjusted = ((refFreq * divisors.m) / divisors.n) 	/ divisors.p;
-		uint32 pixelMultiply = uint32(adjusted 	/ (pixelClock / 1000.0f));
+		float adjusted = ((refFreq * divisors.m) / divisors.n) / divisors.p;
+		uint32 pixelMultiply = uint32(adjusted / (pixelClock / 1000.0f));
 		write32(pllMD, (0 << 24) | ((pixelMultiply - 1) << 8));
 	}
 

src/add-ons/accelerants/intel_extreme/Ports.cpp

@@ -354,11 +354,14 @@ LVDSPort::LVDSPort()
 	:
 	Port(INTEL_PORT_C, "LVDS")
 {
+#if 0
+	// FIXME results in black screen on SandyBridge
 	// Always unlock LVDS port as soon as we start messing with it.
 	uint32 panelControl = INTEL_PANEL_CONTROL;
 	if (gInfo->shared_info->pch_info != INTEL_PCH_NONE)
 		panelControl = PCH_PANEL_CONTROL;
 	write32(panelControl, read32(panelControl) | PANEL_REGISTER_UNLOCK);
+#endif
 }
 
 

src/add-ons/accelerants/intel_extreme/accelerant.cpp

@@ -373,6 +373,9 @@ probe_ports()
 		foundLVDS = true;
 		gInfo->ports[gInfo->port_count++] = lvdsPort;
 		gInfo->head_mode |= HEAD_MODE_LVDS_PANEL;
+		gInfo->head_mode |= HEAD_MODE_A_ANALOG;
+			// FIXME this should not be set, but without it, LVDS modesetting
+			// doesn't work on SandyBridge. Find out why it makes a difference.
 		gInfo->head_mode |= HEAD_MODE_B_DIGITAL;
 	} else
 		delete lvdsPort;

src/add-ons/accelerants/intel_extreme/dpms.cpp

@@ -47,6 +47,10 @@ static void
 enable_lvds_panel(bool enable)
 {
 	bool hasPCH = (gInfo->shared_info->pch_info != INTEL_PCH_NONE);
+	if (hasPCH) {
+		// TODO: fix for PCH (does not enable the panel - crashes?)
+		return;
+	}
 
 	int controlRegister = hasPCH ? PCH_PANEL_CONTROL : INTEL_PANEL_CONTROL;
 	int statusRegister = hasPCH ? PCH_PANEL_STATUS : INTEL_PANEL_STATUS;