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removed more nvidia refs

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@9796 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2004-11-04 16:15:08 +00:00
parent 024b8e7bd1
commit bf1feef864
16 changed files with 937 additions and 937 deletions
Download Patch File Download Diff File Expand all files Collapse all files
headers/private/graphics/skeleton/DriverInterface.h
+10 -10
View File
@@ -38,7 +38,7 @@ typedef struct {
#define DELETE_BEN(x) delete_sem(x.sem); #define DELETE_BEN(x) delete_sem(x.sem);
#define NV_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ #define SKEL_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */
/*dualhead extensions to flags*/ /*dualhead extensions to flags*/
#define DUALHEAD_OFF (0<<6) #define DUALHEAD_OFF (0<<6)
@@ -61,15 +61,15 @@ typedef struct {
#define SKD_HANDLER_INSTALLED 0x80000000 #define SKD_HANDLER_INSTALLED 0x80000000
enum { enum {
NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, ENG_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
NV_GET_PCI, ENG_GET_PCI,
NV_SET_PCI, ENG_SET_PCI,
NV_DEVICE_NAME, ENG_DEVICE_NAME,
NV_RUN_INTERRUPTS, ENG_RUN_INTERRUPTS,
NV_GET_NTH_AGP_INFO, ENG_GET_NTH_AGP_INFO,
NV_ENABLE_AGP, ENG_ENABLE_AGP,
NV_ISA_OUT, ENG_ISA_OUT,
NV_ISA_IN ENG_ISA_IN
}; };
/* max. number of overlay buffers */ /* max. number of overlay buffers */
headers/private/graphics/skeleton/macros.h
+702 -702
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File diff suppressed because it is too large Load Diff
src/add-ons/accelerants/skeleton/InitAccelerant.c
+5 -5
View File
@@ -25,9 +25,9 @@ static status_t init_common(int the_fd) {
/* memorize the file descriptor */ /* memorize the file descriptor */
fd = the_fd; fd = the_fd;
/* set the magic number so the driver knows we're for real */ /* set the magic number so the driver knows we're for real */
gpd.magic = NV_PRIVATE_DATA_MAGIC; gpd.magic = SKEL_PRIVATE_DATA_MAGIC;
/* contact driver and get a pointer to the registers and shared data */ /* contact driver and get a pointer to the registers and shared data */
result = ioctl(fd, NV_GET_PRIVATE_DATA, &gpd, sizeof(gpd)); result = ioctl(fd, ENG_GET_PRIVATE_DATA, &gpd, sizeof(gpd));
if (result != B_OK) goto error0; if (result != B_OK) goto error0;
/* clone the shared area for our use */ /* clone the shared area for our use */
@@ -211,7 +211,7 @@ ssize_t ACCELERANT_CLONE_INFO_SIZE(void) {
Since we're passing the name of the device as the only required Since we're passing the name of the device as the only required
info, return the size of the name buffer info, return the size of the name buffer
*/ */
return B_OS_NAME_LENGTH; // apsed, was MAX_NV_DEVICE_NAME_LENGTH; return B_OS_NAME_LENGTH; // apsed, was MAX_ENG_DEVICE_NAME_LENGTH;
} }
@@ -224,10 +224,10 @@ void GET_ACCELERANT_CLONE_INFO(void *data) {
status_t result; status_t result;
/* call the kernel driver to get the device name */ /* call the kernel driver to get the device name */
dn.magic = NV_PRIVATE_DATA_MAGIC; dn.magic = SKEL_PRIVATE_DATA_MAGIC;
/* store the returned info directly into the passed buffer */ /* store the returned info directly into the passed buffer */
dn.name = (char *)data; dn.name = (char *)data;
result = ioctl(fd, NV_DEVICE_NAME, &dn, sizeof(dn)); result = ioctl(fd, ENG_DEVICE_NAME, &dn, sizeof(dn));
} }
/* /*
src/add-ons/accelerants/skeleton/SetDisplayMode.c
+2 -2
View File
@@ -22,10 +22,10 @@ static void interrupt_enable(bool flag) {
eng_set_bool_state sbs; eng_set_bool_state sbs;
/* set the magic number so the driver knows we're for real */ /* set the magic number so the driver knows we're for real */
sbs.magic = NV_PRIVATE_DATA_MAGIC; sbs.magic = SKEL_PRIVATE_DATA_MAGIC;
sbs.do_it = flag; sbs.do_it = flag;
/* contact driver and get a pointer to the registers and shared data */ /* contact driver and get a pointer to the registers and shared data */
result = ioctl(fd, NV_RUN_INTERRUPTS, &sbs, sizeof(sbs)); result = ioctl(fd, ENG_RUN_INTERRUPTS, &sbs, sizeof(sbs));
} }
/* First validate the mode, then call lots of bit banging stuff to set the mode(s)! */ /* First validate the mode, then call lots of bit banging stuff to set the mode(s)! */
src/add-ons/accelerants/skeleton/engine/acc.c
+13 -13
View File
@@ -52,7 +52,7 @@ status_t eng_acc_init()
if (si->ps.card_arch == NV04A) if (si->ps.card_arch == NV04A)
{ {
/* set framebuffer config: type = notiling, PRAMIN write access enabled */ /* set framebuffer config: type = notiling, PRAMIN write access enabled */
NV_REG32(NV32_PFB_CONFIG_0) = 0x00001114; ENG_RG32(RG32_PFB_CONFIG_0) = 0x00001114;
} }
/*** PFIFO ***/ /*** PFIFO ***/
@@ -685,7 +685,7 @@ status_t eng_acc_init()
* setup clipping region (workspace size) to 32768 x 32768 pixels: * setup clipping region (workspace size) to 32768 x 32768 pixels:
* wait for room in fifo for clipping cmd if needed. * wait for room in fifo for clipping cmd if needed.
* (fifo holds 256 32bit words: count those, not bytes) */ * (fifo holds 256 32bit words: count those, not bytes) */
while (((NV_REG16(NV16_CLP_FIFOFREE)) >> 2) < 2) while (((ENG_REG16(RG16_CLP_FIFOFREE)) >> 2) < 2)
{ {
/* snooze a bit so I do not hammer the bus */ /* snooze a bit so I do not hammer the bus */
snooze (10); snooze (10);
@@ -703,7 +703,7 @@ status_t eng_acc_setup_blit()
/* setup solid pattern: /* setup solid pattern:
* wait for room in fifo for pattern cmd if needed. * wait for room in fifo for pattern cmd if needed.
* (fifo holds 256 32bit words: count those, not bytes) */ * (fifo holds 256 32bit words: count those, not bytes) */
while (((NV_REG16(NV16_PAT_FIFOFREE)) >> 2) < 5) while (((ENG_REG16(RG16_PAT_FIFOFREE)) >> 2) < 5)
{ {
/* snooze a bit so I do not hammer the bus */ /* snooze a bit so I do not hammer the bus */
snooze (10); snooze (10);
@@ -718,7 +718,7 @@ status_t eng_acc_setup_blit()
/* ROP3 registers (Raster OPeration): /* ROP3 registers (Raster OPeration):
* wait for room in fifo for ROP cmd if needed. * wait for room in fifo for ROP cmd if needed.
* (fifo holds 256 32bit words: count those, not bytes) */ * (fifo holds 256 32bit words: count those, not bytes) */
while (((NV_REG16(NV16_ROP_FIFOFREE)) >> 2) < 1) while (((ENG_REG16(RG16_ROP_FIFOFREE)) >> 2) < 1)
{ {
/* snooze a bit so I do not hammer the bus */ /* snooze a bit so I do not hammer the bus */
snooze (10); snooze (10);
@@ -736,7 +736,7 @@ status_t eng_acc_blit(uint16 xs,uint16 ys,uint16 xd,uint16 yd,uint16 w,uint16 h)
/* instruct engine what to blit: /* instruct engine what to blit:
* wait for room in fifo for blit cmd if needed. * wait for room in fifo for blit cmd if needed.
* (fifo holds 256 32bit words: count those, not bytes) */ * (fifo holds 256 32bit words: count those, not bytes) */
while (((NV_REG16(NV16_BLT_FIFOFREE)) >> 2) < 3) while (((ENG_REG16(RG16_BLT_FIFOFREE)) >> 2) < 3)
{ {
/* snooze a bit so I do not hammer the bus */ /* snooze a bit so I do not hammer the bus */
snooze (10); snooze (10);
@@ -756,7 +756,7 @@ status_t eng_acc_setup_rectangle(uint32 color)
/* setup solid pattern: /* setup solid pattern:
* wait for room in fifo for pattern cmd if needed. * wait for room in fifo for pattern cmd if needed.
* (fifo holds 256 32bit words: count those, not bytes) */ * (fifo holds 256 32bit words: count those, not bytes) */
while (((NV_REG16(NV16_PAT_FIFOFREE)) >> 2) < 5) while (((ENG_REG16(RG16_PAT_FIFOFREE)) >> 2) < 5)
{ {
/* snooze a bit so I do not hammer the bus */ /* snooze a bit so I do not hammer the bus */
snooze (10); snooze (10);
@@ -771,7 +771,7 @@ status_t eng_acc_setup_rectangle(uint32 color)
/* ROP3 registers (Raster OPeration): /* ROP3 registers (Raster OPeration):
* wait for room in fifo for ROP cmd if needed. * wait for room in fifo for ROP cmd if needed.
* (fifo holds 256 32bit words: count those, not bytes) */ * (fifo holds 256 32bit words: count those, not bytes) */
while (((NV_REG16(NV16_ROP_FIFOFREE)) >> 2) < 1) while (((ENG_REG16(RG16_ROP_FIFOFREE)) >> 2) < 1)
{ {
/* snooze a bit so I do not hammer the bus */ /* snooze a bit so I do not hammer the bus */
snooze (10); snooze (10);
@@ -782,7 +782,7 @@ status_t eng_acc_setup_rectangle(uint32 color)
/* setup fill color: /* setup fill color:
* wait for room in fifo for bitmap cmd if needed. * wait for room in fifo for bitmap cmd if needed.
* (fifo holds 256 32bit words: count those, not bytes) */ * (fifo holds 256 32bit words: count those, not bytes) */
while (((NV_REG16(NV16_BMP_FIFOFREE)) >> 2) < 1) while (((ENG_REG16(RG16_BMP_FIFOFREE)) >> 2) < 1)
{ {
/* snooze a bit so I do not hammer the bus */ /* snooze a bit so I do not hammer the bus */
snooze (10); snooze (10);
@@ -798,7 +798,7 @@ status_t eng_acc_rectangle(uint32 xs,uint32 xe,uint32 ys,uint32 yl)
/* instruct engine what to fill: /* instruct engine what to fill:
* wait for room in fifo for bitmap cmd if needed. * wait for room in fifo for bitmap cmd if needed.
* (fifo holds 256 32bit words: count those, not bytes) */ * (fifo holds 256 32bit words: count those, not bytes) */
while (((NV_REG16(NV16_BMP_FIFOFREE)) >> 2) < 2) while (((ENG_REG16(RG16_BMP_FIFOFREE)) >> 2) < 2)
{ {
/* snooze a bit so I do not hammer the bus */ /* snooze a bit so I do not hammer the bus */
snooze (10); snooze (10);
@@ -816,7 +816,7 @@ status_t eng_acc_setup_rect_invert()
/* setup solid pattern: /* setup solid pattern:
* wait for room in fifo for pattern cmd if needed. * wait for room in fifo for pattern cmd if needed.
* (fifo holds 256 32bit words: count those, not bytes) */ * (fifo holds 256 32bit words: count those, not bytes) */
while (((NV_REG16(NV16_PAT_FIFOFREE)) >> 2) < 5) while (((ENG_REG16(RG16_PAT_FIFOFREE)) >> 2) < 5)
{ {
/* snooze a bit so I do not hammer the bus */ /* snooze a bit so I do not hammer the bus */
snooze (10); snooze (10);
@@ -831,7 +831,7 @@ status_t eng_acc_setup_rect_invert()
/* ROP3 registers (Raster OPeration): /* ROP3 registers (Raster OPeration):
* wait for room in fifo for ROP cmd if needed. * wait for room in fifo for ROP cmd if needed.
* (fifo holds 256 32bit words: count those, not bytes) */ * (fifo holds 256 32bit words: count those, not bytes) */
while (((NV_REG16(NV16_ROP_FIFOFREE)) >> 2) < 1) while (((ENG_REG16(RG16_ROP_FIFOFREE)) >> 2) < 1)
{ {
/* snooze a bit so I do not hammer the bus */ /* snooze a bit so I do not hammer the bus */
snooze (10); snooze (10);
@@ -842,7 +842,7 @@ status_t eng_acc_setup_rect_invert()
/* reset fill color: /* reset fill color:
* wait for room in fifo for bitmap cmd if needed. * wait for room in fifo for bitmap cmd if needed.
* (fifo holds 256 32bit words: count those, not bytes) */ * (fifo holds 256 32bit words: count those, not bytes) */
while (((NV_REG16(NV16_BMP_FIFOFREE)) >> 2) < 1) while (((ENG_REG16(RG16_BMP_FIFOFREE)) >> 2) < 1)
{ {
/* snooze a bit so I do not hammer the bus */ /* snooze a bit so I do not hammer the bus */
snooze (10); snooze (10);
@@ -858,7 +858,7 @@ status_t eng_acc_rectangle_invert(uint32 xs,uint32 xe,uint32 ys,uint32 yl)
/* instruct engine what to invert: /* instruct engine what to invert:
* wait for room in fifo for bitmap cmd if needed. * wait for room in fifo for bitmap cmd if needed.
* (fifo holds 256 32bit words: count those, not bytes) */ * (fifo holds 256 32bit words: count those, not bytes) */
while (((NV_REG16(NV16_BMP_FIFOFREE)) >> 2) < 2) while (((ENG_REG16(RG16_BMP_FIFOFREE)) >> 2) < 2)
{ {
/* snooze a bit so I do not hammer the bus */ /* snooze a bit so I do not hammer the bus */
snooze (10); snooze (10);
src/add-ons/accelerants/skeleton/engine/agp.c
+10 -10
View File
@@ -25,26 +25,26 @@ status_t eng_agp_setup(void)
{ {
uint32 reg; uint32 reg;
LOG(4, ("AGP: STRAPINFO2 contains $%08x\n", NV_REG32(NV32_NVSTRAPINFO2))); LOG(4, ("AGP: STRAPINFO2 contains $%08x\n", ENG_RG32(RG32_NVSTRAPINFO2)));
LOG(4, ("AGP: attempting to enable fastwrite support..\n")); LOG(4, ("AGP: attempting to enable fastwrite support..\n"));
/* 'force' FW support */ /* 'force' FW support */
reg = (NV_REG32(NV32_NVSTRAPINFO2) & ~0x00000800); reg = (ENG_RG32(RG32_NVSTRAPINFO2) & ~0x00000800);
/* enable strapinfo overwrite */ /* enable strapinfo overwrite */
NV_REG32(NV32_NVSTRAPINFO2) = (reg | 0x80000000); ENG_RG32(RG32_NVSTRAPINFO2) = (reg | 0x80000000);
LOG(4, ("AGP: STRAPINFO2 now contains $%08x\n", NV_REG32(NV32_NVSTRAPINFO2))); LOG(4, ("AGP: STRAPINFO2 now contains $%08x\n", ENG_RG32(RG32_NVSTRAPINFO2)));
} }
/* set the magic number so the skeleton kerneldriver knows we're for real */ /* set the magic number so the skeleton kerneldriver knows we're for real */
nca.magic = nai.magic = NV_PRIVATE_DATA_MAGIC; nca.magic = nai.magic = SKEL_PRIVATE_DATA_MAGIC;
/* contact driver and get a pointer to the registers and shared data */ /* contact driver and get a pointer to the registers and shared data */
for (index = 0; index < 8; index++) for (index = 0; index < 8; index++)
{ {
/* get nth AGP device info */ /* get nth AGP device info */
nai.index = index; nai.index = index;
ioctl(fd, NV_GET_NTH_AGP_INFO, &nai, sizeof(nai)); ioctl(fd, ENG_GET_NTH_AGP_INFO, &nai, sizeof(nai));
/* abort if no agp busmanager found */ /* abort if no agp busmanager found */
if (!nai.agp_bus) if (!nai.agp_bus)
@@ -88,8 +88,8 @@ status_t eng_agp_setup(void)
/* if our card is not an AGP type, abort here */ /* if our card is not an AGP type, abort here */
/* Note: /* Note:
* We have to iterate through the capability list as specified in the PCI spec * We have to iterate through the capability list as specified in the PCI spec
* one way or the other, otherwise we cannot distinquish between nVidia PCI and * one way or the other, otherwise we cannot distinquish between PCI and
* AGP type cards as nVidia PCI cards still have AGP registers that pretend to * AGP type cards as PCI cards still might have AGP registers that pretend to
* support AGP. * support AGP.
* We rely on the AGP busmanager to iterate trough this list for us. */ * We rely on the AGP busmanager to iterate trough this list for us. */
if (!agp) if (!agp)
@@ -110,7 +110,7 @@ status_t eng_agp_setup(void)
/* let the AGP busmanager setup PCI mode. /* let the AGP busmanager setup PCI mode.
* (the AGP speed scheme is of no consequence now) */ * (the AGP speed scheme is of no consequence now) */
nca.cmd = 0x00000000; nca.cmd = 0x00000000;
ioctl(fd, NV_ENABLE_AGP, &nca, sizeof(nca)); ioctl(fd, ENG_ENABLE_AGP, &nca, sizeof(nca));
} }
else else
{ {
@@ -121,7 +121,7 @@ status_t eng_agp_setup(void)
nca.cmd = 0xfffffff7; nca.cmd = 0xfffffff7;
/* ..but we do need to select the right speed scheme fetched from our card */ /* ..but we do need to select the right speed scheme fetched from our card */
if (eng_ai.interface.agp_stat & AGP_rate_rev) nca.cmd |= AGP_rate_rev; if (eng_ai.interface.agp_stat & AGP_rate_rev) nca.cmd |= AGP_rate_rev;
ioctl(fd, NV_ENABLE_AGP, &nca, sizeof(nca)); ioctl(fd, ENG_ENABLE_AGP, &nca, sizeof(nca));
} }
/* list mode now activated, /* list mode now activated,
src/add-ons/accelerants/skeleton/engine/bes.c
+4 -4
View File
@@ -357,16 +357,16 @@ status_t eng_bes_to_crtc(bool crtc)
{ {
LOG(4,("Overlay: switching overlay to CRTC2\n")); LOG(4,("Overlay: switching overlay to CRTC2\n"));
/* switch overlay engine to CRTC2 */ /* switch overlay engine to CRTC2 */
NV_REG32(NV32_FUNCSEL) &= ~0x00001000; ENG_RG32(RG32_FUNCSEL) &= ~0x00001000;
NV_REG32(NV32_2FUNCSEL) |= 0x00001000; ENG_RG32(RG32_2FUNCSEL) |= 0x00001000;
si->overlay.crtc = !si->crtc_switch_mode; si->overlay.crtc = !si->crtc_switch_mode;
} }
else else
{ {
LOG(4,("Overlay: switching overlay to CRTC1\n")); LOG(4,("Overlay: switching overlay to CRTC1\n"));
/* switch overlay engine to CRTC1 */ /* switch overlay engine to CRTC1 */
NV_REG32(NV32_2FUNCSEL) &= ~0x00001000; ENG_RG32(RG32_2FUNCSEL) &= ~0x00001000;
NV_REG32(NV32_FUNCSEL) |= 0x00001000; ENG_RG32(RG32_FUNCSEL) |= 0x00001000;
si->overlay.crtc = si->crtc_switch_mode; si->overlay.crtc = si->crtc_switch_mode;
} }
return B_OK; return B_OK;
src/add-ons/accelerants/skeleton/engine/crtc.c
+9 -9
View File
@@ -280,7 +280,7 @@ status_t eng_crtc_set_timing(display_mode target)
/* setup HSYNC & VSYNC polarity */ /* setup HSYNC & VSYNC polarity */
LOG(2,("CRTC: sync polarity: ")); LOG(2,("CRTC: sync polarity: "));
temp = NV_REG8(NV8_MISCR); temp = ENG_REG8(RG8_MISCR);
if (target.timing.flags & B_POSITIVE_HSYNC) if (target.timing.flags & B_POSITIVE_HSYNC)
{ {
LOG(2,("H:pos ")); LOG(2,("H:pos "));
@@ -301,9 +301,9 @@ status_t eng_crtc_set_timing(display_mode target)
LOG(2,("V:neg ")); LOG(2,("V:neg "));
temp |= 0x80; temp |= 0x80;
} }
NV_REG8(NV8_MISCW) = temp; ENG_REG8(RG8_MISCW) = temp;
LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); LOG(2,(", MISC reg readback: $%02x\n", ENG_REG8(RG8_MISCR)));
} }
/* always disable interlaced operation */ /* always disable interlaced operation */
@@ -610,7 +610,7 @@ status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp)
/* we might have no retraces during setmode! */ /* we might have no retraces during setmode! */
/* wait 25mS max. for retrace to occur (refresh > 40Hz) */ /* wait 25mS max. for retrace to occur (refresh > 40Hz) */
while (((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) && while (((ENG_RG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display) &&
(timeout < (25000/10))) (timeout < (25000/10)))
{ {
/* don't snooze much longer or retrace might get missed! */ /* don't snooze much longer or retrace might get missed! */
@@ -646,7 +646,7 @@ status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp)
* wrap-around at 16Mb boundaries!! */ * wrap-around at 16Mb boundaries!! */
/* 30bit adress in 32bit words */ /* 30bit adress in 32bit words */
NV_REG32(NV32_NV10FBSTADD32) = (startadd & 0xfffffffc); ENG_RG32(RG32_NV10FBSTADD32) = (startadd & 0xfffffffc);
} }
/* set NV4/NV10 byte adress: (b0 - 1) */ /* set NV4/NV10 byte adress: (b0 - 1) */
@@ -686,7 +686,7 @@ status_t eng_crtc_cursor_init()
* This register does not exist on pre-NV10 and 'Go' cards. */ * This register does not exist on pre-NV10 and 'Go' cards. */
/* cursorbitmap must still start on 2Kbyte boundary: */ /* cursorbitmap must still start on 2Kbyte boundary: */
NV_REG32(NV32_NV10CURADD32) = (curadd & 0xfffff800); ENG_RG32(RG32_NV10CURADD32) = (curadd & 0xfffff800);
} }
/* set cursor colour: not needed because of direct nature of cursor bitmap. */ /* set cursor colour: not needed because of direct nature of cursor bitmap. */
@@ -699,7 +699,7 @@ status_t eng_crtc_cursor_init()
} }
/* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */
NV_REG32(NV32_CURCONF) = 0x02000100; ENG_RG32(RG32_CURCONF) = 0x02000100;
/* activate hardware cursor */ /* activate hardware cursor */
eng_crtc_cursor_show(); eng_crtc_cursor_show();
@@ -807,7 +807,7 @@ status_t eng_crtc_cursor_position(uint16 x, uint16 y)
{ {
/* we have vertical lines below old and new cursorposition to spare. So we /* we have vertical lines below old and new cursorposition to spare. So we
* update the cursor postion 'mid-screen', but below that area. */ * update the cursor postion 'mid-screen', but below that area. */
while (((uint16)(NV_REG32(NV32_RASTER) & 0x000007ff)) < (yhigh + 16)) while (((uint16)(ENG_RG32(RG32_RASTER) & 0x000007ff)) < (yhigh + 16))
{ {
snooze(10); snooze(10);
} }
@@ -815,7 +815,7 @@ status_t eng_crtc_cursor_position(uint16 x, uint16 y)
else else
{ {
/* no room to spare, just wait for retrace (is relatively slow) */ /* no room to spare, just wait for retrace (is relatively slow) */
while ((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) while ((ENG_RG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display)
{ {
/* don't snooze much longer or retrace might get missed! */ /* don't snooze much longer or retrace might get missed! */
snooze(10); snooze(10);
src/add-ons/accelerants/skeleton/engine/crtc2.c
+9 -9
View File
@@ -263,7 +263,7 @@ status_t eng_crtc2_set_timing(display_mode target)
/* setup HSYNC & VSYNC polarity */ /* setup HSYNC & VSYNC polarity */
LOG(2,("CRTC2: sync polarity: ")); LOG(2,("CRTC2: sync polarity: "));
temp = NV_REG8(NV8_MISCR); temp = ENG_REG8(RG8_MISCR);
if (target.timing.flags & B_POSITIVE_HSYNC) if (target.timing.flags & B_POSITIVE_HSYNC)
{ {
LOG(2,("H:pos ")); LOG(2,("H:pos "));
@@ -284,9 +284,9 @@ status_t eng_crtc2_set_timing(display_mode target)
LOG(2,("V:neg ")); LOG(2,("V:neg "));
temp |= 0x80; temp |= 0x80;
} }
NV_REG8(NV8_MISCW) = temp; ENG_REG8(RG8_MISCW) = temp;
LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); LOG(2,(", MISC reg readback: $%02x\n", ENG_REG8(RG8_MISCR)));
} }
/* always disable interlaced operation */ /* always disable interlaced operation */
@@ -592,7 +592,7 @@ status_t eng_crtc2_set_display_start(uint32 startadd,uint8 bpp)
/* we might have no retraces during setmode! */ /* we might have no retraces during setmode! */
/* wait 25mS max. for retrace to occur (refresh > 40Hz) */ /* wait 25mS max. for retrace to occur (refresh > 40Hz) */
while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && while (((ENG_RG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) &&
(timeout < (25000/10))) (timeout < (25000/10)))
{ {
/* don't snooze much longer or retrace might get missed! */ /* don't snooze much longer or retrace might get missed! */
@@ -609,7 +609,7 @@ status_t eng_crtc2_set_display_start(uint32 startadd,uint8 bpp)
* wrap-around at 16Mb boundaries!! */ * wrap-around at 16Mb boundaries!! */
/* 30bit adress in 32bit words */ /* 30bit adress in 32bit words */
NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc); ENG_RG32(RG32_NV10FB2STADD32) = (startadd & 0xfffffffc);
/* set byte adress: (b0 - 1) */ /* set byte adress: (b0 - 1) */
ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1)); ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1));
@@ -648,7 +648,7 @@ status_t eng_crtc2_cursor_init()
* This register does not exist on pre-NV10 and 'Go' cards. */ * This register does not exist on pre-NV10 and 'Go' cards. */
/* cursorbitmap must still start on 2Kbyte boundary: */ /* cursorbitmap must still start on 2Kbyte boundary: */
NV_REG32(NV32_NV10CUR2ADD32) = (curadd & 0xfffff800); ENG_RG32(RG32_NV10CUR2ADD32) = (curadd & 0xfffff800);
} }
/* set cursor colour: not needed because of direct nature of cursor bitmap. */ /* set cursor colour: not needed because of direct nature of cursor bitmap. */
@@ -661,7 +661,7 @@ status_t eng_crtc2_cursor_init()
} }
/* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */
NV_REG32(NV32_2CURCONF) = 0x02000100; ENG_RG32(RG32_2CURCONF) = 0x02000100;
/* activate hardware cursor */ /* activate hardware cursor */
eng_crtc2_cursor_show(); eng_crtc2_cursor_show();
@@ -769,7 +769,7 @@ status_t eng_crtc2_cursor_position(uint16 x, uint16 y)
{ {
/* we have vertical lines below old and new cursorposition to spare. So we /* we have vertical lines below old and new cursorposition to spare. So we
* update the cursor postion 'mid-screen', but below that area. */ * update the cursor postion 'mid-screen', but below that area. */
while (((uint16)(NV_REG32(NV32_RASTER2) & 0x000007ff)) < (yhigh + 16)) while (((uint16)(ENG_RG32(RG32_RASTER2) & 0x000007ff)) < (yhigh + 16))
{ {
snooze(10); snooze(10);
} }
@@ -777,7 +777,7 @@ status_t eng_crtc2_cursor_position(uint16 x, uint16 y)
else else
{ {
/* no room to spare, just wait for retrace (is relatively slow) */ /* no room to spare, just wait for retrace (is relatively slow) */
while ((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) while ((ENG_RG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display)
{ {
/* don't snooze much longer or retrace might get missed! */ /* don't snooze much longer or retrace might get missed! */
snooze(10); snooze(10);
src/add-ons/accelerants/skeleton/engine/dac.c
+11 -11
View File
@@ -84,8 +84,8 @@ status_t eng_dac_mode(int mode,float brightness)
if (eng_dac_palette(r,g,b) != B_OK) return B_ERROR; if (eng_dac_palette(r,g,b) != B_OK) return B_ERROR;
/* disable palette RAM adressing mask */ /* disable palette RAM adressing mask */
NV_REG8(NV8_PALMASK) = 0xff; ENG_REG8(RG8_PALMASK) = 0xff;
LOG(2,("DAC: PAL pixrdmsk readback $%02x\n", NV_REG8(NV8_PALMASK))); LOG(2,("DAC: PAL pixrdmsk readback $%02x\n", ENG_REG8(RG8_PALMASK)));
return B_OK; return B_OK;
} }
@@ -98,17 +98,17 @@ status_t eng_dac_palette(uint8 r[256],uint8 g[256],uint8 b[256])
LOG(4,("DAC: setting palette\n")); LOG(4,("DAC: setting palette\n"));
/* select first PAL adress before starting programming */ /* select first PAL adress before starting programming */
NV_REG8(NV8_PALINDW) = 0x00; ENG_REG8(RG8_PALINDW) = 0x00;
/* loop through all 256 to program DAC */ /* loop through all 256 to program DAC */
for (i = 0; i < 256; i++) for (i = 0; i < 256; i++)
{ {
/* the 6 implemented bits are on b0-b5 of the bus */ /* the 6 implemented bits are on b0-b5 of the bus */
NV_REG8(NV8_PALDATA) = r[i]; ENG_REG8(RG8_PALDATA) = r[i];
NV_REG8(NV8_PALDATA) = g[i]; ENG_REG8(RG8_PALDATA) = g[i];
NV_REG8(NV8_PALDATA) = b[i]; ENG_REG8(RG8_PALDATA) = b[i];
} }
if (NV_REG8(NV8_PALINDW) != 0x00) if (ENG_REG8(RG8_PALINDW) != 0x00)
{ {
LOG(8,("DAC: PAL write index incorrect after programming\n")); LOG(8,("DAC: PAL write index incorrect after programming\n"));
return B_ERROR; return B_ERROR;
@@ -118,12 +118,12 @@ if (1)
uint8 R, G, B; uint8 R, G, B;
/* select first PAL adress to read (modulo 3 counter) */ /* select first PAL adress to read (modulo 3 counter) */
NV_REG8(NV8_PALINDR) = 0x00; ENG_REG8(RG8_PALINDR) = 0x00;
for (i = 0; i < 256; i++) for (i = 0; i < 256; i++)
{ {
R = NV_REG8(NV8_PALDATA); R = ENG_REG8(RG8_PALDATA);
G = NV_REG8(NV8_PALDATA); G = ENG_REG8(RG8_PALDATA);
B = NV_REG8(NV8_PALDATA); B = ENG_REG8(RG8_PALDATA);
if ((r[i] != R) || (g[i] != G) || (b[i] != B)) if ((r[i] != R) || (g[i] != G) || (b[i] != B))
LOG(1,("DAC palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed LOG(1,("DAC palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed
} }
src/add-ons/accelerants/skeleton/engine/dac2.c
+11 -11
View File
@@ -92,8 +92,8 @@ status_t eng_dac2_mode(int mode,float brightness)
if (eng_dac2_palette(r,g,b) != B_OK) return B_ERROR; if (eng_dac2_palette(r,g,b) != B_OK) return B_ERROR;
/* disable palette RAM adressing mask */ /* disable palette RAM adressing mask */
NV_REG8(NV8_PAL2MASK) = 0xff; ENG_REG8(RG8_PAL2MASK) = 0xff;
LOG(2,("DAC2: PAL pixrdmsk readback $%02x\n", NV_REG8(NV8_PAL2MASK))); LOG(2,("DAC2: PAL pixrdmsk readback $%02x\n", ENG_REG8(RG8_PAL2MASK)));
return B_OK; return B_OK;
} }
@@ -106,17 +106,17 @@ status_t eng_dac2_palette(uint8 r[256],uint8 g[256],uint8 b[256])
LOG(4,("DAC2: setting palette\n")); LOG(4,("DAC2: setting palette\n"));
/* select first PAL adress before starting programming */ /* select first PAL adress before starting programming */
NV_REG8(NV8_PAL2INDW) = 0x00; ENG_REG8(RG8_PAL2INDW) = 0x00;
/* loop through all 256 to program DAC */ /* loop through all 256 to program DAC */
for (i = 0; i < 256; i++) for (i = 0; i < 256; i++)
{ {
/* the 6 implemented bits are on b0-b5 of the bus */ /* the 6 implemented bits are on b0-b5 of the bus */
NV_REG8(NV8_PAL2DATA) = r[i]; ENG_REG8(RG8_PAL2DATA) = r[i];
NV_REG8(NV8_PAL2DATA) = g[i]; ENG_REG8(RG8_PAL2DATA) = g[i];
NV_REG8(NV8_PAL2DATA) = b[i]; ENG_REG8(RG8_PAL2DATA) = b[i];
} }
if (NV_REG8(NV8_PAL2INDW) != 0x00) if (ENG_REG8(RG8_PAL2INDW) != 0x00)
{ {
LOG(8,("DAC2: PAL write index incorrect after programming\n")); LOG(8,("DAC2: PAL write index incorrect after programming\n"));
return B_ERROR; return B_ERROR;
@@ -126,12 +126,12 @@ if (1)
uint8 R, G, B; uint8 R, G, B;
/* select first PAL adress to read (modulo 3 counter) */ /* select first PAL adress to read (modulo 3 counter) */
NV_REG8(NV8_PAL2INDR) = 0x00; ENG_REG8(RG8_PAL2INDR) = 0x00;
for (i = 0; i < 256; i++) for (i = 0; i < 256; i++)
{ {
R = NV_REG8(NV8_PAL2DATA); R = ENG_REG8(RG8_PAL2DATA);
G = NV_REG8(NV8_PAL2DATA); G = ENG_REG8(RG8_PAL2DATA);
B = NV_REG8(NV8_PAL2DATA); B = ENG_REG8(RG8_PAL2DATA);
if ((r[i] != R) || (g[i] != G) || (b[i] != B)) if ((r[i] != R) || (g[i] != G) || (b[i] != B))
LOG(1,("DAC2 palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed LOG(1,("DAC2 palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed
} }
src/add-ons/accelerants/skeleton/engine/general.c
+7 -7
View File
@@ -17,7 +17,7 @@ static void eng_dump_configuration_space (void)
#define DUMP_CFG(reg, type) if (si->ps.card_type >= type) do { \ #define DUMP_CFG(reg, type) if (si->ps.card_type >= type) do { \
uint32 value = CFGR(reg); \ uint32 value = CFGR(reg); \
MSG(("configuration_space 0x%02x %20s 0x%08x\n", \ MSG(("configuration_space 0x%02x %20s 0x%08x\n", \
NVCFG_##reg, #reg, value)); \ ENCFG_##reg, #reg, value)); \
} while (0) } while (0)
DUMP_CFG (DEVID, 0); DUMP_CFG (DEVID, 0);
DUMP_CFG (DEVCTRL, 0); DUMP_CFG (DEVCTRL, 0);
@@ -406,7 +406,7 @@ status_t eng_general_head_select(bool cross)
static status_t eng_general_bios_to_powergraphics() static status_t eng_general_bios_to_powergraphics()
{ {
/* let acc engine make power off/power on cycle to start 'fresh' */ /* let acc engine make power off/power on cycle to start 'fresh' */
NV_REG32(NV32_PWRUPCTRL) = 0x13110011; ENG_RG32(RG32_PWRUPCTRL) = 0x13110011;
snooze(1000); snooze(1000);
/* power-up all hardware function blocks */ /* power-up all hardware function blocks */
@@ -419,10 +419,10 @@ static status_t eng_general_bios_to_powergraphics()
* bit 8: PFIFO, * bit 8: PFIFO,
* bit 4: PMEDIA, * bit 4: PMEDIA,
* bit 0: TVOUT. (> NV04A) */ * bit 0: TVOUT. (> NV04A) */
NV_REG32(NV32_PWRUPCTRL) = 0x13111111; ENG_RG32(RG32_PWRUPCTRL) = 0x13111111;
/* select colormode CRTC registers base adresses */ /* select colormode CRTC registers base adresses */
NV_REG8(NV8_MISCW) = 0xcb; ENG_REG8(RG8_MISCW) = 0xcb;
/* enable access to primary head */ /* enable access to primary head */
set_crtc_owner(0); set_crtc_owner(0);
@@ -456,8 +456,8 @@ static status_t eng_general_bios_to_powergraphics()
* bit 9: TVout chip #2 (confirmed on NV18, NV25, NV28), * bit 9: TVout chip #2 (confirmed on NV18, NV25, NV28),
* bit 8: TVout chip #1 (all cards), * bit 8: TVout chip #1 (all cards),
* bit 4: both I2C busses (all cards) */ * bit 4: both I2C busses (all cards) */
NV_REG32(NV32_2FUNCSEL) &= ~0x00001000; ENG_RG32(RG32_2FUNCSEL) &= ~0x00001000;
NV_REG32(NV32_FUNCSEL) |= 0x00001000; ENG_RG32(RG32_FUNCSEL) |= 0x00001000;
} }
si->overlay.crtc = false; si->overlay.crtc = false;
@@ -497,7 +497,7 @@ static status_t eng_general_bios_to_powergraphics()
/* enable access to secondary head */ /* enable access to secondary head */
set_crtc_owner(1); set_crtc_owner(1);
/* select colormode CRTC2 registers base adresses */ /* select colormode CRTC2 registers base adresses */
NV_REG8(NV8_MISCW) = 0xcb; ENG_REG8(RG8_MISCW) = 0xcb;
/* note: 'BUFFER' is a non-standard register in behaviour(!) on most /* note: 'BUFFER' is a non-standard register in behaviour(!) on most
* NV11's like the GeForce2 MX200, while the MX400 and non-NV11 cards * NV11's like the GeForce2 MX200, while the MX400 and non-NV11 cards
* behave normally. * behave normally.
src/add-ons/accelerants/skeleton/engine/globals.c
+2 -2
View File
@@ -20,7 +20,7 @@ int accelerantIsClone;
eng_get_set_pci eng_pci_access= eng_get_set_pci eng_pci_access=
{ {
NV_PRIVATE_DATA_MAGIC, SKEL_PRIVATE_DATA_MAGIC,
0, 0,
4, 4,
0 0
@@ -28,7 +28,7 @@ eng_get_set_pci eng_pci_access=
eng_in_out_isa eng_isa_access= eng_in_out_isa eng_isa_access=
{ {
NV_PRIVATE_DATA_MAGIC, SKEL_PRIVATE_DATA_MAGIC,
0, 0,
1, 1,
0 0
src/add-ons/accelerants/skeleton/engine/info.c
+112 -112
View File
@@ -238,10 +238,10 @@ static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 in
LOG(8,("INFO: now executing coldstart...\n")); LOG(8,("INFO: now executing coldstart...\n"));
/* select colormode CRTC registers base adresses */ /* select colormode CRTC registers base adresses */
NV_REG8(NV8_MISCW) = 0xcb; ENG_REG8(RG8_MISCW) = 0xcb;
/* unknown.. */ /* unknown.. */
NV_REG8(NV8_VSE2) = 0x01; ENG_REG8(RG8_VSE2) = 0x01;
/* enable access to primary head */ /* enable access to primary head */
set_crtc_owner(0); set_crtc_owner(0);
@@ -311,15 +311,15 @@ static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_ta
//fixme?: works on at least one NV28... how about other cards? //fixme?: works on at least one NV28... how about other cards?
if (si->ps.card_type == NV28) if (si->ps.card_type == NV28)
{ {
fb_mrs2 = NV_REG32(NV32_FB_MRS2); fb_mrs2 = ENG_RG32(RG32_FB_MRS2);
fb_mrs1 = NV_REG32(NV32_FB_MRS1); fb_mrs1 = ENG_RG32(RG32_FB_MRS1);
} }
/* select colormode CRTC registers base adresses */ /* select colormode CRTC registers base adresses */
NV_REG8(NV8_MISCW) = 0xcb; ENG_REG8(RG8_MISCW) = 0xcb;
/* unknown.. */ /* unknown.. */
NV_REG8(NV8_VSE2) = 0x01; ENG_REG8(RG8_VSE2) = 0x01;
/* enable access to primary head */ /* enable access to primary head */
set_crtc_owner(0); set_crtc_owner(0);
@@ -381,8 +381,8 @@ static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_ta
/* get NV28 RAM access up and running */ /* get NV28 RAM access up and running */
//fixme?: works on at least one NV28... how about other cards? //fixme?: works on at least one NV28... how about other cards?
NV_REG32(NV32_FB_MRS2) = fb_mrs2; ENG_RG32(RG32_FB_MRS2) = fb_mrs2;
NV_REG32(NV32_FB_MRS1) = fb_mrs1; ENG_RG32(RG32_FB_MRS1) = fb_mrs1;
} }
/* now enable ROM shadow or the card will remain shut-off! */ /* now enable ROM shadow or the card will remain shut-off! */
@@ -448,7 +448,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
float calced_clk; float calced_clk;
uint8 m, n, p; uint8 m, n, p;
eng_dac_sys_pll_find(((float)data2), &calced_clk, &m, &n, &p, 0); eng_dac_sys_pll_find(((float)data2), &calced_clk, &m, &n, &p, 0);
NV_REG32(reg) = ((p << 16) | (n << 8) | m); ENG_RG32(reg) = ((p << 16) | (n << 8) | m);
} }
log_pll(reg, data2); log_pll(reg, data2);
break; break;
@@ -470,7 +470,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
adress += 2; adress += 2;
data2 = *((uint32*)(&(rom[data]))); data2 = *((uint32*)(&(rom[data])));
LOG(8,("cmd 'WR indirect 32bit reg' $%08x = $%08x\n", reg, data2)); LOG(8,("cmd 'WR indirect 32bit reg' $%08x = $%08x\n", reg, data2));
if (exec) NV_REG32(reg) = data2; if (exec) ENG_RG32(reg) = data2;
break; break;
case 0x63: case 0x63:
*size -= 1; *size -= 1;
@@ -509,8 +509,8 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n", LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n",
reg, data, data2)); reg, data, data2));
/* always done */ /* always done */
NV_REG32(reg) = data; ENG_RG32(reg) = data;
NV_REG32(reg) = data2; ENG_RG32(reg) = data2;
CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe)); CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe));
break; break;
case 0x69: case 0x69:
@@ -536,10 +536,10 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
if (exec) if (exec)
{ {
translate_ISA_PCI(&reg); translate_ISA_PCI(&reg);
byte = NV_REG8(reg); byte = ENG_REG8(reg);
byte &= (uint8)and_out; byte &= (uint8)and_out;
byte |= (uint8)or_in; byte |= (uint8)or_in;
NV_REG8(reg) = byte; ENG_REG8(reg) = byte;
} }
break; break;
case 0x6d: case 0x6d:
@@ -554,7 +554,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
/* execute */ /* execute */
adress += 1; adress += 1;
data = NV_REG32(NV32_NV4STRAPINFO); data = ENG_RG32(RG32_NV4STRAPINFO);
and_out = *((uint8*)(&(rom[adress]))); and_out = *((uint8*)(&(rom[adress])));
adress += 1; adress += 1;
byte = *((uint8*)(&(rom[adress]))); byte = *((uint8*)(&(rom[adress])));
@@ -594,10 +594,10 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
reg, and_out, or_in)); reg, and_out, or_in));
if (exec) if (exec)
{ {
data = NV_REG32(reg); data = ENG_RG32(reg);
data &= and_out; data &= and_out;
data |= or_in; data |= or_in;
NV_REG32(reg) = data; ENG_RG32(reg) = data;
} }
break; break;
case 0x71: case 0x71:
@@ -637,7 +637,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
/* execute */ /* execute */
adress += 1; adress += 1;
data = NV_REG32(NV32_NVSTRAPINFO2); data = ENG_RG32(RG32_NVSTRAPINFO2);
and_out = *((uint32*)(&(rom[adress]))); and_out = *((uint32*)(&(rom[adress])));
adress += 4; adress += 4;
data2 = *((uint32*)(&(rom[adress]))); data2 = *((uint32*)(&(rom[adress])));
@@ -691,7 +691,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
adress += 2; adress += 2;
LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x (b31-16 = '0', b15-0 = data)\n", LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x (b31-16 = '0', b15-0 = data)\n",
reg, data)); reg, data));
if (exec) NV_REG32(reg) = data; if (exec) ENG_RG32(reg) = data;
break; break;
case 0x78: case 0x78:
*size -= 6; *size -= 6;
@@ -718,11 +718,11 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
if (exec) if (exec)
{ {
translate_ISA_PCI(&reg); translate_ISA_PCI(&reg);
NV_REG8(reg) = index; ENG_REG8(reg) = index;
byte = NV_REG8(reg + 1); byte = ENG_REG8(reg + 1);
byte &= (uint8)and_out; byte &= (uint8)and_out;
byte |= (uint8)or_in; byte |= (uint8)or_in;
NV_REG8(reg + 1) = byte; ENG_REG8(reg + 1) = byte;
} }
break; break;
case 0x79: case 0x79:
@@ -747,7 +747,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
float calced_clk; float calced_clk;
uint8 m, n, p; uint8 m, n, p;
eng_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0); eng_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0);
NV_REG32(reg) = ((p << 16) | (n << 8) | m); ENG_RG32(reg) = ((p << 16) | (n << 8) | m);
} }
log_pll(reg, (data / 100)); log_pll(reg, (data / 100));
break; break;
@@ -768,7 +768,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
data = *((uint32*)(&(rom[adress]))); data = *((uint32*)(&(rom[adress])));
adress += 4; adress += 4;
LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data)); LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data));
if (exec) NV_REG32(reg) = data; if (exec) ENG_RG32(reg) = data;
break; break;
default: default:
LOG(8,("unknown cmd, aborting!\n\n")); LOG(8,("unknown cmd, aborting!\n\n"));
@@ -787,33 +787,33 @@ static void log_pll(uint32 reg, uint32 freq)
LOG(8,("INFO: ---WARNING: check/update PLL programming script code!!!\n")); LOG(8,("INFO: ---WARNING: check/update PLL programming script code!!!\n"));
switch (reg) switch (reg)
{ {
case NV32_MEMPLL: case RG32_MEMPLL:
LOG(8,("INFO: ---Memory PLL accessed.\n")); LOG(8,("INFO: ---Memory PLL accessed.\n"));
/* update the card's specs */ /* update the card's specs */
si->ps.std_memory_clock = freq; si->ps.std_memory_clock = freq;
break; break;
case NV32_COREPLL: case RG32_COREPLL:
LOG(8,("INFO: ---Core PLL accessed.\n")); LOG(8,("INFO: ---Core PLL accessed.\n"));
/* update the card's specs */ /* update the card's specs */
si->ps.std_engine_clock = freq; si->ps.std_engine_clock = freq;
break; break;
case NVDAC_PIXPLLC: case ENDAC_PIXPLLC:
LOG(8,("INFO: ---DAC1 PLL accessed.\n")); LOG(8,("INFO: ---DAC1 PLL accessed.\n"));
break; break;
case NVDAC2_PIXPLLC: case ENDAC2_PIXPLLC:
LOG(8,("INFO: ---DAC2 PLL accessed.\n")); LOG(8,("INFO: ---DAC2 PLL accessed.\n"));
break; break;
/* unexpected cases, here for learning goals... */ /* unexpected cases, here for learning goals... */
case NV32_MEMPLL2: case RG32_MEMPLL2:
LOG(8,("INFO: ---NV31/NV36 extension to memory PLL accessed only!\n")); LOG(8,("INFO: ---NV31/NV36 extension to memory PLL accessed only!\n"));
break; break;
case NV32_COREPLL2: case RG32_COREPLL2:
LOG(8,("INFO: ---NV31/NV36 extension to core PLL accessed only!\n")); LOG(8,("INFO: ---NV31/NV36 extension to core PLL accessed only!\n"));
break; break;
case NVDAC_PIXPLLC2: case ENDAC_PIXPLLC2:
LOG(8,("INFO: ---NV31/NV36 extension to DAC1 PLL accessed only!\n")); LOG(8,("INFO: ---NV31/NV36 extension to DAC1 PLL accessed only!\n"));
break; break;
case NVDAC2_PIXPLLC2: case ENDAC2_PIXPLLC2:
LOG(8,("INFO: ---NV31/NV36 extension to DAC2 PLL accessed only!\n")); LOG(8,("INFO: ---NV31/NV36 extension to DAC2 PLL accessed only!\n"));
break; break;
default: default:
@@ -828,9 +828,9 @@ static void setup_ram_config(uint8* rom, uint16 ram_tab)
uint8 cnt; uint8 cnt;
/* set MRS = 256 */ /* set MRS = 256 */
NV_REG32(NV32_PFB_DEBUG_0) &= 0xffffffef; ENG_RG32(RG32_PFB_DEBUG_0) &= 0xffffffef;
/* read RAM config hardware(?) strap */ /* read RAM config hardware(?) strap */
ram_cfg = ((NV_REG32(NV32_NVSTRAPINFO2) >> 2) & 0x0000000f); ram_cfg = ((ENG_RG32(RG32_NVSTRAPINFO2) >> 2) & 0x0000000f);
LOG(8,("INFO: ---RAM config strap is $%01x\n", ram_cfg)); LOG(8,("INFO: ---RAM config strap is $%01x\n", ram_cfg));
/* use it as a pointer in a BIOS table for prerecorded RAM configurations */ /* use it as a pointer in a BIOS table for prerecorded RAM configurations */
ram_cfg = *((uint16*)(&(rom[(ram_tab + (ram_cfg * 2))]))); ram_cfg = *((uint16*)(&(rom[(ram_tab + (ram_cfg * 2))])));
@@ -876,15 +876,15 @@ static void setup_ram_config(uint8* rom, uint16 ram_tab)
break; break;
} }
/* set RAM amount, width and type */ /* set RAM amount, width and type */
data = (NV_REG32(NV32_NV4STRAPINFO) & 0xffffffc0); data = (ENG_RG32(RG32_NV4STRAPINFO) & 0xffffffc0);
NV_REG32(NV32_NV4STRAPINFO) = (data | (ram_cfg & 0x0000003f)); ENG_RG32(RG32_NV4STRAPINFO) = (data | (ram_cfg & 0x0000003f));
/* setup write to read delay (?) */ /* setup write to read delay (?) */
data = (NV_REG32(NV32_PFB_CONFIG_1) & 0xff8ffffe); data = (ENG_RG32(RG32_PFB_CONFIG_1) & 0xff8ffffe);
data |= ((ram_cfg & 0x00000700) << 12); data |= ((ram_cfg & 0x00000700) << 12);
/* force update via b0 = 0... */ /* force update via b0 = 0... */
NV_REG32(NV32_PFB_CONFIG_1) = data; ENG_RG32(RG32_PFB_CONFIG_1) = data;
/* ... followed by b0 = 1(?) */ /* ... followed by b0 = 1(?) */
NV_REG32(NV32_PFB_CONFIG_1) = (data | 0x00000001); ENG_RG32(RG32_PFB_CONFIG_1) = (data | 0x00000001);
/* do RAM width test to confirm RAM width set to be correct */ /* do RAM width test to confirm RAM width set to be correct */
/* write testpattern to first 128 bits of graphics memory... */ /* write testpattern to first 128 bits of graphics memory... */
@@ -896,7 +896,7 @@ static void setup_ram_config(uint8* rom, uint16 ram_tab)
if (((uint32 *)si->framebuffer)[3] != data) if (((uint32 *)si->framebuffer)[3] != data)
{ {
LOG(8,("INFO: ---RAM width tested: width is 64bits, correcting settings.\n")); LOG(8,("INFO: ---RAM width tested: width is 64bits, correcting settings.\n"));
NV_REG32(NV32_NV4STRAPINFO) &= ~0x00000004; ENG_RG32(RG32_NV4STRAPINFO) &= ~0x00000004;
} }
else else
{ {
@@ -963,11 +963,11 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
LOG(8,("INFO: (cont.) then WR result data to 32bit reg $%08x'\n", reg2)); LOG(8,("INFO: (cont.) then WR result data to 32bit reg $%08x'\n", reg2));
if (*exec && reg2) if (*exec && reg2)
{ {
data = NV_REG32(reg); data = ENG_RG32(reg);
data &= and_out; data &= and_out;
data >>= shift; data >>= shift;
data2 = *((uint32*)(&(rom[(*adress + (data << 2))]))); data2 = *((uint32*)(&(rom[(*adress + (data << 2))])));
NV_REG32(reg2) = data2; ENG_RG32(reg2) = data2;
} }
*adress += size32; *adress += size32;
break; break;
@@ -1003,13 +1003,13 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
if (*exec && reg2) if (*exec && reg2)
{ {
translate_ISA_PCI(&reg); translate_ISA_PCI(&reg);
NV_REG8(reg) = index; ENG_REG8(reg) = index;
byte = NV_REG8(reg + 1); byte = ENG_REG8(reg + 1);
byte &= (uint8)and_out; byte &= (uint8)and_out;
byte >>= byte2; byte >>= byte2;
offset32 = (byte << 2); offset32 = (byte << 2);
data = *((uint32*)(&(rom[(*adress + offset32)]))); data = *((uint32*)(&(rom[(*adress + offset32)])));
NV_REG32(reg2) = data; ENG_RG32(reg2) = data;
} }
*adress += size32; *adress += size32;
break; break;
@@ -1075,8 +1075,8 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
LOG(8,("INFO: (cont.) RD table-index ($%02x) for cmd $39'\n", LOG(8,("INFO: (cont.) RD table-index ($%02x) for cmd $39'\n",
offset32)); offset32));
translate_ISA_PCI(&reg); translate_ISA_PCI(&reg);
NV_REG8(reg) = index; ENG_REG8(reg) = index;
byte = NV_REG8(reg + 1); byte = ENG_REG8(reg + 1);
byte &= (uint8)and_out; byte &= (uint8)and_out;
data = (byte >> shift); data = (byte >> shift);
data <<= 1; data <<= 1;
@@ -1102,10 +1102,10 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
uint8 m, n, p; uint8 m, n, p;
eng_dac_sys_pll_find((data2 / 100.0), &calced_clk, &m, &n, &p, 0); eng_dac_sys_pll_find((data2 / 100.0), &calced_clk, &m, &n, &p, 0);
/* programming the PLL needs to be done in steps! (confirmed NV28) */ /* programming the PLL needs to be done in steps! (confirmed NV28) */
data = NV_REG32(reg2); data = ENG_RG32(reg2);
NV_REG32(reg2) = ((data & 0xffff0000) | (n << 8) | m); ENG_RG32(reg2) = ((data & 0xffff0000) | (n << 8) | m);
data = NV_REG32(reg2); data = ENG_RG32(reg2);
NV_REG32(reg2) = ((p << 16) | (n << 8) | m); ENG_RG32(reg2) = ((p << 16) | (n << 8) | m);
//fixme? //fixme?
/* program 2nd set N and M scalers if they exist (b31=1 enables them) */ /* program 2nd set N and M scalers if they exist (b31=1 enables them) */
// if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) // if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36))
@@ -1178,7 +1178,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
index, reg2, and_out2)); index, reg2, and_out2));
if (*exec) if (*exec)
{ {
data = NV_REG32(reg); data = ENG_RG32(reg);
if (byte2 < 0x80) if (byte2 < 0x80)
{ {
data >>= byte2; data >>= byte2;
@@ -1189,11 +1189,11 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
} }
data &= and_out; data &= and_out;
translate_ISA_PCI(&reg2); translate_ISA_PCI(&reg2);
NV_REG8(reg2) = index; ENG_REG8(reg2) = index;
byte = NV_REG8(reg2 + 1); byte = ENG_REG8(reg2 + 1);
byte &= (uint8)and_out2; byte &= (uint8)and_out2;
byte |= (uint8)data; byte |= (uint8)data;
NV_REG8(reg2 + 1) = byte; ENG_REG8(reg2 + 1) = byte;
} }
break; break;
case 0x38: /* new */ case 0x38: /* new */
@@ -1274,12 +1274,12 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
*adress += 1; *adress += 1;
data2 = *((uint8*)(&(rom[*adress]))); data2 = *((uint8*)(&(rom[*adress])));
*adress += 1; *adress += 1;
NV_REG32(reg2) = data2; ENG_RG32(reg2) = data2;
data = NV_REG32(reg); data = ENG_RG32(reg);
data &= and_out; data &= and_out;
data |= or_in; data |= or_in;
data |= or_in2; data |= or_in2;
NV_REG32(reg) = data; ENG_RG32(reg) = data;
} }
} }
else else
@@ -1307,7 +1307,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
if (*exec) if (*exec)
{ {
translate_ISA_PCI(&reg); translate_ISA_PCI(&reg);
NV_REG8(reg) = byte; ENG_REG8(reg) = byte;
} }
break; break;
case 0x62: /* new */ case 0x62: /* new */
@@ -1332,7 +1332,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
if (*exec) if (*exec)
{ {
translate_ISA_PCI(&reg); translate_ISA_PCI(&reg);
NV_REG16(reg) = ((((uint16)byte) << 8) | index); ENG_REG16(reg) = ((((uint16)byte) << 8) | index);
} }
break; break;
case 0x63: /* new setup compared to pre-NV10 version */ case 0x63: /* new setup compared to pre-NV10 version */
@@ -1380,8 +1380,8 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n", LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n",
reg, data, data2)); reg, data, data2));
/* always done */ /* always done */
NV_REG32(reg) = data; ENG_RG32(reg) = data;
NV_REG32(reg) = data2; ENG_RG32(reg) = data2;
CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe)); CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe));
break; break;
case 0x69: /* identical to type1 */ case 0x69: /* identical to type1 */
@@ -1407,10 +1407,10 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
if (*exec) if (*exec)
{ {
translate_ISA_PCI(&reg); translate_ISA_PCI(&reg);
byte = NV_REG8(reg); byte = ENG_REG8(reg);
byte &= (uint8)and_out; byte &= (uint8)and_out;
byte |= (uint8)or_in; byte |= (uint8)or_in;
NV_REG8(reg) = byte; ENG_REG8(reg) = byte;
} }
break; break;
case 0x6a: /* new */ case 0x6a: /* new */
@@ -1479,10 +1479,10 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
reg, and_out, or_in)); reg, and_out, or_in));
if (*exec) if (*exec)
{ {
data = NV_REG32(reg); data = ENG_RG32(reg);
data &= and_out; data &= and_out;
data |= or_in; data |= or_in;
NV_REG32(reg) = data; ENG_RG32(reg) = data;
} }
break; break;
case 0x6f: /* new */ case 0x6f: /* new */
@@ -1522,7 +1522,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
{ {
reg2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3))]))); reg2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3))])));
data2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3) + 4)]))); data2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3) + 4)])));
NV_REG32(reg2) = data2; ENG_RG32(reg2) = data2;
safe32++; safe32++;
} }
} }
@@ -1598,7 +1598,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
reg = *((uint32*)(&(rom[data]))); reg = *((uint32*)(&(rom[data])));
and_out = *((uint32*)(&(rom[(data + 4)]))); and_out = *((uint32*)(&(rom[(data + 4)])));
data2 = *((uint32*)(&(rom[(data + 8)]))); data2 = *((uint32*)(&(rom[(data + 8)])));
data = NV_REG32(reg); data = ENG_RG32(reg);
data &= and_out; data &= and_out;
LOG(8,("cmd 'CHK bits AND-out $%08x reg $%08x for $%08x'\n", LOG(8,("cmd 'CHK bits AND-out $%08x reg $%08x for $%08x'\n",
and_out, reg, data2)); and_out, reg, data2));
@@ -1633,8 +1633,8 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
LOG(8,("cmd 'CHK bits AND-out $%02x idx ISA reg $%02x via $%04x for $%02x'\n", LOG(8,("cmd 'CHK bits AND-out $%02x idx ISA reg $%02x via $%04x for $%02x'\n",
and_out, index, reg, byte2)); and_out, index, reg, byte2));
translate_ISA_PCI(&reg); translate_ISA_PCI(&reg);
NV_REG8(reg) = index; ENG_REG8(reg) = index;
byte = NV_REG8(reg + 1); byte = ENG_REG8(reg + 1);
byte &= (uint8)and_out; byte &= (uint8)and_out;
if (byte != byte2) if (byte != byte2)
{ {
@@ -1671,11 +1671,11 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
if (*exec) if (*exec)
{ {
translate_ISA_PCI(&reg); translate_ISA_PCI(&reg);
NV_REG8(reg) = index; ENG_REG8(reg) = index;
byte = NV_REG8(reg + 1); byte = ENG_REG8(reg + 1);
byte &= (uint8)and_out; byte &= (uint8)and_out;
byte |= (uint8)or_in; byte |= (uint8)or_in;
NV_REG8(reg + 1) = byte; ENG_REG8(reg + 1) = byte;
} }
break; break;
case 0x79: case 0x79:
@@ -1701,10 +1701,10 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
uint8 m, n, p; uint8 m, n, p;
eng_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0); eng_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0);
/* programming the PLL needs to be done in steps! (confirmed NV28) */ /* programming the PLL needs to be done in steps! (confirmed NV28) */
data2 = NV_REG32(reg); data2 = ENG_RG32(reg);
NV_REG32(reg) = ((data2 & 0xffff0000) | (n << 8) | m); ENG_RG32(reg) = ((data2 & 0xffff0000) | (n << 8) | m);
data2 = NV_REG32(reg); data2 = ENG_RG32(reg);
NV_REG32(reg) = ((p << 16) | (n << 8) | m); ENG_RG32(reg) = ((p << 16) | (n << 8) | m);
//fixme? //fixme?
/* program 2nd set N and M scalers if they exist (b31=1 enables them) */ /* program 2nd set N and M scalers if they exist (b31=1 enables them) */
// if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) // if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36))
@@ -1729,7 +1729,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
data = *((uint32*)(&(rom[*adress]))); data = *((uint32*)(&(rom[*adress])));
*adress += 4; *adress += 4;
LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data)); LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data));
if (*exec) NV_REG32(reg) = data; if (*exec) ENG_RG32(reg) = data;
break; break;
default: default:
LOG(8,("unknown cmd, aborting!\n\n")); LOG(8,("unknown cmd, aborting!\n\n"));
@@ -1759,8 +1759,8 @@ static void exec_cmd_39_type2(uint8* rom, uint32 data, PinsTables tabs, bool* ex
LOG(8,("cmd 'AND-out bits $%02x idx ISA reg $%02x via $%04x, shift-right = $%02x,\n", LOG(8,("cmd 'AND-out bits $%02x idx ISA reg $%02x via $%04x, shift-right = $%02x,\n",
and_out, index, reg, shift)); and_out, index, reg, shift));
translate_ISA_PCI(&reg); translate_ISA_PCI(&reg);
NV_REG8(reg) = index; ENG_REG8(reg) = index;
byte = NV_REG8(reg + 1); byte = ENG_REG8(reg + 1);
byte &= (uint8)and_out; byte &= (uint8)and_out;
offset32 += (byte >> shift); offset32 += (byte >> shift);
safe = byte = *((uint8*)(&(rom[offset32]))); safe = byte = *((uint8*)(&(rom[offset32])));
@@ -1787,7 +1787,7 @@ static void setup_ram_config_nv10_up(uint8* rom)
status_t stat = B_ERROR; status_t stat = B_ERROR;
/* set 'refctrl is valid' */ /* set 'refctrl is valid' */
NV_REG32(NV32_PFB_REFCTRL) = 0x80000000; ENG_RG32(RG32_PFB_REFCTRL) = 0x80000000;
/* check RAM for 256bits buswidth(?) */ /* check RAM for 256bits buswidth(?) */
while ((cnt < 4) && (stat != B_OK)) while ((cnt < 4) && (stat != B_OK))
@@ -1810,7 +1810,7 @@ static void setup_ram_config_nv10_up(uint8* rom)
if (stat != B_OK) if (stat != B_OK)
{ {
LOG(8,("INFO: ---RAM test #1 done: access errors, modified setup.\n")); LOG(8,("INFO: ---RAM test #1 done: access errors, modified setup.\n"));
data = NV_REG32(NV32_PFB_CONFIG_0); data = ENG_RG32(RG32_PFB_CONFIG_0);
if (data & 0x00000010) if (data & 0x00000010)
{ {
data &= 0xffffffcf; data &= 0xffffffcf;
@@ -1820,7 +1820,7 @@ static void setup_ram_config_nv10_up(uint8* rom)
data &= 0xffffffcf; data &= 0xffffffcf;
data |= 0x00000020; data |= 0x00000020;
} }
NV_REG32(NV32_PFB_CONFIG_0) = data; ENG_RG32(RG32_PFB_CONFIG_0) = data;
} }
else else
{ {
@@ -1833,7 +1833,7 @@ static void setup_ram_config_nv10_up(uint8* rom)
while ((cnt < 4) && (stat != B_OK)) while ((cnt < 4) && (stat != B_OK))
{ {
/* read RAM size */ /* read RAM size */
data = NV_REG32(NV32_NV10STRAPINFO); data = ENG_RG32(RG32_NV10STRAPINFO);
/* subtract 1MB */ /* subtract 1MB */
data -= 0x00100000; data -= 0x00100000;
/* write testpattern at generated RAM adress */ /* write testpattern at generated RAM adress */
@@ -1854,7 +1854,7 @@ static void setup_ram_config_nv10_up(uint8* rom)
if (stat != B_OK) if (stat != B_OK)
{ {
LOG(8,("INFO: ---RAM test #2 done: access errors, modified setup.\n")); LOG(8,("INFO: ---RAM test #2 done: access errors, modified setup.\n"));
NV_REG32(NV32_PFB_CONFIG_0) &= 0xffffefff; ENG_RG32(RG32_PFB_CONFIG_0) &= 0xffffefff;
} }
else else
{ {
@@ -1871,13 +1871,13 @@ static void setup_ram_config_nv28(uint8* rom)
status_t stat = B_ERROR; status_t stat = B_ERROR;
/* set 'refctrl is valid' */ /* set 'refctrl is valid' */
NV_REG32(NV32_PFB_REFCTRL) = 0x80000000; ENG_RG32(RG32_PFB_REFCTRL) = 0x80000000;
/* check RAM */ /* check RAM */
while ((cnt < 4) && (stat != B_OK)) while ((cnt < 4) && (stat != B_OK))
{ {
/* set bit 11: 'pulse' something into a new setting? */ /* set bit 11: 'pulse' something into a new setting? */
NV_REG32(NV32_PFB_CONFIG_0) |= 0x00000800; ENG_RG32(RG32_PFB_CONFIG_0) |= 0x00000800;
/* write testpattern to RAM adress 127Mb */ /* write testpattern to RAM adress 127Mb */
((uint32 *)si->framebuffer)[0x01fc0000] = 0x4e564441; ((uint32 *)si->framebuffer)[0x01fc0000] = 0x4e564441;
/* reset first RAM adress */ /* reset first RAM adress */
@@ -1897,7 +1897,7 @@ static void setup_ram_config_nv28(uint8* rom)
} }
/* clear bit 11: set normal mode */ /* clear bit 11: set normal mode */
NV_REG32(NV32_PFB_CONFIG_0) &= ~0x00000800; ENG_RG32(RG32_PFB_CONFIG_0) &= ~0x00000800;
if (stat == B_OK) if (stat == B_OK)
LOG(8,("INFO: ---RAM test done: access was OK within %d iteration(s).\n", cnt)); LOG(8,("INFO: ---RAM test done: access was OK within %d iteration(s).\n", cnt));
@@ -1910,49 +1910,49 @@ static status_t translate_ISA_PCI(uint32* reg)
switch (*reg) switch (*reg)
{ {
case 0x03c0: case 0x03c0:
*reg = NV8_ATTRDATW; *reg = RG8_ATTRDATW;
break; break;
case 0x03c1: case 0x03c1:
*reg = NV8_ATTRDATR; *reg = RG8_ATTRDATR;
break; break;
case 0x03c2: case 0x03c2:
*reg = NV8_MISCW; *reg = RG8_MISCW;
break; break;
case 0x03c4: case 0x03c4:
*reg = NV8_SEQIND; *reg = RG8_SEQIND;
break; break;
case 0x03c5: case 0x03c5:
*reg = NV8_SEQDAT; *reg = RG8_SEQDAT;
break; break;
case 0x03c6: case 0x03c6:
*reg = NV8_PALMASK; *reg = RG8_PALMASK;
break; break;
case 0x03c7: case 0x03c7:
*reg = NV8_PALINDR; *reg = RG8_PALINDR;
break; break;
case 0x03c8: case 0x03c8:
*reg = NV8_PALINDW; *reg = RG8_PALINDW;
break; break;
case 0x03c9: case 0x03c9:
*reg = NV8_PALDATA; *reg = RG8_PALDATA;
break; break;
case 0x03cc: case 0x03cc:
*reg = NV8_MISCR; *reg = RG8_MISCR;
break; break;
case 0x03ce: case 0x03ce:
*reg = NV8_GRPHIND; *reg = RG8_GRPHIND;
break; break;
case 0x03cf: case 0x03cf:
*reg = NV8_GRPHDAT; *reg = RG8_GRPHDAT;
break; break;
case 0x03d4: case 0x03d4:
*reg = NV8_CRTCIND; *reg = RG8_CRTCIND;
break; break;
case 0x03d5: case 0x03d5:
*reg = NV8_CRTCDAT; *reg = RG8_CRTCDAT;
break; break;
case 0x03da: case 0x03da:
*reg = NV8_INSTAT1; *reg = RG8_INSTAT1;
break; break;
default: default:
LOG(8,("\n\nINFO: WARNING: ISA->PCI register adress translation failed!\n\n")); LOG(8,("\n\nINFO: WARNING: ISA->PCI register adress translation failed!\n\n"));
@@ -2334,7 +2334,7 @@ static void detect_panels()
/* dump some panel configuration registers... */ /* dump some panel configuration registers... */
LOG(2,("INFO: Dumping flatpanel registers:\n")); LOG(2,("INFO: Dumping flatpanel registers:\n"));
LOG(2,("DUALHEAD_CTRL: $%08x\n", NV_REG32(NV32_DUALHEAD_CTRL))); LOG(2,("DUALHEAD_CTRL: $%08x\n", ENG_RG32(RG32_DUALHEAD_CTRL)));
LOG(2,("DAC1: FP_HDISPEND: %d\n", DACR(FP_HDISPEND))); LOG(2,("DAC1: FP_HDISPEND: %d\n", DACR(FP_HDISPEND)));
LOG(2,("DAC1: FP_HTOTAL: %d\n", DACR(FP_HTOTAL))); LOG(2,("DAC1: FP_HTOTAL: %d\n", DACR(FP_HTOTAL)));
LOG(2,("DAC1: FP_HCRTC: %d\n", DACR(FP_HCRTC))); LOG(2,("DAC1: FP_HCRTC: %d\n", DACR(FP_HCRTC)));
@@ -2359,8 +2359,8 @@ static void detect_panels()
LOG(2,("DAC1: FP_DEBUG2: $%08x\n", DACR(FP_DEBUG2))); LOG(2,("DAC1: FP_DEBUG2: $%08x\n", DACR(FP_DEBUG2)));
LOG(2,("DAC1: FP_DEBUG3: $%08x\n", DACR(FP_DEBUG3))); LOG(2,("DAC1: FP_DEBUG3: $%08x\n", DACR(FP_DEBUG3)));
LOG(2,("DAC1: FUNCSEL: $%08x\n", NV_REG32(NV32_FUNCSEL))); LOG(2,("DAC1: FUNCSEL: $%08x\n", ENG_RG32(RG32_FUNCSEL)));
LOG(2,("DAC1: PANEL_PWR: $%08x\n", NV_REG32(NV32_PANEL_PWR))); LOG(2,("DAC1: PANEL_PWR: $%08x\n", ENG_RG32(RG32_PANEL_PWR)));
if(si->ps.secondary_head) if(si->ps.secondary_head)
{ {
@@ -2388,8 +2388,8 @@ static void detect_panels()
LOG(2,("DAC2: FP_DEBUG2: $%08x\n", DAC2R(FP_DEBUG2))); LOG(2,("DAC2: FP_DEBUG2: $%08x\n", DAC2R(FP_DEBUG2)));
LOG(2,("DAC2: FP_DEBUG3: $%08x\n", DAC2R(FP_DEBUG3))); LOG(2,("DAC2: FP_DEBUG3: $%08x\n", DAC2R(FP_DEBUG3)));
LOG(2,("DAC2: FUNCSEL: $%08x\n", NV_REG32(NV32_2FUNCSEL))); LOG(2,("DAC2: FUNCSEL: $%08x\n", ENG_RG32(RG32_2FUNCSEL)));
LOG(2,("DAC2: PANEL_PWR: $%08x\n", NV_REG32(NV32_2PANEL_PWR))); LOG(2,("DAC2: PANEL_PWR: $%08x\n", ENG_RG32(RG32_2PANEL_PWR)));
} }
LOG(2,("INFO: End flatpanel registers dump.\n")); LOG(2,("INFO: End flatpanel registers dump.\n"));
} }
@@ -2850,7 +2850,7 @@ static void pinsnv30_arch_fake(void)
static void getRAMsize_arch_nv4(void) static void getRAMsize_arch_nv4(void)
{ {
uint32 strapinfo = NV_REG32(NV32_NV4STRAPINFO); uint32 strapinfo = ENG_RG32(RG32_NV4STRAPINFO);
if (strapinfo & 0x00000100) if (strapinfo & 0x00000100)
{ {
@@ -2883,7 +2883,7 @@ static void getRAMsize_arch_nv4(void)
static void getstrap_arch_nv4(void) static void getstrap_arch_nv4(void)
{ {
uint32 strapinfo = NV_REG32(NV32_NVSTRAPINFO2); uint32 strapinfo = ENG_RG32(RG32_NVSTRAPINFO2);
/* determine PLL reference crystal frequency */ /* determine PLL reference crystal frequency */
if (strapinfo & 0x00000040) if (strapinfo & 0x00000040)
@@ -2898,7 +2898,7 @@ static void getstrap_arch_nv4(void)
static void getRAMsize_arch_nv10_20_30_40(void) static void getRAMsize_arch_nv10_20_30_40(void)
{ {
uint32 dev_manID = CFGR(DEVID); uint32 dev_manID = CFGR(DEVID);
uint32 strapinfo = NV_REG32(NV32_NV10STRAPINFO); uint32 strapinfo = ENG_RG32(RG32_NV10STRAPINFO);
switch (dev_manID) switch (dev_manID)
{ {
@@ -2950,7 +2950,7 @@ static void getRAMsize_arch_nv10_20_30_40(void)
static void getstrap_arch_nv10_20_30_40(void) static void getstrap_arch_nv10_20_30_40(void)
{ {
uint32 dev_manID = CFGR(DEVID); uint32 dev_manID = CFGR(DEVID);
uint32 strapinfo = NV_REG32(NV32_NVSTRAPINFO2); uint32 strapinfo = ENG_RG32(RG32_NVSTRAPINFO2);
/* determine PLL reference crystal frequency: three types are used... */ /* determine PLL reference crystal frequency: three types are used... */
if (strapinfo & 0x00000040) if (strapinfo & 0x00000040)
src/add-ons/accelerants/skeleton/engine/tvout.c
+3 -3
View File
@@ -681,7 +681,7 @@ int maventv_init(display_mode target)
// if (si->ps.card_type <= G400MAX) MAVW(PGM, 0x01); // if (si->ps.card_type <= G400MAX) MAVW(PGM, 0x01);
// else // else
// { // {
// DXIW(TVO_IDX, NVMAV_PGM); // DXIW(TVO_IDX, ENMAV_PGM);
// DXIW(TVO_DATA, 0x01); // DXIW(TVO_DATA, 0x01);
// } // }
@@ -917,7 +917,7 @@ int maventv_init(display_mode target)
// MAVW(GAMMA9, 0xC8); /* 200 */ // MAVW(GAMMA9, 0xC8); /* 200 */
/* set flickerfilter */ /* set flickerfilter */
/* OFF: is dependant on MAVEN chip version(?): NV_TVO_B = $40, else $00. /* OFF: is dependant on MAVEN chip version(?): ENG_TVO_B = $40, else $00.
* ON : always set $a2. */ * ON : always set $a2. */
// MAVW(FFILTER, 0xa2); // MAVW(FFILTER, 0xa2);
@@ -1197,7 +1197,7 @@ int maventv_init(display_mode target)
// if (si->ps.card_type <= G400MAX) MAVW(PGM, 0x00); // if (si->ps.card_type <= G400MAX) MAVW(PGM, 0x00);
// else // else
// { // {
// DXIW(TVO_IDX, NVMAV_PGM); // DXIW(TVO_IDX, ENMAV_PGM);
// DXIW(TVO_DATA, 0x00); // DXIW(TVO_DATA, 0x00);
/* Select 2.0 Volt MAVEN DAC ref. so we have enough contrast/brightness range */ /* Select 2.0 Volt MAVEN DAC ref. so we have enough contrast/brightness range */
src/add-ons/kernel/drivers/graphics/skeleton/driver.c
+27 -27
View File
@@ -143,33 +143,33 @@ static void dumprom (void *rom, uint32 size)
/* return 1 if vblank interrupt has occured */ /* return 1 if vblank interrupt has occured */
static int caused_vbi(vuint32 * regs) static int caused_vbi(vuint32 * regs)
{ {
return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); return (ENG_RG32(RG32_CRTC_INTS) & 0x00000001);
} }
/* clear the vblank interrupt */ /* clear the vblank interrupt */
static void clear_vbi(vuint32 * regs) static void clear_vbi(vuint32 * regs)
{ {
NV_REG32(NV32_CRTC_INTS) = 0x00000001; ENG_RG32(RG32_CRTC_INTS) = 0x00000001;
} }
static void enable_vbi(vuint32 * regs) static void enable_vbi(vuint32 * regs)
{ {
/* clear the vblank interrupt */ /* clear the vblank interrupt */
NV_REG32(NV32_CRTC_INTS) = 0x00000001; ENG_RG32(RG32_CRTC_INTS) = 0x00000001;
/* enable nVidia interrupt source vblank */ /* enable nVidia interrupt source vblank */
NV_REG32(NV32_CRTC_INTE) |= 0x00000001; ENG_RG32(RG32_CRTC_INTE) |= 0x00000001;
/* enable nVidia interrupt system hardware (b0-1) */ /* enable nVidia interrupt system hardware (b0-1) */
NV_REG32(NV32_MAIN_INTE) = 0x00000001; ENG_RG32(RG32_MAIN_INTE) = 0x00000001;
} }
static void disable_vbi(vuint32 * regs) static void disable_vbi(vuint32 * regs)
{ {
/* disable nVidia interrupt source vblank */ /* disable nVidia interrupt source vblank */
NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; ENG_RG32(RG32_CRTC_INTE) &= 0xfffffffe;
/* clear the vblank interrupt */ /* clear the vblank interrupt */
NV_REG32(NV32_CRTC_INTS) = 0x00000001; ENG_RG32(RG32_CRTC_INTS) = 0x00000001;
/* disable nVidia interrupt system hardware (b0-1) */ /* disable nVidia interrupt system hardware (b0-1) */
NV_REG32(NV32_MAIN_INTE) = 0x00000000; ENG_RG32(RG32_MAIN_INTE) = 0x00000000;
} }
/* /*
@@ -394,7 +394,7 @@ static status_t map_device(device_info *di)
* NV18, NV28 and NV34 keep working. * NV18, NV28 and NV34 keep working.
* confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes,
* however the actual ROM content (so the used part) is intact (confirmed). */ * however the actual ROM content (so the used part) is intact (confirmed). */
//set_pci(NVCFG_ROMSHADOW, 4, 0); //set_pci(ENCFG_ROMSHADOW, 4, 0);
/* get ROM memory mapped base adress - this is defined in the PCI standard */ /* get ROM memory mapped base adress - this is defined in the PCI standard */
tmpUlong = get_pci(PCI_rom_base, 4); tmpUlong = get_pci(PCI_rom_base, 4);
@@ -851,39 +851,39 @@ control_hook (void* dev, uint32 msg, void *buf, size_t len) {
} break; } break;
/* PRIVATE ioctl from here on */ /* PRIVATE ioctl from here on */
case NV_GET_PRIVATE_DATA: { case ENG_GET_PRIVATE_DATA: {
eng_get_private_data *gpd = (eng_get_private_data *)buf; eng_get_private_data *gpd = (eng_get_private_data *)buf;
if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { if (gpd->magic == SKEL_PRIVATE_DATA_MAGIC) {
gpd->shared_info_area = di->shared_area; gpd->shared_info_area = di->shared_area;
result = B_OK; result = B_OK;
} }
} break; } break;
case NV_GET_PCI: { case ENG_GET_PCI: {
eng_get_set_pci *gsp = (eng_get_set_pci *)buf; eng_get_set_pci *gsp = (eng_get_set_pci *)buf;
if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { if (gsp->magic == SKEL_PRIVATE_DATA_MAGIC) {
pci_info *pcii = &(di->pcii); pci_info *pcii = &(di->pcii);
gsp->value = get_pci(gsp->offset, gsp->size); gsp->value = get_pci(gsp->offset, gsp->size);
result = B_OK; result = B_OK;
} }
} break; } break;
case NV_SET_PCI: { case ENG_SET_PCI: {
eng_get_set_pci *gsp = (eng_get_set_pci *)buf; eng_get_set_pci *gsp = (eng_get_set_pci *)buf;
if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { if (gsp->magic == SKEL_PRIVATE_DATA_MAGIC) {
pci_info *pcii = &(di->pcii); pci_info *pcii = &(di->pcii);
set_pci(gsp->offset, gsp->size, gsp->value); set_pci(gsp->offset, gsp->size, gsp->value);
result = B_OK; result = B_OK;
} }
} break; } break;
case NV_DEVICE_NAME: { // apsed case ENG_DEVICE_NAME: { // apsed
eng_device_name *dn = (eng_device_name *)buf; eng_device_name *dn = (eng_device_name *)buf;
if (dn->magic == NV_PRIVATE_DATA_MAGIC) { if (dn->magic == SKEL_PRIVATE_DATA_MAGIC) {
strcpy(dn->name, di->name); strcpy(dn->name, di->name);
result = B_OK; result = B_OK;
} }
} break; } break;
case NV_RUN_INTERRUPTS: { case ENG_RUN_INTERRUPTS: {
eng_set_bool_state *ri = (eng_set_bool_state *)buf; eng_set_bool_state *ri = (eng_set_bool_state *)buf;
if (ri->magic == NV_PRIVATE_DATA_MAGIC) { if (ri->magic == SKEL_PRIVATE_DATA_MAGIC) {
vuint32 *regs = di->regs; vuint32 *regs = di->regs;
if (ri->do_it) { if (ri->do_it) {
enable_vbi(regs); enable_vbi(regs);
@@ -893,9 +893,9 @@ control_hook (void* dev, uint32 msg, void *buf, size_t len) {
result = B_OK; result = B_OK;
} }
} break; } break;
case NV_GET_NTH_AGP_INFO: { case ENG_GET_NTH_AGP_INFO: {
eng_nth_agp_info *nai = (eng_nth_agp_info *)buf; eng_nth_agp_info *nai = (eng_nth_agp_info *)buf;
if (nai->magic == NV_PRIVATE_DATA_MAGIC) { if (nai->magic == SKEL_PRIVATE_DATA_MAGIC) {
nai->exist = false; nai->exist = false;
nai->agp_bus = false; nai->agp_bus = false;
if (agp_bus) { if (agp_bus) {
@@ -907,9 +907,9 @@ control_hook (void* dev, uint32 msg, void *buf, size_t len) {
result = B_OK; result = B_OK;
} }
} break; } break;
case NV_ENABLE_AGP: { case ENG_ENABLE_AGP: {
eng_cmd_agp *nca = (eng_cmd_agp *)buf; eng_cmd_agp *nca = (eng_cmd_agp *)buf;
if (nca->magic == NV_PRIVATE_DATA_MAGIC) { if (nca->magic == SKEL_PRIVATE_DATA_MAGIC) {
if (agp_bus) { if (agp_bus) {
nca->agp_bus = true; nca->agp_bus = true;
(*agp_bus->enable_agp)(&(nca->cmd)); (*agp_bus->enable_agp)(&(nca->cmd));
@@ -920,9 +920,9 @@ control_hook (void* dev, uint32 msg, void *buf, size_t len) {
result = B_OK; result = B_OK;
} }
} break; } break;
case NV_ISA_OUT: { case ENG_ISA_OUT: {
eng_in_out_isa *io_isa = (eng_in_out_isa *)buf; eng_in_out_isa *io_isa = (eng_in_out_isa *)buf;
if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { if (io_isa->magic == SKEL_PRIVATE_DATA_MAGIC) {
pci_info *pcii = &(di->pcii); pci_info *pcii = &(di->pcii);
/* lock the driver: /* lock the driver:
@@ -949,9 +949,9 @@ control_hook (void* dev, uint32 msg, void *buf, size_t len) {
RELEASE_BEN(pd->kernel); RELEASE_BEN(pd->kernel);
} }
} break; } break;
case NV_ISA_IN: { case ENG_ISA_IN: {
eng_in_out_isa *io_isa = (eng_in_out_isa *)buf; eng_in_out_isa *io_isa = (eng_in_out_isa *)buf;
if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { if (io_isa->magic == SKEL_PRIVATE_DATA_MAGIC) {
pci_info *pcii = &(di->pcii); pci_info *pcii = &(di->pcii);
/* lock the driver: /* lock the driver: