* Adding driver for Atheros AR8131/AR8132 Gigabit/Fast Ethernet network cards.

The source is based on the FreeBSD RELEASE_8_0_0 code, found in Haiku's freebsd vendor branch. This driver enables the network card in my EeePC 1005HA-M, for example. To compile it issue "jam atheros813x". * Introducing the new build target. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@34348 a95241bf-73f2-0310-859d-f6bbb57e9c96
2009-11-29 13:35:30 +00:00
parent e6a7fa65fe
commit c322cc3d7c
11 changed files with 5135 additions and 0 deletions
@@ -31,4 +31,7 @@ SubInclude HAIKU_TOP src add-ons kernel drivers network rtl81xx ;
 SubIncludeGPL HAIKU_TOP src add-ons kernel drivers network bcm440x ;
 SubIncludeGPL HAIKU_TOP src add-ons kernel drivers network bcm570x ;

+# FreeBSD 8 drivers
+SubInclude HAIKU_TOP src add-ons kernel drivers network atheros813x ;
+
 SubInclude HAIKU_TOP src add-ons kernel drivers network wlan ;
@@ -0,0 +1,3 @@
+SubDir HAIKU_TOP src add-ons kernel drivers network atheros813x ;
+
+SubInclude HAIKU_TOP src add-ons kernel drivers network atheros813x dev ;
@@ -0,0 +1,4 @@
+SubDir HAIKU_TOP src add-ons kernel drivers network atheros813x dev ;
+
+SubInclude HAIKU_TOP src add-ons kernel drivers network atheros813x dev mii ;
+SubInclude HAIKU_TOP src add-ons kernel drivers network atheros813x dev alc ;
@@ -0,0 +1,19 @@
+SubDir HAIKU_TOP src add-ons kernel drivers network atheros813x dev alc ;
+
+SubDirCcFlags -Wall ;
+
+UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
+
+UsePrivateHeaders net system ;
+UsePrivateKernelHeaders ;
+
+UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ;
+
+SubDirCcFlags [ FDefines _KERNEL=1 ] ;
+
+KernelAddon atheros813x :
+	if_alc.c
+	glue.c
+	: libfreebsd_network.a atheros813x_mii.a
+	;
+
@@ -0,0 +1,8 @@
+#include <sys/bus.h>
+
+HAIKU_FBSD_DRIVER_GLUE(atheros813x, alc, pci);
+
+HAIKU_FBSD_MII_DRIVER(ukphy);
+HAIKU_DRIVER_REQUIREMENTS(FBSD_TASKQUEUES | FBSD_FAST_TASKQUEUE);
+NO_HAIKU_CHECK_DISABLE_INTERRUPTS();
+NO_HAIKU_REENABLE_INTERRUPTS();
@@ -0,0 +1,947 @@
+/*-
+ * Copyright (c) 2009, Pyun YongHyeon <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMATES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMATE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	_IF_ALCREG_H
+#define	_IF_ALCREG_H
+
+/*
+ * Atheros Communucations, Inc. PCI vendor ID
+ */
+#define	VENDORID_ATHEROS		0x1969
+
+/*
+ * Atheros AR8131/AR8132 device ID
+ */
+#define	DEVICEID_ATHEROS_AR8131		0x1063	/* L1C */
+#define	DEVICEID_ATHEROS_AR8132		0x1062	/* L2C */
+
+/* 0x0000 - 0x02FF : PCIe configuration space */
+
+#define	ALC_PEX_UNC_ERR_SEV		0x10C
+#define	PEX_UNC_ERR_SEV_TRN		0x00000001
+#define	PEX_UNC_ERR_SEV_DLP		0x00000010
+#define	PEX_UNC_ERR_SEV_PSN_TLP		0x00001000
+#define	PEX_UNC_ERR_SEV_FCP		0x00002000
+#define	PEX_UNC_ERR_SEV_CPL_TO		0x00004000
+#define	PEX_UNC_ERR_SEV_CA		0x00008000
+#define	PEX_UNC_ERR_SEV_UC		0x00010000
+#define	PEX_UNC_ERR_SEV_ROV		0x00020000
+#define	PEX_UNC_ERR_SEV_MLFP		0x00040000
+#define	PEX_UNC_ERR_SEV_ECRC		0x00080000
+#define	PEX_UNC_ERR_SEV_UR		0x00100000
+
+#define	ALC_TWSI_CFG			0x218
+#define	TWSI_CFG_SW_LD_START		0x00000800
+#define	TWSI_CFG_HW_LD_START		0x00001000
+#define	TWSI_CFG_LD_EXIST		0x00400000
+
+#define	ALC_PCIE_PHYMISC		0x1000
+#define	PCIE_PHYMISC_FORCE_RCV_DET	0x00000004
+
+#define	ALC_TWSI_DEBUG			0x1108
+#define	TWSI_DEBUG_DEV_EXIST		0x20000000
+
+#define	ALC_EEPROM_CFG			0x12C0
+#define	EEPROM_CFG_DATA_HI_MASK		0x0000FFFF
+#define	EEPROM_CFG_ADDR_MASK		0x03FF0000
+#define	EEPROM_CFG_ACK			0x40000000
+#define	EEPROM_CFG_RW			0x80000000
+#define	EEPROM_CFG_DATA_HI_SHIFT	0
+#define	EEPROM_CFG_ADDR_SHIFT		16
+
+#define	ALC_EEPROM_DATA_LO		0x12C4
+
+#define	ALC_OPT_CFG			0x12F0
+#define	OPT_CFG_CLK_ENB			0x00000002
+
+#define	ALC_PM_CFG			0x12F8
+#define	PM_CFG_SERDES_ENB		0x00000001
+#define	PM_CFG_RBER_ENB			0x00000002
+#define	PM_CFG_CLK_REQ_ENB		0x00000004
+#define	PM_CFG_ASPM_L1_ENB		0x00000008
+#define	PM_CFG_SERDES_L1_ENB		0x00000010
+#define	PM_CFG_SERDES_PLL_L1_ENB	0x00000020
+#define	PM_CFG_SERDES_PD_EX_L1		0x00000040
+#define	PM_CFG_SERDES_BUDS_RX_L1_ENB	0x00000080
+#define	PM_CFG_L0S_ENTRY_TIMER_MASK	0x00000F00
+#define	PM_CFG_ASPM_L0S_ENB		0x00001000
+#define	PM_CFG_CLK_SWH_L1		0x00002000
+#define	PM_CFG_CLK_PWM_VER1_1		0x00004000
+#define	PM_CFG_PCIE_RECV		0x00008000
+#define	PM_CFG_L1_ENTRY_TIMER_MASK	0x000F0000
+#define	PM_CFG_PM_REQ_TIMER_MASK	0x00F00000
+#define	PM_CFG_LCKDET_TIMER_MASK	0x3F000000
+#define	PM_CFG_MAC_ASPM_CHK		0x40000000
+#define	PM_CFG_HOTRST			0x80000000
+#define	PM_CFG_L0S_ENTRY_TIMER_SHIFT	8
+#define	PM_CFG_L1_ENTRY_TIMER_SHIFT	16
+#define	PM_CFG_PM_REQ_TIMER_SHIFT	20
+#define	PM_CFG_LCKDET_TIMER_SHIFT	24
+
+#define	ALC_MASTER_CFG			0x1400
+#define	MASTER_RESET			0x00000001
+#define	MASTER_BERT_START		0x00000010
+#define	MASTER_TEST_MODE_MASK		0x000000C0
+#define	MASTER_MTIMER_ENB		0x00000100
+#define	MASTER_MANUAL_INTR_ENB		0x00000200
+#define	MASTER_IM_TX_TIMER_ENB		0x00000400
+#define	MASTER_IM_RX_TIMER_ENB		0x00000800
+#define	MASTER_CLK_SEL_DIS		0x00001000
+#define	MASTER_CLK_SWH_MODE		0x00002000
+#define	MASTER_INTR_RD_CLR		0x00004000
+#define	MASTER_CHIP_REV_MASK		0x00FF0000
+#define	MASTER_CHIP_ID_MASK		0x7F000000
+#define	MASTER_OTP_SEL			0x80000000
+#define	MASTER_TEST_MODE_SHIFT		2
+#define	MASTER_CHIP_REV_SHIFT		16
+#define	MASTER_CHIP_ID_SHIFT		24
+
+/* Number of ticks per usec for AR8131/AR8132. */
+#define	ALC_TICK_USECS			2
+#define	ALC_USECS(x)			((x) / ALC_TICK_USECS)
+
+#define	ALC_MANUAL_TIMER		0x1404
+
+#define	ALC_IM_TIMER			0x1408
+#define	IM_TIMER_TX_MASK		0x0000FFFF
+#define	IM_TIMER_RX_MASK		0xFFFF0000
+#define	IM_TIMER_TX_SHIFT		0
+#define	IM_TIMER_RX_SHIFT		16
+#define	ALC_IM_TIMER_MIN		0
+#define	ALC_IM_TIMER_MAX		130000	/* 130ms */
+/*
+ * 100us will ensure alc(4) wouldn't generate more than 10000 Rx
+ * interrupts in a second.
+ */
+#define	ALC_IM_RX_TIMER_DEFAULT		100	/* 100us */
+/*
+ * alc(4) does not rely on Tx completion interrupts, so set it
+ * somewhat large value to reduce Tx completion interrupts.
+ */
+#define	ALC_IM_TX_TIMER_DEFAULT		50000	/* 50ms */
+
+#define	ALC_GPHY_CFG			0x140C	/* 16bits */
+#define	GPHY_CFG_EXT_RESET		0x0001
+#define	GPHY_CFG_RTL_MODE		0x0002
+#define	GPHY_CFG_LED_MODE		0x0004
+#define	GPHY_CFG_ANEG_NOW		0x0008
+#define	GPHY_CFG_RECV_ANEG		0x0010
+#define	GPHY_CFG_GATE_25M_ENB		0x0020
+#define	GPHY_CFG_LPW_EXIT		0x0040
+#define	GPHY_CFG_PHY_IDDQ		0x0080
+#define	GPHY_CFG_PHY_IDDQ_DIS		0x0100
+#define	GPHY_CFG_PCLK_SEL_DIS		0x0200
+#define	GPHY_CFG_HIB_EN			0x0400
+#define	GPHY_CFG_HIB_PULSE		0x0800
+#define	GPHY_CFG_SEL_ANA_RESET		0x1000
+#define	GPHY_CFG_PHY_PLL_ON		0x2000
+#define	GPHY_CFG_PWDOWN_HW		0x4000
+#define	GPHY_CFG_PHY_PLL_BYPASS		0x8000
+
+#define	ALC_IDLE_STATUS			0x1410
+#define	IDLE_STATUS_RXMAC		0x00000001
+#define	IDLE_STATUS_TXMAC		0x00000002
+#define	IDLE_STATUS_RXQ			0x00000004
+#define	IDLE_STATUS_TXQ			0x00000008
+#define	IDLE_STATUS_DMARD		0x00000010
+#define	IDLE_STATUS_DMAWR		0x00000020
+#define	IDLE_STATUS_SMB			0x00000040
+#define	IDLE_STATUS_CMB			0x00000080
+
+#define	ALC_MDIO			0x1414
+#define	MDIO_DATA_MASK			0x0000FFFF
+#define	MDIO_REG_ADDR_MASK		0x001F0000
+#define	MDIO_OP_READ			0x00200000
+#define	MDIO_OP_WRITE			0x00000000
+#define	MDIO_SUP_PREAMBLE		0x00400000
+#define	MDIO_OP_EXECUTE			0x00800000
+#define	MDIO_CLK_25_4			0x00000000
+#define	MDIO_CLK_25_6			0x02000000
+#define	MDIO_CLK_25_8			0x03000000
+#define	MDIO_CLK_25_10			0x04000000
+#define	MDIO_CLK_25_14			0x05000000
+#define	MDIO_CLK_25_20			0x06000000
+#define	MDIO_CLK_25_28			0x07000000
+#define	MDIO_OP_BUSY			0x08000000
+#define	MDIO_AP_ENB			0x10000000
+#define	MDIO_DATA_SHIFT			0
+#define	MDIO_REG_ADDR_SHIFT		16
+
+#define	MDIO_REG_ADDR(x)	\
+	(((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK)
+/* Default PHY address. */
+#define	ALC_PHY_ADDR			0
+
+#define	ALC_PHY_STATUS			0x1418
+#define	PHY_STATUS_RECV_ENB		0x00000001
+#define	PHY_STATUS_GENERAL_MASK		0x0000FFFF
+#define	PHY_STATUS_OE_PWSP_MASK		0x07FF0000
+#define	PHY_STATUS_LPW_STATE		0x80000000
+#define	PHY_STATIS_OE_PWSP_SHIFT	16
+
+/* Packet memory BIST. */
+#define	ALC_BIST0			0x141C
+#define	BIST0_ENB			0x00000001
+#define	BIST0_SRAM_FAIL			0x00000002
+#define	BIST0_FUSE_FLAG			0x00000004
+
+/* PCIe retry buffer BIST. */
+#define	ALC_BIST1			0x1420
+#define	BIST1_ENB			0x00000001
+#define	BIST1_SRAM_FAIL			0x00000002
+#define	BIST1_FUSE_FLAG			0x00000004
+
+#define	ALC_SERDES_LOCK			0x1424
+#define	SERDES_LOCK_DET			0x00000001
+#define	SERDES_LOCK_DET_ENB		0x00000002
+
+#define	ALC_MAC_CFG			0x1480
+#define	MAC_CFG_TX_ENB			0x00000001
+#define	MAC_CFG_RX_ENB			0x00000002
+#define	MAC_CFG_TX_FC			0x00000004
+#define	MAC_CFG_RX_FC			0x00000008
+#define	MAC_CFG_LOOP			0x00000010
+#define	MAC_CFG_FULL_DUPLEX		0x00000020
+#define	MAC_CFG_TX_CRC_ENB		0x00000040
+#define	MAC_CFG_TX_AUTO_PAD		0x00000080
+#define	MAC_CFG_TX_LENCHK		0x00000100
+#define	MAC_CFG_RX_JUMBO_ENB		0x00000200
+#define	MAC_CFG_PREAMBLE_MASK		0x00003C00
+#define	MAC_CFG_VLAN_TAG_STRIP		0x00004000
+#define	MAC_CFG_PROMISC			0x00008000
+#define	MAC_CFG_TX_PAUSE		0x00010000
+#define	MAC_CFG_SCNT			0x00020000
+#define	MAC_CFG_SYNC_RST_TX		0x00040000
+#define	MAC_CFG_SIM_RST_TX		0x00080000
+#define	MAC_CFG_SPEED_MASK		0x00300000
+#define	MAC_CFG_SPEED_10_100		0x00100000
+#define	MAC_CFG_SPEED_1000		0x00200000
+#define	MAC_CFG_DBG_TX_BACKOFF		0x00400000
+#define	MAC_CFG_TX_JUMBO_ENB		0x00800000
+#define	MAC_CFG_RXCSUM_ENB		0x01000000
+#define	MAC_CFG_ALLMULTI		0x02000000
+#define	MAC_CFG_BCAST			0x04000000
+#define	MAC_CFG_DBG			0x08000000
+#define	MAC_CFG_SINGLE_PAUSE_ENB	0x10000000
+#define	MAC_CFG_PREAMBLE_SHIFT		10
+#define	MAC_CFG_PREAMBLE_DEFAULT	7
+
+#define	ALC_IPG_IFG_CFG			0x1484
+#define	IPG_IFG_IPGT_MASK		0x0000007F
+#define	IPG_IFG_MIFG_MASK		0x0000FF00
+#define	IPG_IFG_IPG1_MASK		0x007F0000
+#define	IPG_IFG_IPG2_MASK		0x7F000000
+#define	IPG_IFG_IPGT_SHIFT		0
+#define	IPG_IFG_IPGT_DEFAULT		0x60
+#define	IPG_IFG_MIFG_SHIFT		8
+#define	IPG_IFG_MIFG_DEFAULT		0x50
+#define	IPG_IFG_IPG1_SHIFT		16
+#define	IPG_IFG_IPG1_DEFAULT		0x40
+#define	IPG_IFG_IPG2_SHIFT		24
+#define	IPG_IFG_IPG2_DEFAULT		0x60
+
+/* Station address. */
+#define	ALC_PAR0			0x1488
+#define	ALC_PAR1			0x148C
+
+/* 64bit multicast hash register. */
+#define	ALC_MAR0			0x1490
+#define	ALC_MAR1			0x1494
+
+/* half-duplex parameter configuration. */
+#define	ALC_HDPX_CFG			0x1498
+#define	HDPX_CFG_LCOL_MASK		0x000003FF
+#define	HDPX_CFG_RETRY_MASK		0x0000F000
+#define	HDPX_CFG_EXC_DEF_EN		0x00010000
+#define	HDPX_CFG_NO_BACK_C		0x00020000
+#define	HDPX_CFG_NO_BACK_P		0x00040000
+#define	HDPX_CFG_ABEBE			0x00080000
+#define	HDPX_CFG_ABEBT_MASK		0x00F00000
+#define	HDPX_CFG_JAMIPG_MASK		0x0F000000
+#define	HDPX_CFG_LCOL_SHIFT		0
+#define	HDPX_CFG_LCOL_DEFAULT		0x37
+#define	HDPX_CFG_RETRY_SHIFT		12
+#define	HDPX_CFG_RETRY_DEFAULT		0x0F
+#define	HDPX_CFG_ABEBT_SHIFT		20
+#define	HDPX_CFG_ABEBT_DEFAULT		0x0A
+#define	HDPX_CFG_JAMIPG_SHIFT		24
+#define	HDPX_CFG_JAMIPG_DEFAULT		0x07
+
+#define	ALC_FRAME_SIZE			0x149C
+
+#define	ALC_WOL_CFG			0x14A0
+#define	WOL_CFG_PATTERN			0x00000001
+#define	WOL_CFG_PATTERN_ENB		0x00000002
+#define	WOL_CFG_MAGIC			0x00000004
+#define	WOL_CFG_MAGIC_ENB		0x00000008
+#define	WOL_CFG_LINK_CHG		0x00000010
+#define	WOL_CFG_LINK_CHG_ENB		0x00000020
+#define	WOL_CFG_PATTERN_DET		0x00000100
+#define	WOL_CFG_MAGIC_DET		0x00000200
+#define	WOL_CFG_LINK_CHG_DET		0x00000400
+#define	WOL_CFG_CLK_SWITCH_ENB		0x00008000
+#define	WOL_CFG_PATTERN0		0x00010000
+#define	WOL_CFG_PATTERN1		0x00020000
+#define	WOL_CFG_PATTERN2		0x00040000
+#define	WOL_CFG_PATTERN3		0x00080000
+#define	WOL_CFG_PATTERN4		0x00100000
+#define	WOL_CFG_PATTERN5		0x00200000
+#define	WOL_CFG_PATTERN6		0x00400000
+
+/* WOL pattern length. */
+#define	ALC_PATTERN_CFG0		0x14A4
+#define	PATTERN_CFG_0_LEN_MASK		0x0000007F
+#define	PATTERN_CFG_1_LEN_MASK		0x00007F00
+#define	PATTERN_CFG_2_LEN_MASK		0x007F0000
+#define	PATTERN_CFG_3_LEN_MASK		0x7F000000
+
+#define	ALC_PATTERN_CFG1		0x14A8
+#define	PATTERN_CFG_4_LEN_MASK		0x0000007F
+#define	PATTERN_CFG_5_LEN_MASK		0x00007F00
+#define	PATTERN_CFG_6_LEN_MASK		0x007F0000
+
+/* RSS */
+#define	ALC_RSS_KEY0			0x14B0
+
+#define	ALC_RSS_KEY1			0x14B4
+
+#define	ALC_RSS_KEY2			0x14B8
+
+#define	ALC_RSS_KEY3			0x14BC
+
+#define	ALC_RSS_KEY4			0x14C0
+
+#define	ALC_RSS_KEY5			0x14C4
+
+#define	ALC_RSS_KEY6			0x14C8
+
+#define	ALC_RSS_KEY7			0x14CC
+
+#define	ALC_RSS_KEY8			0x14D0
+
+#define	ALC_RSS_KEY9			0x14D4
+
+#define	ALC_RSS_IDT_TABLE0		0x14E0
+
+#define	ALC_RSS_IDT_TABLE1		0x14E4
+
+#define	ALC_RSS_IDT_TABLE2		0x14E8
+
+#define	ALC_RSS_IDT_TABLE3		0x14EC
+
+#define	ALC_RSS_IDT_TABLE4		0x14F0
+
+#define	ALC_RSS_IDT_TABLE5		0x14F4
+
+#define	ALC_RSS_IDT_TABLE6		0x14F8
+
+#define	ALC_RSS_IDT_TABLE7		0x14FC
+
+#define	ALC_SRAM_RD0_ADDR		0x1500
+
+#define	ALC_SRAM_RD1_ADDR		0x1504
+
+#define	ALC_SRAM_RD2_ADDR		0x1508
+
+#define	ALC_SRAM_RD3_ADDR		0x150C
+
+#define	RD_HEAD_ADDR_MASK		0x000003FF
+#define	RD_TAIL_ADDR_MASK		0x03FF0000
+#define	RD_HEAD_ADDR_SHIFT		0
+#define	RD_TAIL_ADDR_SHIFT		16
+
+#define	ALC_RD_NIC_LEN0			0x1510	/* 8 bytes unit */
+#define	RD_NIC_LEN_MASK			0x000003FF
+
+#define	ALC_RD_NIC_LEN1			0x1514
+
+#define	ALC_SRAM_TD_ADDR		0x1518
+#define	TD_HEAD_ADDR_MASK		0x000003FF
+#define	TD_TAIL_ADDR_MASK		0x03FF0000
+#define	TD_HEAD_ADDR_SHIFT		0
+#define	TD_TAIL_ADDR_SHIFT		16
+
+#define	ALC_SRAM_TD_LEN			0x151C	/* 8 bytes unit */
+#define	SRAM_TD_LEN_MASK		0x000003FF
+
+#define	ALC_SRAM_RX_FIFO_ADDR		0x1520
+
+#define	ALC_SRAM_RX_FIFO_LEN		0x1524
+
+#define	ALC_SRAM_TX_FIFO_ADDR		0x1528
+
+#define	ALC_SRAM_TX_FIFO_LEN		0x152C
+
+#define	ALC_SRAM_TCPH_ADDR		0x1530
+#define	SRAM_TCPH_ADDR_MASK		0x00000FFF
+#define	SRAM_PATH_ADDR_MASK		0x0FFF0000
+#define	SRAM_TCPH_ADDR_SHIFT		0
+#define	SRAM_PKTH_ADDR_SHIFT		16
+
+#define	ALC_DMA_BLOCK			0x1534
+#define	DMA_BLOCK_LOAD			0x00000001
+
+#define	ALC_RX_BASE_ADDR_HI		0x1540
+
+#define	ALC_TX_BASE_ADDR_HI		0x1544
+
+#define	ALC_SMB_BASE_ADDR_HI		0x1548
+
+#define	ALC_SMB_BASE_ADDR_LO		0x154C
+
+#define	ALC_RD0_HEAD_ADDR_LO		0x1550
+
+#define	ALC_RD1_HEAD_ADDR_LO		0x1554
+
+#define	ALC_RD2_HEAD_ADDR_LO		0x1558
+
+#define	ALC_RD3_HEAD_ADDR_LO		0x155C
+
+#define	ALC_RD_RING_CNT			0x1560
+#define	RD_RING_CNT_MASK		0x00000FFF
+#define	RD_RING_CNT_SHIFT		0
+
+#define	ALC_RX_BUF_SIZE			0x1564
+#define	RX_BUF_SIZE_MASK		0x0000FFFF
+/*
+ * If larger buffer size than 1536 is specified the controller
+ * will be locked up. This is hardware limitation.
+ */
+#define	RX_BUF_SIZE_MAX			1536
+
+#define	ALC_RRD0_HEAD_ADDR_LO		0x1568
+
+#define	ALC_RRD1_HEAD_ADDR_LO		0x156C
+
+#define	ALC_RRD2_HEAD_ADDR_LO		0x1570
+
+#define	ALC_RRD3_HEAD_ADDR_LO		0x1574
+
+#define	ALC_RRD_RING_CNT		0x1578
+#define	RRD_RING_CNT_MASK		0x00000FFF
+#define	RRD_RING_CNT_SHIFT		0
+
+#define	ALC_TDH_HEAD_ADDR_LO		0x157C
+
+#define	ALC_TDL_HEAD_ADDR_LO		0x1580
+
+#define	ALC_TD_RING_CNT			0x1584
+#define	TD_RING_CNT_MASK		0x0000FFFF
+#define	TD_RING_CNT_SHIFT		0
+
+#define	ALC_CMB_BASE_ADDR_LO		0x1588
+
+#define	ALC_TXQ_CFG			0x1590
+#define	TXQ_CFG_TD_BURST_MASK		0x0000000F
+#define	TXQ_CFG_IP_OPTION_ENB		0x00000010
+#define	TXQ_CFG_ENB			0x00000020
+#define	TXQ_CFG_ENHANCED_MODE		0x00000040
+#define	TXQ_CFG_8023_ENB		0x00000080
+#define	TXQ_CFG_TX_FIFO_BURST_MASK	0xFFFF0000
+#define	TXQ_CFG_TD_BURST_SHIFT		0
+#define	TXQ_CFG_TD_BURST_DEFAULT	5
+#define	TXQ_CFG_TX_FIFO_BURST_SHIFT	16
+
+#define	ALC_TSO_OFFLOAD_THRESH		0x1594	/* 8 bytes unit */
+#define	TSO_OFFLOAD_THRESH_MASK		0x000007FF
+#define	TSO_OFFLOAD_THRESH_SHIFT	0
+#define	TSO_OFFLOAD_THRESH_UNIT		8
+#define	TSO_OFFLOAD_THRESH_UNIT_SHIFT	3
+
+#define	ALC_TXF_WATER_MARK		0x1598	/* 8 bytes unit */
+#define	TXF_WATER_MARK_HI_MASK		0x00000FFF
+#define	TXF_WATER_MARK_LO_MASK		0x0FFF0000
+#define	TXF_WATER_MARK_BURST_ENB	0x80000000
+#define	TXF_WATER_MARK_LO_SHIFT		0
+#define	TXF_WATER_MARK_HI_SHIFT		16
+
+#define	ALC_THROUGHPUT_MON		0x159C
+#define	THROUGHPUT_MON_RATE_MASK	0x00000003
+#define	THROUGHPUT_MON_ENB		0x00000080
+#define	THROUGHPUT_MON_RATE_SHIFT	0
+
+#define	ALC_RXQ_CFG			0x15A0
+#define	RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK	0x00000003
+#define	RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE	0x00000000
+#define	RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M	0x00000001
+#define	RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M	0x00000002
+#define	RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M	0x00000003
+#define	RXQ_CFG_QUEUE1_ENB		0x00000010
+#define	RXQ_CFG_QUEUE2_ENB		0x00000020
+#define	RXQ_CFG_QUEUE3_ENB		0x00000040
+#define	RXQ_CFG_IPV6_CSUM_ENB		0x00000080
+#define	RXQ_CFG_RSS_HASH_TBL_LEN_MASK	0x0000FF00
+#define	RXQ_CFG_RSS_HASH_IPV4		0x00010000
+#define	RXQ_CFG_RSS_HASH_IPV4_TCP	0x00020000
+#define	RXQ_CFG_RSS_HASH_IPV6		0x00040000
+#define	RXQ_CFG_RSS_HASH_IPV6_TCP	0x00080000
+#define	RXQ_CFG_RD_BURST_MASK		0x03F00000
+#define	RXQ_CFG_RSS_MODE_DIS		0x00000000
+#define	RXQ_CFG_RSS_MODE_SQSINT		0x04000000
+#define	RXQ_CFG_RSS_MODE_MQUESINT	0x08000000
+#define	RXQ_CFG_RSS_MODE_MQUEMINT	0x0C000000
+#define	RXQ_CFG_NIP_QUEUE_SEL_TBL	0x10000000
+#define	RXQ_CFG_RSS_HASH_ENB		0x20000000
+#define	RXQ_CFG_CUT_THROUGH_ENB		0x40000000
+#define	RXQ_CFG_QUEUE0_ENB		0x80000000
+#define	RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT	8
+#define	RXQ_CFG_RD_BURST_DEFAULT	8
+#define	RXQ_CFG_RD_BURST_SHIFT		20
+#define	RXQ_CFG_ENB					\
+	(RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB |	\
+	 RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB)
+
+#define	ALC_RX_RD_FREE_THRESH		0x15A4	/* 8 bytes unit. */
+#define	RX_RD_FREE_THRESH_HI_MASK	0x0000003F
+#define	RX_RD_FREE_THRESH_LO_MASK	0x00000FC0
+#define	RX_RD_FREE_THRESH_HI_SHIFT	0
+#define	RX_RD_FREE_THRESH_LO_SHIFT	6
+#define	RX_RD_FREE_THRESH_HI_DEFAULT	16
+#define	RX_RD_FREE_THRESH_LO_DEFAULT	8
+
+#define	ALC_RX_FIFO_PAUSE_THRESH	0x15A8
+#define	RX_FIFO_PAUSE_THRESH_LO_MASK	0x00000FFF
+#define	RX_FIFO_PAUSE_THRESH_HI_MASK	0x0FFF0000
+#define	RX_FIFO_PAUSE_THRESH_LO_SHIFT	0
+#define	RX_FIFO_PAUSE_THRESH_HI_SHIFT	16
+
+#define	ALC_RD_DMA_CFG			0x15AC
+#define	RD_DMA_CFG_THRESH_MASK		0x00000FFF	/* 8 bytes unit */
+#define	RD_DMA_CFG_TIMER_MASK		0xFFFF0000
+#define	RD_DMA_CFG_THRESH_SHIFT		0
+#define	RD_DMA_CFG_TIMER_SHIFT		16
+#define	RD_DMA_CFG_THRESH_DEFAULT	0x100
+#define	RD_DMA_CFG_TIMER_DEFAULT	0
+#define	RD_DMA_CFG_TICK_USECS		8
+#define	ALC_RD_DMA_CFG_USECS(x)		((x) / RD_DMA_CFG_TICK_USECS)
+
+#define	ALC_RSS_HASH_VALUE		0x15B0
+
+#define	ALC_RSS_HASH_FLAG		0x15B4
+
+#define	ALC_RSS_CPU			0x15B8
+
+#define	ALC_DMA_CFG			0x15C0
+#define	DMA_CFG_IN_ORDER		0x00000001
+#define	DMA_CFG_ENH_ORDER		0x00000002
+#define	DMA_CFG_OUT_ORDER		0x00000004
+#define	DMA_CFG_RCB_64			0x00000000
+#define	DMA_CFG_RCB_128			0x00000008
+#define	DMA_CFG_RD_BURST_128		0x00000000
+#define	DMA_CFG_RD_BURST_256		0x00000010
+#define	DMA_CFG_RD_BURST_512		0x00000020
+#define	DMA_CFG_RD_BURST_1024		0x00000030
+#define	DMA_CFG_RD_BURST_2048		0x00000040
+#define	DMA_CFG_RD_BURST_4096		0x00000050
+#define	DMA_CFG_WR_BURST_128		0x00000000
+#define	DMA_CFG_WR_BURST_256		0x00000080
+#define	DMA_CFG_WR_BURST_512		0x00000100
+#define	DMA_CFG_WR_BURST_1024		0x00000180
+#define	DMA_CFG_WR_BURST_2048		0x00000200
+#define	DMA_CFG_WR_BURST_4096		0x00000280
+#define	DMA_CFG_RD_REQ_PRI		0x00000400
+#define	DMA_CFG_RD_DELAY_CNT_MASK	0x0000F800
+#define	DMA_CFG_WR_DELAY_CNT_MASK	0x000F0000
+#define	DMA_CFG_CMB_ENB			0x00100000
+#define	DMA_CFG_SMB_ENB			0x00200000
+#define	DMA_CFG_CMB_NOW			0x00400000
+#define	DMA_CFG_SMB_DIS			0x01000000
+#define	DMA_CFG_SMB_NOW			0x80000000
+#define	DMA_CFG_RD_BURST_MASK		0x07
+#define	DMA_CFG_RD_BURST_SHIFT		4
+#define	DMA_CFG_WR_BURST_MASK		0x07
+#define	DMA_CFG_WR_BURST_SHIFT		7
+#define	DMA_CFG_RD_DELAY_CNT_SHIFT	11
+#define	DMA_CFG_WR_DELAY_CNT_SHIFT	16
+#define	DMA_CFG_RD_DELAY_CNT_DEFAULT	15
+#define	DMA_CFG_WR_DELAY_CNT_DEFAULT	4
+
+#define	ALC_SMB_STAT_TIMER		0x15C4
+#define	SMB_STAT_TIMER_MASK		0x00FFFFFF
+#define	SMB_STAT_TIMER_SHIFT		0
+
+#define	ALC_CMB_TD_THRESH		0x15C8
+#define	CMB_TD_THRESH_MASK		0x0000FFFF
+#define	CMB_TD_THRESH_SHIFT		0
+
+#define	ALC_CMB_TX_TIMER		0x15CC
+#define	CMB_TX_TIMER_MASK		0x0000FFFF
+#define	CMB_TX_TIMER_SHIFT		0
+
+#define	ALC_MBOX_RD0_PROD_IDX		0x15E0
+
+#define	ALC_MBOX_RD1_PROD_IDX		0x15E4
+
+#define	ALC_MBOX_RD2_PROD_IDX		0x15E8
+
+#define	ALC_MBOX_RD3_PROD_IDX		0x15EC
+
+#define	ALC_MBOX_RD_PROD_MASK		0x0000FFFF
+#define	MBOX_RD_PROD_SHIFT		0
+
+#define	ALC_MBOX_TD_PROD_IDX		0x15F0
+#define	MBOX_TD_PROD_HI_IDX_MASK	0x0000FFFF
+#define	MBOX_TD_PROD_LO_IDX_MASK	0xFFFF0000
+#define	MBOX_TD_PROD_HI_IDX_SHIFT	0
+#define	MBOX_TD_PROD_LO_IDX_SHIFT	16
+
+#define	ALC_MBOX_TD_CONS_IDX		0x15F4
+#define	MBOX_TD_CONS_HI_IDX_MASK	0x0000FFFF
+#define	MBOX_TD_CONS_LO_IDX_MASK	0xFFFF0000
+#define	MBOX_TD_CONS_HI_IDX_SHIFT	0
+#define	MBOX_TD_CONS_LO_IDX_SHIFT	16
+
+#define	ALC_MBOX_RD01_CONS_IDX		0x15F8
+#define	MBOX_RD0_CONS_IDX_MASK		0x0000FFFF
+#define	MBOX_RD1_CONS_IDX_MASK		0xFFFF0000
+#define	MBOX_RD0_CONS_IDX_SHIFT		0
+#define	MBOX_RD1_CONS_IDX_SHIFT		16
+
+#define	ALC_MBOX_RD23_CONS_IDX		0x15FC
+#define	MBOX_RD2_CONS_IDX_MASK		0x0000FFFF
+#define	MBOX_RD3_CONS_IDX_MASK		0xFFFF0000
+#define	MBOX_RD2_CONS_IDX_SHIFT		0
+#define	MBOX_RD3_CONS_IDX_SHIFT		16
+
+#define	ALC_INTR_STATUS			0x1600
+#define	INTR_SMB			0x00000001
+#define	INTR_TIMER			0x00000002
+#define	INTR_MANUAL_TIMER		0x00000004
+#define	INTR_RX_FIFO_OFLOW		0x00000008
+#define	INTR_RD0_UNDERRUN		0x00000010
+#define	INTR_RD1_UNDERRUN		0x00000020
+#define	INTR_RD2_UNDERRUN		0x00000040
+#define	INTR_RD3_UNDERRUN		0x00000080
+#define	INTR_TX_FIFO_UNDERRUN		0x00000100
+#define	INTR_DMA_RD_TO_RST		0x00000200
+#define	INTR_DMA_WR_TO_RST		0x00000400
+#define	INTR_TX_CREDIT			0x00000800
+#define	INTR_GPHY			0x00001000
+#define	INTR_GPHY_LOW_PW		0x00002000
+#define	INTR_TXQ_TO_RST			0x00004000
+#define	INTR_TX_PKT			0x00008000
+#define	INTR_RX_PKT0			0x00010000
+#define	INTR_RX_PKT1			0x00020000
+#define	INTR_RX_PKT2			0x00040000
+#define	INTR_RX_PKT3			0x00080000
+#define	INTR_MAC_RX			0x00100000
+#define	INTR_MAC_TX			0x00200000
+#define	INTR_UNDERRUN			0x00400000
+#define	INTR_FRAME_ERROR		0x00800000
+#define	INTR_FRAME_OK			0x01000000
+#define	INTR_CSUM_ERROR			0x02000000
+#define	INTR_PHY_LINK_DOWN		0x04000000
+#define	INTR_DIS_INT			0x80000000
+
+/* Interrupt Mask Register */
+#define	ALC_INTR_MASK			0x1604
+
+#ifdef	notyet
+#define	INTR_RX_PKT					\
+	(INTR_RX_PKT0 | INTR_RX_PKT1 | INTR_RX_PKT2 |	\
+	 INTR_RX_PKT3)
+#define	INTR_RD_UNDERRUN				\
+	(INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN |	\
+	INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN)
+#else
+#define	INTR_RX_PKT			INTR_RX_PKT0
+#define	INTR_RD_UNDERRUN		INTR_RD0_UNDERRUN
+#endif
+
+#define	ALC_INTRS					\
+	(INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |	\
+	INTR_TXQ_TO_RST	| INTR_RX_PKT | INTR_TX_PKT |	\
+	INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN |		\
+	INTR_TX_FIFO_UNDERRUN)
+
+#define	ALC_INTR_RETRIG_TIMER		0x1608
+#define	INTR_RETRIG_TIMER_MASK		0x0000FFFF
+#define	INTR_RETRIG_TIMER_SHIFT		0
+
+#define	ALC_HDS_CFG			0x160C
+#define	HDS_CFG_ENB			0x00000001
+#define	HDS_CFG_BACKFILLSIZE_MASK	0x000FFF00
+#define	HDS_CFG_MAX_HDRSIZE_MASK	0xFFF00000
+#define	HDS_CFG_BACKFILLSIZE_SHIFT	8
+#define	HDS_CFG_MAX_HDRSIZE_SHIFT	20
+
+/* AR8131/AR8132 registers for MAC statistics */
+#define	ALC_RX_MIB_BASE			0x1700
+
+#define	ALC_TX_MIB_BASE			0x1760
+
+#define	ALC_DEBUG_DATA0			0x1900
+
+#define	ALC_DEBUG_DATA1			0x1904
+
+#define	ALC_MII_DBG_ADDR		0x1D
+#define	ALC_MII_DBG_DATA		0x1E
+
+#define	MII_ANA_CFG0			0x00
+#define	ANA_RESTART_CAL			0x0001
+#define	ANA_MANUL_SWICH_ON_MASK		0x001E
+#define	ANA_MAN_ENABLE			0x0020
+#define	ANA_SEL_HSP			0x0040
+#define	ANA_EN_HB			0x0080
+#define	ANA_EN_HBIAS			0x0100
+#define	ANA_OEN_125M			0x0200
+#define	ANA_EN_LCKDT			0x0400
+#define	ANA_LCKDT_PHY			0x0800
+#define	ANA_AFE_MODE			0x1000
+#define	ANA_VCO_SLOW			0x2000
+#define	ANA_VCO_FAST			0x4000
+#define	ANA_SEL_CLK125M_DSP		0x8000
+#define	ANA_MANUL_SWICH_ON_SHIFT	1
+
+#define	MII_ANA_CFG4			0x04
+#define	ANA_IECHO_ADJ_MASK		0x0F
+#define	ANA_IECHO_ADJ_3_MASK		0x000F
+#define	ANA_IECHO_ADJ_2_MASK		0x00F0
+#define	ANA_IECHO_ADJ_1_MASK		0x0F00
+#define	ANA_IECHO_ADJ_0_MASK		0xF000
+#define	ANA_IECHO_ADJ_3_SHIFT		0
+#define	ANA_IECHO_ADJ_2_SHIFT		4
+#define	ANA_IECHO_ADJ_1_SHIFT		8
+#define	ANA_IECHO_ADJ_0_SHIFT		12
+
+#define	MII_ANA_CFG5			0x05
+#define	ANA_SERDES_CDR_BW_MASK		0x0003
+#define	ANA_MS_PAD_DBG			0x0004
+#define	ANA_SPEEDUP_DBG			0x0008
+#define	ANA_SERDES_TH_LOS_MASK		0x0030
+#define	ANA_SERDES_EN_DEEM		0x0040
+#define	ANA_SERDES_TXELECIDLE		0x0080
+#define	ANA_SERDES_BEACON		0x0100
+#define	ANA_SERDES_HALFTXDR		0x0200
+#define	ANA_SERDES_SEL_HSP		0x0400
+#define	ANA_SERDES_EN_PLL		0x0800
+#define	ANA_SERDES_EN			0x1000
+#define	ANA_SERDES_EN_LCKDT		0x2000
+#define	ANA_SERDES_CDR_BW_SHIFT		0
+#define	ANA_SERDES_TH_LOS_SHIFT		4
+
+#define	MII_ANA_CFG11			0x0B
+#define	ANA_PS_HIB_EN			0x8000
+
+#define	MII_ANA_CFG18			0x12
+#define	ANA_TEST_MODE_10BT_01MASK	0x0003
+#define	ANA_LOOP_SEL_10BT		0x0004
+#define	ANA_RGMII_MODE_SW		0x0008
+#define	ANA_EN_LONGECABLE		0x0010
+#define	ANA_TEST_MODE_10BT_2		0x0020
+#define	ANA_EN_10BT_IDLE		0x0400
+#define	ANA_EN_MASK_TB			0x0800
+#define	ANA_TRIGGER_SEL_TIMER_MASK	0x3000
+#define	ANA_INTERVAL_SEL_TIMER_MASK	0xC000
+#define	ANA_TEST_MODE_10BT_01SHIFT	0
+#define	ANA_TRIGGER_SEL_TIMER_SHIFT	12
+#define	ANA_INTERVAL_SEL_TIMER_SHIFT	14
+
+#define	MII_ANA_CFG41			0x29
+#define	ANA_TOP_PS_EN			0x8000
+
+#define	MII_ANA_CFG54			0x36
+#define	ANA_LONG_CABLE_TH_100_MASK	0x003F
+#define	ANA_DESERVED			0x0040
+#define	ANA_EN_LIT_CH			0x0080
+#define	ANA_SHORT_CABLE_TH_100_MASK	0x3F00
+#define	ANA_BP_BAD_LINK_ACCUM		0x4000
+#define	ANA_BP_SMALL_BW			0x8000
+#define	ANA_LONG_CABLE_TH_100_SHIFT	0
+#define	ANA_SHORT_CABLE_TH_100_SHIFT	8
+
+/* Statistics counters collected by the MAC. */
+struct smb {
+	/* Rx stats. */
+	uint32_t rx_frames;
+	uint32_t rx_bcast_frames;
+	uint32_t rx_mcast_frames;
+	uint32_t rx_pause_frames;
+	uint32_t rx_control_frames;
+	uint32_t rx_crcerrs;
+	uint32_t rx_lenerrs;
+	uint32_t rx_bytes;
+	uint32_t rx_runts;
+	uint32_t rx_fragments;
+	uint32_t rx_pkts_64;
+	uint32_t rx_pkts_65_127;
+	uint32_t rx_pkts_128_255;
+	uint32_t rx_pkts_256_511;
+	uint32_t rx_pkts_512_1023;
+	uint32_t rx_pkts_1024_1518;
+	uint32_t rx_pkts_1519_max;
+	uint32_t rx_pkts_truncated;
+	uint32_t rx_fifo_oflows;
+	uint32_t rx_rrs_errs;
+	uint32_t rx_alignerrs;
+	uint32_t rx_bcast_bytes;
+	uint32_t rx_mcast_bytes;
+	uint32_t rx_pkts_filtered;
+	/* Tx stats. */
+	uint32_t tx_frames;
+	uint32_t tx_bcast_frames;
+	uint32_t tx_mcast_frames;
+	uint32_t tx_pause_frames;
+	uint32_t tx_excess_defer;
+	uint32_t tx_control_frames;
+	uint32_t tx_deferred;
+	uint32_t tx_bytes;
+	uint32_t tx_pkts_64;
+	uint32_t tx_pkts_65_127;
+	uint32_t tx_pkts_128_255;
+	uint32_t tx_pkts_256_511;
+	uint32_t tx_pkts_512_1023;
+	uint32_t tx_pkts_1024_1518;
+	uint32_t tx_pkts_1519_max;
+	uint32_t tx_single_colls;
+	uint32_t tx_multi_colls;
+	uint32_t tx_late_colls;
+	uint32_t tx_excess_colls;
+	uint32_t tx_abort;
+	uint32_t tx_underrun;
+	uint32_t tx_desc_underrun;
+	uint32_t tx_lenerrs;
+	uint32_t tx_pkts_truncated;
+	uint32_t tx_bcast_bytes;
+	uint32_t tx_mcast_bytes;
+	uint32_t updated;
+};
+
+/* CMB(Coalesing message block) */
+struct cmb {
+	uint32_t cons;
+};
+
+/* Rx free descriptor */
+struct rx_desc {
+	uint64_t addr;
+};
+
+/* Rx return descriptor */
+struct rx_rdesc {
+	uint32_t rdinfo;
+#define	RRD_CSUM_MASK			0x0000FFFF
+#define	RRD_RD_CNT_MASK			0x000F0000
+#define	RRD_RD_IDX_MASK			0xFFF00000
+#define	RRD_CSUM_SHIFT			0
+#define	RRD_RD_CNT_SHIFT		16
+#define	RRD_RD_IDX_SHIFT		20
+#define	RRD_CSUM(x)			\
+	(((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT)
+#define	RRD_RD_CNT(x)			\
+	(((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT)
+#define	RRD_RD_IDX(x)			\
+	(((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT)
+	uint32_t rss;
+	uint32_t vtag;
+#define	RRD_VLAN_MASK			0x0000FFFF
+#define	RRD_HEAD_LEN_MASK		0x00FF0000
+#define	RRD_HDS_MASK			0x03000000
+#define	RRD_HDS_NONE			0x00000000
+#define	RRD_HDS_HEAD			0x01000000
+#define	RRD_HDS_DATA			0x02000000
+#define	RRD_CPU_MASK			0x0C000000
+#define	RRD_HASH_FLAG_MASK		0xF0000000
+#define	RRD_VLAN_SHIFT			0
+#define	RRD_HEAD_LEN_SHIFT		16
+#define	RRD_HDS_SHIFT			24
+#define	RRD_CPU_SHIFT			26
+#define	RRD_HASH_FLAG_SHIFT		28
+#define	RRD_VLAN(x)			\
+	(((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT)
+#define	RRD_HEAD_LEN(x)			\
+	(((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT)
+#define	RRD_CPU(x)			\
+	(((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT)
+	uint32_t status;
+#define	RRD_LEN_MASK			0x00003FFF
+#define	RRD_LEN_SHIFT			0
+#define	RRD_TCP_UDPCSUM_NOK		0x00004000
+#define	RRD_IPCSUM_NOK			0x00008000
+#define	RRD_VLAN_TAG			0x00010000
+#define	RRD_PROTO_MASK			0x000E0000
+#define	RRD_PROTO_IPV4			0x00020000
+#define	RRD_PROTO_IPV6			0x000C0000
+#define	RRD_ERR_SUM			0x00100000
+#define	RRD_ERR_CRC			0x00200000
+#define	RRD_ERR_ALIGN			0x00400000
+#define	RRD_ERR_TRUNC			0x00800000
+#define	RRD_ERR_RUNT			0x01000000
+#define	RRD_ERR_ICMP			0x02000000
+#define	RRD_BCAST			0x04000000
+#define	RRD_MCAST			0x08000000
+#define	RRD_SNAP_LLC			0x10000000
+#define	RRD_ETHER			0x00000000
+#define	RRD_FIFO_FULL			0x20000000
+#define	RRD_ERR_LENGTH			0x40000000
+#define	RRD_VALID			0x80000000
+#define	RRD_BYTES(x)			\
+	(((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT)
+#define	RRD_IPV4(x)			\
+	(((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4)
+};
+
+/* Tx descriptor */
+struct tx_desc {
+	uint32_t len;
+#define	TD_BUFLEN_MASK			0x00003FFF
+#define	TD_VLAN_MASK			0xFFFF0000
+#define	TD_BUFLEN_SHIFT			0
+#define	TX_BYTES(x)			\
+	(((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK)
+#define	TD_VLAN_SHIFT			16
+	uint32_t flags;
+#define	TD_L4HDR_OFFSET_MASK		0x000000FF	/* byte unit */
+#define	TD_TCPHDR_OFFSET_MASK		0x000000FF	/* byte unit */
+#define	TD_PLOAD_OFFSET_MASK		0x000000FF	/* 2 bytes unit */
+#define	TD_CUSTOM_CSUM			0x00000100
+#define	TD_IPCSUM			0x00000200
+#define	TD_TCPCSUM			0x00000400
+#define	TD_UDPCSUM			0x00000800
+#define	TD_TSO				0x00001000
+#define	TD_TSO_DESCV1			0x00000000
+#define	TD_TSO_DESCV2			0x00002000
+#define	TD_CON_VLAN_TAG			0x00004000
+#define	TD_INS_VLAN_TAG			0x00008000
+#define	TD_IPV4_DESCV2			0x00010000
+#define	TD_LLC_SNAP			0x00020000
+#define	TD_ETHERNET			0x00000000
+#define	TD_CUSTOM_CSUM_OFFSET_MASK	0x03FC0000	/* 2 bytes unit */
+#define	TD_CUSTOM_CSUM_EVEN_PAD		0x40000000
+#define	TD_MSS_MASK			0x7FFC0000
+#define	TD_EOP				0x80000000
+#define	TD_L4HDR_OFFSET_SHIFT		0
+#define	TD_TCPHDR_OFFSET_SHIFT		0
+#define	TD_PLOAD_OFFSET_SHIFT		0
+#define	TD_CUSTOM_CSUM_OFFSET_SHIFT	18
+#define	TD_MSS_SHIFT			18
+	uint64_t addr;
+};
+
+#endif	/* _IF_ALCREG_H */
@@ -0,0 +1,274 @@
+/*-
+ * Copyright (c) 2009, Pyun YongHyeon <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	_IF_ALCVAR_H
+#define	_IF_ALCVAR_H
+
+#define	ALC_TX_RING_CNT		256
+#define	ALC_TX_RING_ALIGN	sizeof(struct tx_desc)
+#define	ALC_RX_RING_CNT		256
+#define	ALC_RX_RING_ALIGN	sizeof(struct rx_desc)
+#define	ALC_RX_BUF_ALIGN	4
+#define	ALC_RR_RING_CNT		ALC_RX_RING_CNT
+#define	ALC_RR_RING_ALIGN	sizeof(struct rx_rdesc)
+#define	ALC_CMB_ALIGN		8
+#define	ALC_SMB_ALIGN		8
+
+#define	ALC_TSO_MAXSEGSIZE	4096
+#define	ALC_TSO_MAXSIZE		(65535 + sizeof(struct ether_vlan_header))
+#define	ALC_MAXTXSEGS		32
+
+#define	ALC_ADDR_LO(x)		((uint64_t) (x) & 0xFFFFFFFF)
+#define	ALC_ADDR_HI(x)		((uint64_t) (x) >> 32)
+
+#define	ALC_DESC_INC(x, y)	((x) = ((x) + 1) % (y))
+
+/* Water mark to kick reclaiming Tx buffers. */
+#define	ALC_TX_DESC_HIWAT	((ALC_TX_RING_CNT * 6) / 10)
+
+#define	ALC_MSI_MESSAGES	1
+#define	ALC_MSIX_MESSAGES	1
+
+#define	ALC_TX_RING_SZ		\
+	(sizeof(struct tx_desc) * ALC_TX_RING_CNT)
+#define	ALC_RX_RING_SZ		\
+	(sizeof(struct rx_desc) * ALC_RX_RING_CNT)
+#define	ALC_RR_RING_SZ		\
+	(sizeof(struct rx_rdesc) * ALC_RR_RING_CNT)
+#define	ALC_CMB_SZ		(sizeof(struct cmb))
+#define	ALC_SMB_SZ		(sizeof(struct smb))
+
+#define	ALC_PROC_MIN		16
+#define	ALC_PROC_MAX		(ALC_RX_RING_CNT - 1)
+#define	ALC_PROC_DEFAULT	(ALC_RX_RING_CNT / 4)
+
+#define	ALC_JUMBO_FRAMELEN	(9 * 1024)
+#define	ALC_JUMBO_MTU		\
+	(ALC_JUMBO_FRAMELEN - sizeof(struct ether_vlan_header) - ETHER_CRC_LEN)
+#define	ALC_MAX_FRAMELEN	(ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)
+
+/*
+ * The number of bits reserved for MSS in AR8121/AR8132 controllers
+ * are 13 bits. This limits the maximum interface MTU size in TSO
+ * case(8191 + sizeof(struct ip) + sizeof(struct tcphdr)) as upper
+ * stack should not generate TCP segments with MSS greater than the
+ * limit. Also Atheros says that maximum MTU for TSO is 6KB.
+ */
+#define	ALC_TSO_MTU		(6 * 1024)
+
+struct alc_rxdesc {
+	struct mbuf		*rx_m;
+	bus_dmamap_t		rx_dmamap;
+	struct rx_desc		*rx_desc;
+};
+
+struct alc_txdesc {
+	struct mbuf		*tx_m;
+	bus_dmamap_t		tx_dmamap;
+};
+
+struct alc_ring_data {
+	struct tx_desc		*alc_tx_ring;
+	bus_addr_t		alc_tx_ring_paddr;
+	struct rx_desc		*alc_rx_ring;
+	bus_addr_t		alc_rx_ring_paddr;
+	struct rx_rdesc		*alc_rr_ring;
+	bus_addr_t		alc_rr_ring_paddr;
+	struct cmb		*alc_cmb;
+	bus_addr_t		alc_cmb_paddr;
+	struct smb		*alc_smb;
+	bus_addr_t		alc_smb_paddr;
+};
+
+struct alc_chain_data {
+	bus_dma_tag_t		alc_parent_tag;
+	bus_dma_tag_t		alc_buffer_tag;
+	bus_dma_tag_t		alc_tx_tag;
+	struct alc_txdesc	alc_txdesc[ALC_TX_RING_CNT];
+	bus_dma_tag_t		alc_rx_tag;
+	struct alc_rxdesc	alc_rxdesc[ALC_RX_RING_CNT];
+	bus_dma_tag_t		alc_tx_ring_tag;
+	bus_dmamap_t		alc_tx_ring_map;
+	bus_dma_tag_t		alc_rx_ring_tag;
+	bus_dmamap_t		alc_rx_ring_map;
+	bus_dma_tag_t		alc_rr_ring_tag;
+	bus_dmamap_t		alc_rr_ring_map;
+	bus_dmamap_t		alc_rx_sparemap;
+	bus_dma_tag_t		alc_cmb_tag;
+	bus_dmamap_t		alc_cmb_map;
+	bus_dma_tag_t		alc_smb_tag;
+	bus_dmamap_t		alc_smb_map;
+
+	int			alc_tx_prod;
+	int			alc_tx_cons;
+	int			alc_tx_cnt;
+	int			alc_rx_cons;
+	int			alc_rr_cons;
+	int			alc_rxlen;
+
+	struct mbuf		*alc_rxhead;
+	struct mbuf		*alc_rxtail;
+	struct mbuf		*alc_rxprev_tail;
+};
+
+struct alc_hw_stats {
+	/* Rx stats. */
+	uint32_t rx_frames;
+	uint32_t rx_bcast_frames;
+	uint32_t rx_mcast_frames;
+	uint32_t rx_pause_frames;
+	uint32_t rx_control_frames;
+	uint32_t rx_crcerrs;
+	uint32_t rx_lenerrs;
+	uint64_t rx_bytes;
+	uint32_t rx_runts;
+	uint32_t rx_fragments;
+	uint32_t rx_pkts_64;
+	uint32_t rx_pkts_65_127;
+	uint32_t rx_pkts_128_255;
+	uint32_t rx_pkts_256_511;
+	uint32_t rx_pkts_512_1023;
+	uint32_t rx_pkts_1024_1518;
+	uint32_t rx_pkts_1519_max;
+	uint32_t rx_pkts_truncated;
+	uint32_t rx_fifo_oflows;
+	uint32_t rx_rrs_errs;
+	uint32_t rx_alignerrs;
+	uint64_t rx_bcast_bytes;
+	uint64_t rx_mcast_bytes;
+	uint32_t rx_pkts_filtered;
+	/* Tx stats. */
+	uint32_t tx_frames;
+	uint32_t tx_bcast_frames;
+	uint32_t tx_mcast_frames;
+	uint32_t tx_pause_frames;
+	uint32_t tx_excess_defer;
+	uint32_t tx_control_frames;
+	uint32_t tx_deferred;
+	uint64_t tx_bytes;
+	uint32_t tx_pkts_64;
+	uint32_t tx_pkts_65_127;
+	uint32_t tx_pkts_128_255;
+	uint32_t tx_pkts_256_511;
+	uint32_t tx_pkts_512_1023;
+	uint32_t tx_pkts_1024_1518;
+	uint32_t tx_pkts_1519_max;
+	uint32_t tx_single_colls;
+	uint32_t tx_multi_colls;
+	uint32_t tx_late_colls;
+	uint32_t tx_excess_colls;
+	uint32_t tx_abort;
+	uint32_t tx_underrun;
+	uint32_t tx_desc_underrun;
+	uint32_t tx_lenerrs;
+	uint32_t tx_pkts_truncated;
+	uint64_t tx_bcast_bytes;
+	uint64_t tx_mcast_bytes;
+};
+
+/*
+ * Software state per device.
+ */
+struct alc_softc {
+	struct ifnet 		*alc_ifp;
+	device_t		alc_dev;
+	device_t		alc_miibus;
+	struct resource		*alc_res[1];
+	struct resource_spec	*alc_res_spec;
+	struct resource		*alc_irq[ALC_MSI_MESSAGES];
+	struct resource_spec	*alc_irq_spec;
+	void			*alc_intrhand[ALC_MSI_MESSAGES];
+	int			alc_rev;
+	int			alc_chip_rev;
+	int			alc_phyaddr;
+	uint8_t			alc_eaddr[ETHER_ADDR_LEN];
+	uint32_t		alc_dma_rd_burst;
+	uint32_t		alc_dma_wr_burst;
+	uint32_t		alc_rcb;
+	int			alc_flags;
+#define	ALC_FLAG_PCIE		0x0001
+#define	ALC_FLAG_PCIX		0x0002
+#define	ALC_FLAG_MSI		0x0004
+#define	ALC_FLAG_MSIX		0x0008
+#define	ALC_FLAG_FASTETHER	0x0020
+#define	ALC_FLAG_JUMBO		0x0040
+#define	ALC_FLAG_ASPM_MON	0x0080
+#define	ALC_FLAG_CMB_BUG	0x0100
+#define	ALC_FLAG_SMB_BUG	0x0200
+#define	ALC_FLAG_DETACH		0x4000
+#define	ALC_FLAG_LINK		0x8000
+
+	struct callout		alc_tick_ch;
+	struct alc_hw_stats	alc_stats;
+	struct alc_chain_data	alc_cdata;
+	struct alc_ring_data	alc_rdata;
+	int			alc_if_flags;
+	int			alc_watchdog_timer;
+	int			alc_process_limit;
+	volatile int		alc_morework;
+	int			alc_int_rx_mod;
+	int			alc_int_tx_mod;
+	int			alc_buf_size;
+
+	struct task		alc_int_task;
+	struct task		alc_tx_task;
+	struct taskqueue	*alc_tq;
+	struct mtx		alc_mtx;
+};
+
+/* Register access macros. */
+#define	CSR_WRITE_4(_sc, reg, val)	\
+	bus_write_4((_sc)->alc_res[0], (reg), (val))
+#define	CSR_WRITE_2(_sc, reg, val)	\
+	bus_write_2((_sc)->alc_res[0], (reg), (val))
+#define	CSR_WRITE_1(_sc, reg, val)	\
+	bus_write_1((_sc)->alc_res[0], (reg), (val))
+#define	CSR_READ_2(_sc, reg)		\
+	bus_read_2((_sc)->alc_res[0], (reg))
+#define	CSR_READ_4(_sc, reg)		\
+	bus_read_4((_sc)->alc_res[0], (reg))
+
+#define	ALC_RXCHAIN_RESET(_sc)						\
+do {									\
+	(_sc)->alc_cdata.alc_rxhead = NULL;				\
+	(_sc)->alc_cdata.alc_rxtail = NULL;				\
+	(_sc)->alc_cdata.alc_rxprev_tail = NULL;			\
+	(_sc)->alc_cdata.alc_rxlen = 0;					\
+} while (0)
+
+#define	ALC_LOCK(_sc)		mtx_lock(&(_sc)->alc_mtx)
+#define	ALC_UNLOCK(_sc)		mtx_unlock(&(_sc)->alc_mtx)
+#define	ALC_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->alc_mtx, MA_OWNED)
+
+#define	ALC_TX_TIMEOUT		5
+#define	ALC_RESET_TIMEOUT	100
+#define	ALC_TIMEOUT		1000
+#define	ALC_PHY_TIMEOUT		1000
+
+#endif	/* _IF_ALCVAR_H */
@@ -0,0 +1,16 @@
+SubDir HAIKU_TOP src add-ons kernel drivers network atheros813x dev mii ;
+
+UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
+UsePrivateHeaders net system ;
+UsePrivateKernelHeaders ;
+
+UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ;
+
+SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
+
+KernelStaticLibrary atheros813x_mii.a
+	:
+	ukphy.c
+	ukphy_subr.c
+	;
+
@@ -0,0 +1,220 @@
+/*	$NetBSD: ukphy.c,v 1.2 1999/04/23 04:24:32 thorpej Exp $	*/
+
+/*-
+ * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center, and by Frank van der Linden.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 1997 Manuel Bouyer.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Manuel Bouyer.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * driver for generic unknown PHYs
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/errno.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+
+#include <net/if.h>
+#include <net/if_media.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+#include "miibus_if.h"
+
+static int ukphy_probe(device_t);
+static int ukphy_attach(device_t);
+
+static device_method_t ukphy_methods[] = {
+	/* device interface */
+	DEVMETHOD(device_probe,		ukphy_probe),
+	DEVMETHOD(device_attach,	ukphy_attach),
+	DEVMETHOD(device_detach,	mii_phy_detach),
+	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
+	{ 0, 0 }
+};
+
+static devclass_t ukphy_devclass;
+
+static driver_t ukphy_driver = {
+	"ukphy",
+	ukphy_methods,
+	sizeof(struct mii_softc)
+};
+
+DRIVER_MODULE(ukphy, miibus, ukphy_driver, ukphy_devclass, 0, 0);
+
+static int	ukphy_service(struct mii_softc *, struct mii_data *, int);
+
+static int
+ukphy_probe(device_t dev)
+{
+
+	/*
+	 * We know something is here, so always match at a low priority.
+	 */
+	device_set_desc(dev, "Generic IEEE 802.3u media interface");
+	return (BUS_PROBE_GENERIC);
+}
+
+static int
+ukphy_attach(device_t dev)
+{
+	struct mii_softc *sc;
+	struct mii_attach_args *ma;
+	struct mii_data *mii;
+
+	sc = device_get_softc(dev);
+	ma = device_get_ivars(dev);
+	sc->mii_dev = device_get_parent(dev);
+	mii = device_get_softc(sc->mii_dev);
+	LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
+
+	if (bootverbose)
+		device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
+		    MII_OUI(ma->mii_id1, ma->mii_id2),
+		    MII_MODEL(ma->mii_id2), MII_REV(ma->mii_id2));
+
+	sc->mii_inst = mii->mii_instance;
+	sc->mii_phy = ma->mii_phyno;
+	sc->mii_service = ukphy_service;
+	sc->mii_pdata = mii;
+
+	mii->mii_instance++;
+
+	mii_phy_reset(sc);
+
+	sc->mii_capabilities =
+	    PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
+	if (sc->mii_capabilities & BMSR_EXTSTAT)
+		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
+	device_printf(dev, " ");
+	mii_phy_add_media(sc);
+	printf("\n");
+
+	MIIBUS_MEDIAINIT(sc->mii_dev);
+	mii_phy_setmedia(sc);
+
+	return (0);
+}
+
+static int
+ukphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
+{
+	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
+	int reg;
+
+	switch (cmd) {
+	case MII_POLLSTAT:
+		/*
+		 * If we're not polling our PHY instance, just return.
+		 */
+		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
+			return (0);
+		break;
+
+	case MII_MEDIACHG:
+		/*
+		 * If the media indicates a different PHY instance,
+		 * isolate ourselves.
+		 */
+		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
+			reg = PHY_READ(sc, MII_BMCR);
+			PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
+			return (0);
+		}
+
+		/*
+		 * If the interface is not up, don't do anything.
+		 */
+		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
+			break;
+
+		mii_phy_setmedia(sc);
+		break;
+
+	case MII_TICK:
+		/*
+		 * If we're not currently selected, just return.
+		 */
+		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
+			return (0);
+		if (mii_phy_tick(sc) == EJUSTRETURN)
+			return (0);
+		break;
+	}
+
+	/* Update the media status. */
+	ukphy_status(sc);
+
+	/* Callback if something changed. */
+	mii_phy_update(sc, cmd);
+	return (0);
+}
@@ -0,0 +1,129 @@
+/*	$NetBSD: ukphy_subr.c,v 1.2 1998/11/05 04:08:02 thorpej Exp $	*/
+
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center, and by Frank van der Linden.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * Subroutines shared by the ukphy driver and other PHY drivers.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/socket.h>
+#include <sys/module.h>
+#include <sys/bus.h>
+
+#include <net/if.h>
+#include <net/if_media.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+#include "miibus_if.h"
+
+/*
+ * Media status subroutine.  If a PHY driver does media detection simply
+ * by decoding the NWay autonegotiation, use this routine.
+ */
+void
+ukphy_status(struct mii_softc *phy)
+{
+	struct mii_data *mii = phy->mii_pdata;
+	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
+	int bmsr, bmcr, anlpar, gtcr, gtsr;
+
+	mii->mii_media_status = IFM_AVALID;
+	mii->mii_media_active = IFM_ETHER;
+
+	bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR);
+	if (bmsr & BMSR_LINK)
+		mii->mii_media_status |= IFM_ACTIVE;
+
+	bmcr = PHY_READ(phy, MII_BMCR);
+	if (bmcr & BMCR_ISO) {
+		mii->mii_media_active |= IFM_NONE;
+		mii->mii_media_status = 0;
+		return;
+	}
+
+	if (bmcr & BMCR_LOOP)
+		mii->mii_media_active |= IFM_LOOP;
+
+	if (bmcr & BMCR_AUTOEN) {
+		/*
+		 * NWay autonegotiation takes the highest-order common
+		 * bit of the ANAR and ANLPAR (i.e. best media advertised
+		 * both by us and our link partner).
+		 */
+		if ((bmsr & BMSR_ACOMP) == 0) {
+			/* Erg, still trying, I guess... */
+			mii->mii_media_active |= IFM_NONE;
+			return;
+		}
+
+		anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR);
+		if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 &&
+		    (phy->mii_extcapabilities &
+		    (EXTSR_1000THDX | EXTSR_1000TFDX)) != 0) {
+			gtcr = PHY_READ(phy, MII_100T2CR);
+			gtsr = PHY_READ(phy, MII_100T2SR);
+		} else
+			gtcr = gtsr = 0;
+
+		if ((gtcr & GTCR_ADV_1000TFDX) && (gtsr & GTSR_LP_1000TFDX))
+			mii->mii_media_active |= IFM_1000_T|IFM_FDX;
+		else if ((gtcr & GTCR_ADV_1000THDX) &&
+		    (gtsr & GTSR_LP_1000THDX))
+			mii->mii_media_active |= IFM_1000_T;
+		else if (anlpar & ANLPAR_TX_FD)
+			mii->mii_media_active |= IFM_100_TX|IFM_FDX;
+		else if (anlpar & ANLPAR_T4)
+			mii->mii_media_active |= IFM_100_T4;
+		else if (anlpar & ANLPAR_TX)
+			mii->mii_media_active |= IFM_100_TX;
+		else if (anlpar & ANLPAR_10_FD)
+			mii->mii_media_active |= IFM_10_T|IFM_FDX;
+		else if (anlpar & ANLPAR_10)
+			mii->mii_media_active |= IFM_10_T;
+		else
+			mii->mii_media_active |= IFM_NONE;
+	} else
+		mii->mii_media_active = ife->ifm_media;
+}