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Style cleanups only, no functional change.

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* Make the pointer style consistent accross all components, which should make it
  easier when working all over the place.
* 80 char limits.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42863 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Michael Lotz
2011-10-16 15:15:03 +00:00
parent 2d004e3e89
commit c788baed28
17 changed files with 314 additions and 249 deletions
Download Patch File Download Diff File Expand all files Collapse all files
headers/private/graphics/intel_extreme/intel_extreme.h
+2 -1
View File
@@ -227,7 +227,8 @@ struct intel_free_graphics_memory {
// Register definitions, taken from X driver // Register definitions, taken from X driver
// PCI bridge memory management // PCI bridge memory management
#define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // GGC - (G)MCH Graphics Control Register #define INTEL_GRAPHICS_MEMORY_CONTROL 0x52
// GGC - (G)MCH Graphics Control Register
#define MEMORY_CONTROL_ENABLED 0x0004 #define MEMORY_CONTROL_ENABLED 0x0004
#define MEMORY_MASK 0x0001 #define MEMORY_MASK 0x0001
#define STOLEN_MEMORY_MASK 0x00f0 #define STOLEN_MEMORY_MASK 0x00f0
src/add-ons/accelerants/intel_extreme/accelerant_protos.h
+25 -18
View File
@@ -31,16 +31,18 @@ sem_id intel_accelerant_retrace_semaphore(void);
// modes & constraints // modes & constraints
uint32 intel_accelerant_mode_count(void); uint32 intel_accelerant_mode_count(void);
status_t intel_get_mode_list(display_mode* dm); status_t intel_get_mode_list(display_mode* dm);
status_t intel_propose_display_mode(display_mode *target, const display_mode *low, status_t intel_propose_display_mode(display_mode* target,
const display_mode *high); const display_mode* low, const display_mode* high);
status_t intel_set_display_mode(display_mode* mode); status_t intel_set_display_mode(display_mode* mode);
status_t intel_get_display_mode(display_mode* currentMode); status_t intel_get_display_mode(display_mode* currentMode);
status_t intel_get_edid_info(void* info, size_t size, uint32* _version); status_t intel_get_edid_info(void* info, size_t size, uint32* _version);
status_t intel_get_frame_buffer_config(frame_buffer_config* config); status_t intel_get_frame_buffer_config(frame_buffer_config* config);
status_t intel_get_pixel_clock_limits(display_mode *mode, uint32 *low, uint32 *high); status_t intel_get_pixel_clock_limits(display_mode* mode, uint32* low,
uint32* high);
status_t intel_move_display(uint16 hDisplayStart, uint16 vDisplayStart); status_t intel_move_display(uint16 hDisplayStart, uint16 vDisplayStart);
status_t intel_get_timing_constraints(display_timing_constraints* constraints); status_t intel_get_timing_constraints(display_timing_constraints* constraints);
void intel_set_indexed_colors(uint count, uint8 first, uint8 *colorData, uint32 flags); void intel_set_indexed_colors(uint count, uint8 first, uint8* colorData,
uint32 flags);
// DPMS // DPMS
uint32 intel_dpms_capabilities(void); uint32 intel_dpms_capabilities(void);
@@ -48,8 +50,8 @@ uint32 intel_dpms_mode(void);
status_t intel_set_dpms_mode(uint32 flags); status_t intel_set_dpms_mode(uint32 flags);
// cursor // cursor
status_t intel_set_cursor_shape(uint16 width, uint16 height, uint16 hotX, uint16 hotY, status_t intel_set_cursor_shape(uint16 width, uint16 height, uint16 hotX,
uint8 *andMask, uint8 *xorMask); uint16 hotY, uint8* andMask, uint8* xorMask);
void intel_move_cursor(uint16 x, uint16 y); void intel_move_cursor(uint16 x, uint16 y);
void intel_show_cursor(bool isVisible); void intel_show_cursor(bool isVisible);
@@ -63,27 +65,32 @@ status_t intel_get_sync_token(engine_token *engineToken, sync_token *syncToken);
status_t intel_sync_to_token(sync_token* syncToken); status_t intel_sync_to_token(sync_token* syncToken);
// 2D acceleration // 2D acceleration
void intel_screen_to_screen_blit(engine_token *engineToken, blit_params *list, uint32 count); void intel_screen_to_screen_blit(engine_token* engineToken,
void intel_fill_rectangle(engine_token *engineToken, uint32 color, fill_rect_params *list, blit_params* list, uint32 count);
void intel_fill_rectangle(engine_token* engineToken, uint32 color,
fill_rect_params* list, uint32 count);
void intel_invert_rectangle(engine_token* engineToken, fill_rect_params* list,
uint32 count);
void intel_fill_span(engine_token* engineToken, uint32 color, uint16* list,
uint32 count); uint32 count);
void intel_invert_rectangle(engine_token *engineToken, fill_rect_params *list, uint32 count);
void intel_fill_span(engine_token *engineToken, uint32 color, uint16 *list, uint32 count);
// overlay // overlay
uint32 intel_overlay_count(const display_mode* mode); uint32 intel_overlay_count(const display_mode* mode);
const uint32* intel_overlay_supported_spaces(const display_mode* mode); const uint32* intel_overlay_supported_spaces(const display_mode* mode);
uint32 intel_overlay_supported_features(uint32 colorSpace); uint32 intel_overlay_supported_features(uint32 colorSpace);
const overlay_buffer *intel_allocate_overlay_buffer(color_space space, uint16 width, const overlay_buffer* intel_allocate_overlay_buffer(color_space space,
uint16 height); uint16 width, uint16 height);
status_t intel_release_overlay_buffer(const overlay_buffer* buffer); status_t intel_release_overlay_buffer(const overlay_buffer* buffer);
status_t intel_get_overlay_constraints(const display_mode *mode, const overlay_buffer *buffer, status_t intel_get_overlay_constraints(const display_mode* mode,
overlay_constraints *constraints); const overlay_buffer* buffer, overlay_constraints* constraints);
overlay_token intel_allocate_overlay(void); overlay_token intel_allocate_overlay(void);
status_t intel_release_overlay(overlay_token overlayToken); status_t intel_release_overlay(overlay_token overlayToken);
status_t intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer, status_t intel_configure_overlay(overlay_token overlayToken,
const overlay_window *window, const overlay_view *view); const overlay_buffer* buffer, const overlay_window* window,
status_t i965_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer, const overlay_view* view);
const overlay_window *window, const overlay_view *view); status_t i965_configure_overlay(overlay_token overlayToken,
const overlay_buffer* buffer, const overlay_window* window,
const overlay_view* view);
#ifdef __cplusplus #ifdef __cplusplus
} }
src/add-ons/accelerants/intel_extreme/cursor.cpp
+8 -4
View File
@@ -23,7 +23,8 @@ intel_set_cursor_shape(uint16 width, uint16 height, uint16 hotX, uint16 hotY,
write32(INTEL_CURSOR_CONTROL, 0); write32(INTEL_CURSOR_CONTROL, 0);
// disable cursor // disable cursor
// In two-color mode, the data is ordered as follows (always 64 bit per line): // In two-color mode, the data is ordered as follows (always 64 bit per
// line):
// plane 1: line 0 (AND mask) // plane 1: line 0 (AND mask)
// plane 0: line 0 (XOR mask) // plane 0: line 0 (XOR mask)
// plane 1: line 1 (AND mask) // plane 1: line 1 (AND mask)
@@ -49,10 +50,12 @@ intel_set_cursor_shape(uint16 width, uint16 height, uint16 hotX, uint16 hotY,
gInfo->shared_info->cursor_format = CURSOR_FORMAT_2_COLORS; gInfo->shared_info->cursor_format = CURSOR_FORMAT_2_COLORS;
write32(INTEL_CURSOR_CONTROL, CURSOR_ENABLED | gInfo->shared_info->cursor_format); write32(INTEL_CURSOR_CONTROL,
CURSOR_ENABLED | gInfo->shared_info->cursor_format);
write32(INTEL_CURSOR_SIZE, height << 12 | width); write32(INTEL_CURSOR_SIZE, height << 12 | width);
write32(INTEL_CURSOR_BASE, (uint32)gInfo->shared_info->physical_graphics_memory write32(INTEL_CURSOR_BASE,
(uint32)gInfo->shared_info->physical_graphics_memory
+ gInfo->shared_info->cursor_buffer_offset); + gInfo->shared_info->cursor_buffer_offset);
// changing the hot point changes the cursor position, too // changing the hot point changes the cursor position, too
@@ -104,7 +107,8 @@ intel_show_cursor(bool isVisible)
write32(INTEL_CURSOR_CONTROL, (isVisible ? CURSOR_ENABLED : 0) write32(INTEL_CURSOR_CONTROL, (isVisible ? CURSOR_ENABLED : 0)
| gInfo->shared_info->cursor_format); | gInfo->shared_info->cursor_format);
write32(INTEL_CURSOR_BASE, (uint32)gInfo->shared_info->physical_graphics_memory write32(INTEL_CURSOR_BASE,
(uint32)gInfo->shared_info->physical_graphics_memory
+ gInfo->shared_info->cursor_buffer_offset); + gInfo->shared_info->cursor_buffer_offset);
gInfo->shared_info->cursor_visible = isVisible; gInfo->shared_info->cursor_visible = isVisible;
src/add-ons/accelerants/intel_extreme/dpms.cpp
+40 -18
View File
@@ -27,21 +27,32 @@ enable_display_plane(bool enable)
uint32 planeBControl = read32(INTEL_DISPLAY_B_CONTROL); uint32 planeBControl = read32(INTEL_DISPLAY_B_CONTROL);
if (enable) { if (enable) {
// when enabling the display, the register values are updated automatically // when enabling the display, the register values are updated
if (gInfo->head_mode & HEAD_MODE_A_ANALOG) // automatically
write32(INTEL_DISPLAY_A_CONTROL, planeAControl | DISPLAY_CONTROL_ENABLED); if (gInfo->head_mode & HEAD_MODE_A_ANALOG) {
if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) write32(INTEL_DISPLAY_A_CONTROL,
write32(INTEL_DISPLAY_B_CONTROL, planeBControl | DISPLAY_CONTROL_ENABLED); planeAControl | DISPLAY_CONTROL_ENABLED);
}
if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) {
write32(INTEL_DISPLAY_B_CONTROL,
planeBControl | DISPLAY_CONTROL_ENABLED);
}
read32(INTEL_DISPLAY_A_BASE); read32(INTEL_DISPLAY_A_BASE);
// flush the eventually cached PCI bus writes // flush the eventually cached PCI bus writes
} else { } else {
// when disabling it, we have to trigger the update using a write to // when disabling it, we have to trigger the update using a write to
// the display base address // the display base address
if (gInfo->head_mode & HEAD_MODE_A_ANALOG) if (gInfo->head_mode & HEAD_MODE_A_ANALOG) {
write32(INTEL_DISPLAY_A_CONTROL, planeAControl & ~DISPLAY_CONTROL_ENABLED); write32(INTEL_DISPLAY_A_CONTROL,
if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) planeAControl & ~DISPLAY_CONTROL_ENABLED);
write32(INTEL_DISPLAY_B_CONTROL, planeBControl & ~DISPLAY_CONTROL_ENABLED); }
if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) {
write32(INTEL_DISPLAY_B_CONTROL,
planeBControl & ~DISPLAY_CONTROL_ENABLED);
}
set_frame_buffer_base(); set_frame_buffer_base();
} }
@@ -55,15 +66,25 @@ enable_display_pipe(bool enable)
uint32 pipeBControl = read32(INTEL_DISPLAY_B_PIPE_CONTROL); uint32 pipeBControl = read32(INTEL_DISPLAY_B_PIPE_CONTROL);
if (enable) { if (enable) {
if (gInfo->head_mode & HEAD_MODE_A_ANALOG) if (gInfo->head_mode & HEAD_MODE_A_ANALOG) {
write32(INTEL_DISPLAY_A_PIPE_CONTROL, pipeAControl | DISPLAY_PIPE_ENABLED); write32(INTEL_DISPLAY_A_PIPE_CONTROL,
if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) pipeAControl | DISPLAY_PIPE_ENABLED);
write32(INTEL_DISPLAY_B_PIPE_CONTROL, pipeBControl | DISPLAY_PIPE_ENABLED); }
if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) {
write32(INTEL_DISPLAY_B_PIPE_CONTROL,
pipeBControl | DISPLAY_PIPE_ENABLED);
}
} else { } else {
if (gInfo->head_mode & HEAD_MODE_A_ANALOG) if (gInfo->head_mode & HEAD_MODE_A_ANALOG) {
write32(INTEL_DISPLAY_A_PIPE_CONTROL, pipeAControl & ~DISPLAY_PIPE_ENABLED); write32(INTEL_DISPLAY_A_PIPE_CONTROL,
if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) pipeAControl & ~DISPLAY_PIPE_ENABLED);
write32(INTEL_DISPLAY_B_PIPE_CONTROL, pipeBControl & ~DISPLAY_PIPE_ENABLED); }
if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) {
write32(INTEL_DISPLAY_B_PIPE_CONTROL,
pipeBControl & ~DISPLAY_PIPE_ENABLED);
}
} }
read32(INTEL_DISPLAY_A_BASE); read32(INTEL_DISPLAY_A_BASE);
@@ -167,7 +188,8 @@ set_display_power_mode(uint32 mode)
write32(INTEL_DISPLAY_A_ANALOG_PORT, write32(INTEL_DISPLAY_A_ANALOG_PORT,
(read32(INTEL_DISPLAY_A_ANALOG_PORT) (read32(INTEL_DISPLAY_A_ANALOG_PORT)
& ~(DISPLAY_MONITOR_MODE_MASK | DISPLAY_MONITOR_PORT_ENABLED)) & ~(DISPLAY_MONITOR_MODE_MASK | DISPLAY_MONITOR_PORT_ENABLED))
| monitorMode | (mode != B_DPMS_OFF ? DISPLAY_MONITOR_PORT_ENABLED : 0)); | monitorMode
| (mode != B_DPMS_OFF ? DISPLAY_MONITOR_PORT_ENABLED : 0));
} }
if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) { if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) {
write32(INTEL_DISPLAY_B_DIGITAL_PORT, write32(INTEL_DISPLAY_B_DIGITAL_PORT,
src/add-ons/accelerants/intel_extreme/mode.cpp
+28 -16
View File
@@ -99,13 +99,17 @@ set_i2c_signals(void* cookie, int clock, int data)
if (data != 0) if (data != 0)
value |= I2C_DATA_DIRECTION_MASK; value |= I2C_DATA_DIRECTION_MASK;
else else {
value |= I2C_DATA_DIRECTION_MASK | I2C_DATA_DIRECTION_OUT | I2C_DATA_VALUE_MASK; value |= I2C_DATA_DIRECTION_MASK | I2C_DATA_DIRECTION_OUT
| I2C_DATA_VALUE_MASK;
}
if (clock != 0) if (clock != 0)
value |= I2C_CLOCK_DIRECTION_MASK; value |= I2C_CLOCK_DIRECTION_MASK;
else else {
value |= I2C_CLOCK_DIRECTION_MASK | I2C_CLOCK_DIRECTION_OUT | I2C_CLOCK_VALUE_MASK; value |= I2C_CLOCK_DIRECTION_MASK | I2C_CLOCK_DIRECTION_OUT
| I2C_CLOCK_VALUE_MASK;
}
write32(ioRegister, value); write32(ioRegister, value);
read32(ioRegister); read32(ioRegister);
@@ -285,12 +289,14 @@ get_pll_limits(pll_limits &limits)
limits = kLimits; limits = kLimits;
} }
TRACE(("PLL limits, min: p %lu (p1 %lu, p2 %lu), n %lu, m %lu (m1 %lu, m2 %lu)\n", TRACE(("PLL limits, min: p %lu (p1 %lu, p2 %lu), n %lu, m %lu "
limits.min.post, limits.min.post1, limits.min.post2, limits.min.n, "(m1 %lu, m2 %lu)\n", limits.min.post, limits.min.post1,
limits.min.m, limits.min.m1, limits.min.m2)); limits.min.post2, limits.min.n, limits.min.m, limits.min.m1,
TRACE(("PLL limits, max: p %lu (p1 %lu, p2 %lu), n %lu, m %lu (m1 %lu, m2 %lu)\n", limits.min.m2));
limits.max.post, limits.max.post1, limits.max.post2, limits.max.n, TRACE(("PLL limits, max: p %lu (p1 %lu, p2 %lu), n %lu, m %lu "
limits.max.m, limits.max.m1, limits.max.m2)); "(m1 %lu, m2 %lu)\n", limits.max.post, limits.max.post1,
limits.max.post2, limits.max.n, limits.max.m, limits.max.m1,
limits.max.m2));
} }
@@ -316,7 +322,8 @@ compute_pll_divisors(const display_mode &current, pll_divisors& divisors,
bool isLVDS) bool isLVDS)
{ {
float requestedPixelClock = current.timing.pixel_clock / 1000.0f; float requestedPixelClock = current.timing.pixel_clock / 1000.0f;
float referenceClock = gInfo->shared_info->pll_info.reference_frequency / 1000.0f; float referenceClock
= gInfo->shared_info->pll_info.reference_frequency / 1000.0f;
pll_limits limits; pll_limits limits;
get_pll_limits(limits); get_pll_limits(limits);
@@ -344,7 +351,8 @@ compute_pll_divisors(const display_mode &current, pll_divisors& divisors,
pll_divisors bestDivisors; pll_divisors bestDivisors;
bool is_igd = gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD); bool is_igd = gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD);
for (divisors.m1 = limits.min.m1; divisors.m1 <= limits.max.m1; divisors.m1++) { for (divisors.m1 = limits.min.m1; divisors.m1 <= limits.max.m1;
divisors.m1++) {
for (divisors.m2 = limits.min.m2; divisors.m2 <= limits.max.m2 for (divisors.m2 = limits.min.m2; divisors.m2 <= limits.max.m2
&& ((divisors.m2 < divisors.m1) || is_igd); divisors.m2++) { && ((divisors.m2 < divisors.m1) || is_igd); divisors.m2++) {
for (divisors.n = limits.min.n; divisors.n <= limits.max.n; for (divisors.n = limits.min.n; divisors.n <= limits.max.n;
@@ -358,7 +366,8 @@ compute_pll_divisors(const display_mode &current, pll_divisors& divisors,
continue; continue;
float error = fabs(requestedPixelClock float error = fabs(requestedPixelClock
- ((referenceClock * divisors.m) / divisors.n) / divisors.post); - ((referenceClock * divisors.m) / divisors.n)
/ divisors.post);
if (error < best) { if (error < best) {
best = error; best = error;
bestDivisors = divisors; bestDivisors = divisors;
@@ -373,7 +382,8 @@ compute_pll_divisors(const display_mode &current, pll_divisors& divisors,
divisors = bestDivisors; divisors = bestDivisors;
TRACE(("found: %g MHz, p = %lu (p1 = %lu, p2 = %lu), n = %lu, m = %lu (m1 = %lu, m2 = %lu)\n", TRACE(("found: %g MHz, p = %lu (p1 = %lu, p2 = %lu), n = %lu, m = %lu "
"(m1 = %lu, m2 = %lu)\n",
((referenceClock * divisors.m) / divisors.n) / divisors.post, ((referenceClock * divisors.m) / divisors.n) / divisors.post,
divisors.post, divisors.post1, divisors.post2, divisors.n, divisors.post, divisors.post1, divisors.post2, divisors.n,
divisors.m, divisors.m1, divisors.m2)); divisors.m, divisors.m1, divisors.m2));
@@ -1153,7 +1163,8 @@ intel_get_pixel_clock_limits(display_mode *mode, uint32 *_low, uint32 *_high)
if (_low != NULL) { if (_low != NULL) {
// lower limit of about 48Hz vertical refresh // lower limit of about 48Hz vertical refresh
uint32 totalClocks = (uint32)mode->timing.h_total * (uint32)mode->timing.v_total; uint32 totalClocks = (uint32)mode->timing.h_total
* (uint32)mode->timing.v_total;
uint32 low = (totalClocks * 48L) / 1000L; uint32 low = (totalClocks * 48L) / 1000L;
if (low < gInfo->shared_info->pll_info.min_frequency) if (low < gInfo->shared_info->pll_info.min_frequency)
low = gInfo->shared_info->pll_info.min_frequency; low = gInfo->shared_info->pll_info.min_frequency;
@@ -1204,7 +1215,8 @@ intel_get_timing_constraints(display_timing_constraints *constraints)
void void
intel_set_indexed_colors(uint count, uint8 first, uint8* colors, uint32 flags) intel_set_indexed_colors(uint count, uint8 first, uint8* colors, uint32 flags)
{ {
TRACE(("intel_set_indexed_colors(colors = %p, first = %u)\n", colors, first)); TRACE(("intel_set_indexed_colors(colors = %p, first = %u)\n", colors,
first));
if (colors == NULL) if (colors == NULL)
return; return;
src/add-ons/accelerants/intel_extreme/overlay.cpp
+27 -18
View File
@@ -63,19 +63,23 @@ split_coefficient(double &coefficient, int32 mantissaSize,
int32 maxValue = 1 << mantissaSize; int32 maxValue = 1 << mantissaSize;
res = 12 - mantissaSize; res = 12 - mantissaSize;
if ((intCoefficient = (int)(absCoefficient * 4 * maxValue + 0.5)) < maxValue) { if ((intCoefficient = (int)(absCoefficient * 4 * maxValue + 0.5))
< maxValue) {
splitCoefficient.exponent = 3; splitCoefficient.exponent = 3;
splitCoefficient.mantissa = intCoefficient << res; splitCoefficient.mantissa = intCoefficient << res;
coefficient = (double)intCoefficient / (double)(4 * maxValue); coefficient = (double)intCoefficient / (double)(4 * maxValue);
} else if ((intCoefficient = (int)(absCoefficient * 2 * maxValue + 0.5)) < maxValue) { } else if ((intCoefficient = (int)(absCoefficient * 2 * maxValue + 0.5))
< maxValue) {
splitCoefficient.exponent = 2; splitCoefficient.exponent = 2;
splitCoefficient.mantissa = intCoefficient << res; splitCoefficient.mantissa = intCoefficient << res;
coefficient = (double)intCoefficient / (double)(2 * maxValue); coefficient = (double)intCoefficient / (double)(2 * maxValue);
} else if ((intCoefficient = (int)(absCoefficient * maxValue + 0.5)) < maxValue) { } else if ((intCoefficient = (int)(absCoefficient * maxValue + 0.5))
< maxValue) {
splitCoefficient.exponent = 1; splitCoefficient.exponent = 1;
splitCoefficient.mantissa = intCoefficient << res; splitCoefficient.mantissa = intCoefficient << res;
coefficient = (double)intCoefficient / (double)maxValue; coefficient = (double)intCoefficient / (double)maxValue;
} else if ((intCoefficient = (int)(absCoefficient * maxValue * 0.5 + 0.5)) < maxValue) { } else if ((intCoefficient = (int)(absCoefficient * maxValue * 0.5 + 0.5))
< maxValue) {
splitCoefficient.exponent = 0; splitCoefficient.exponent = 0;
splitCoefficient.mantissa = intCoefficient << res; splitCoefficient.mantissa = intCoefficient << res;
coefficient = (double)intCoefficient / (double)(maxValue / 2); coefficient = (double)intCoefficient / (double)(maxValue / 2);
@@ -205,13 +209,13 @@ set_color_key(const overlay_window *window)
break; break;
case B_RGB15: case B_RGB15:
set_color_key(window->red.value << 3, window->green.value << 3, set_color_key(window->red.value << 3, window->green.value << 3,
window->blue.value << 3, window->red.mask << 3, window->green.mask << 3, window->blue.value << 3, window->red.mask << 3,
window->blue.mask << 3); window->green.mask << 3, window->blue.mask << 3);
break; break;
case B_RGB16: case B_RGB16:
set_color_key(window->red.value << 3, window->green.value << 2, set_color_key(window->red.value << 3, window->green.value << 2,
window->blue.value << 3, window->red.mask << 3, window->green.mask << 2, window->blue.value << 3, window->red.mask << 3,
window->blue.mask << 3); window->green.mask << 2, window->blue.mask << 3);
break; break;
default: default:
@@ -239,9 +243,11 @@ update_overlay(bool updateCoefficients)
queue.PutWaitFor(COMMAND_WAIT_FOR_OVERLAY_FLIP); queue.PutWaitFor(COMMAND_WAIT_FOR_OVERLAY_FLIP);
queue.PutFlush(); queue.PutFlush();
TRACE(("update overlay: UP: %lx, TST: %lx, ST: %lx, CMD: %lx (%lx), ERR: %lx\n", TRACE(("update overlay: UP: %lx, TST: %lx, ST: %lx, CMD: %lx (%lx), "
read32(INTEL_OVERLAY_UPDATE), read32(INtEL_OVERLAY_TEST), read32(INTEL_OVERLAY_STATUS), "ERR: %lx\n", read32(INTEL_OVERLAY_UPDATE), read32(INtEL_OVERLAY_TEST),
*(((uint32 *)gInfo->overlay_registers) + 0x68/4), read32(0x30168), read32(0x2024))); read32(INTEL_OVERLAY_STATUS),
*(((uint32*)gInfo->overlay_registers) + 0x68/4), read32(0x30168),
read32(0x2024)));
} }
@@ -259,9 +265,11 @@ show_overlay(void)
queue.PutOverlayFlip(COMMAND_OVERLAY_ON, true); queue.PutOverlayFlip(COMMAND_OVERLAY_ON, true);
queue.PutFlush(); queue.PutFlush();
TRACE(("show overlay: UP: %lx, TST: %lx, ST: %lx, CMD: %lx (%lx), ERR: %lx\n", TRACE(("show overlay: UP: %lx, TST: %lx, ST: %lx, CMD: %lx (%lx), "
read32(INTEL_OVERLAY_UPDATE), read32(INTEL_OVERLAY_TEST), read32(INTEL_OVERLAY_STATUS), "ERR: %lx\n", read32(INTEL_OVERLAY_UPDATE), read32(INTEL_OVERLAY_TEST),
*(((uint32 *)gInfo->overlay_registers) + 0x68/4), read32(0x30168), read32(0x2024))); read32(INTEL_OVERLAY_STATUS),
*(((uint32*)gInfo->overlay_registers) + 0x68/4), read32(0x30168),
read32(0x2024)));
} }
@@ -336,8 +344,8 @@ const overlay_buffer *
intel_allocate_overlay_buffer(color_space colorSpace, uint16 width, intel_allocate_overlay_buffer(color_space colorSpace, uint16 width,
uint16 height) uint16 height)
{ {
TRACE(("intel_allocate_overlay_buffer(width %u, height %u, colorSpace %lu)\n", TRACE(("intel_allocate_overlay_buffer(width %u, height %u, "
width, height, colorSpace)); "colorSpace %lu)\n", width, height, colorSpace));
intel_shared_info &sharedInfo = *gInfo->shared_info; intel_shared_info &sharedInfo = *gInfo->shared_info;
uint32 bytesPerPixel; uint32 bytesPerPixel;
@@ -525,8 +533,9 @@ intel_release_overlay(overlay_token overlayToken)
status_t status_t
intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer, intel_configure_overlay(overlay_token overlayToken,
const overlay_window *window, const overlay_view *view) const overlay_buffer* buffer, const overlay_window* window,
const overlay_view* view)
{ {
TRACE(("intel_configure_overlay: buffer %p, window %p, view %p\n", TRACE(("intel_configure_overlay: buffer %p, window %p, view %p\n",
buffer, window, view)); buffer, window, view));
src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
+10 -7
View File
@@ -219,7 +219,8 @@ determine_memory_sizes(intel_info &info, size_t &gttSize, size_t &stolenSize)
switch (memoryConfig & STOLEN_MEMORY_MASK) { switch (memoryConfig & STOLEN_MEMORY_MASK) {
case i830_LOCAL_MEMORY_ONLY: case i830_LOCAL_MEMORY_ONLY:
// TODO: determine its size! // TODO: determine its size!
dprintf("intel_gart: getting local memory size not implemented.\n"); dprintf("intel_gart: getting local memory size not "
"implemented.\n");
break; break;
case i830_STOLEN_512K: case i830_STOLEN_512K:
memorySize >>= 1; memorySize >>= 1;
@@ -357,8 +358,8 @@ intel_map(intel_info &info)
int fbIndex = 0; int fbIndex = 0;
int mmioIndex = 1; int mmioIndex = 1;
if ((info.type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx) { if ((info.type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx) {
// for some reason Intel saw the need to change the order of the mappings // for some reason Intel saw the need to change the order of the
// with the introduction of the i9xx family // mappings with the introduction of the i9xx family
mmioIndex = 0; mmioIndex = 0;
fbIndex = 2; fbIndex = 2;
} }
@@ -398,7 +399,8 @@ intel_map(intel_info &info)
info.gtt_physical_base = info.display.u.h0.base_registers[mmioIndex] info.gtt_physical_base = info.display.u.h0.base_registers[mmioIndex]
+ (2UL << 20); + (2UL << 20);
} else } else
info.gtt_physical_base = get_pci_config(info.display, i915_GTT_BASE, 4); info.gtt_physical_base
= get_pci_config(info.display, i915_GTT_BASE, 4);
} else { } else {
info.gtt_physical_base = read32(info.registers info.gtt_physical_base = read32(info.registers
+ INTEL_PAGE_TABLE_CONTROL) & ~PAGE_TABLE_ENABLED; + INTEL_PAGE_TABLE_CONTROL) & ~PAGE_TABLE_ENABLED;
@@ -417,8 +419,8 @@ intel_map(intel_info &info)
info.gtt_entries = gttSize / 4096; info.gtt_entries = gttSize / 4096;
info.gtt_stolen_entries = stolenSize / 4096; info.gtt_stolen_entries = stolenSize / 4096;
TRACE("GTT base %lx, size %lu, entries %lu, stolen %lu\n", info.gtt_physical_base, TRACE("GTT base %lx, size %lu, entries %lu, stolen %lu\n",
gttSize, info.gtt_entries, stolenSize); info.gtt_physical_base, gttSize, info.gtt_entries, stolenSize);
AreaKeeper gttMapper; AreaKeeper gttMapper;
info.gtt_area = gttMapper.Map("intel GMCH gtt", info.gtt_area = gttMapper.Map("intel GMCH gtt",
@@ -439,7 +441,8 @@ intel_map(intel_info &info)
info.aperture_size >> 20, gttSize >> 10); info.aperture_size >> 20, gttSize >> 10);
dprintf("intel_gart: GTT base = 0x%lx\n", info.gtt_physical_base); dprintf("intel_gart: GTT base = 0x%lx\n", info.gtt_physical_base);
dprintf("intel_gart: MMIO base = 0x%lx\n", info.display.u.h0.base_registers[mmioIndex]); dprintf("intel_gart: MMIO base = 0x%lx\n",
info.display.u.h0.base_registers[mmioIndex]);
dprintf("intel_gart: GMR base = 0x%lx\n", info.aperture_physical_base); dprintf("intel_gart: GMR base = 0x%lx\n", info.aperture_physical_base);
AreaKeeper apertureMapper; AreaKeeper apertureMapper;
src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp
+10 -5
View File
@@ -39,9 +39,12 @@
static status_t device_open(const char* name, uint32 flags, void** _cookie); static status_t device_open(const char* name, uint32 flags, void** _cookie);
static status_t device_close(void* data); static status_t device_close(void* data);
static status_t device_free(void* data); static status_t device_free(void* data);
static status_t device_ioctl(void *data, uint32 opcode, void *buffer, size_t length); static status_t device_ioctl(void* data, uint32 opcode, void* buffer,
static status_t device_read(void *data, off_t offset, void *buffer, size_t *length); size_t length);
static status_t device_write(void *data, off_t offset, const void *buffer, size_t *length); static status_t device_read(void* data, off_t offset, void* buffer,
size_t* length);
static status_t device_write(void* data, off_t offset, const void* buffer,
size_t* length);
device_hooks gDeviceHooks = { device_hooks gDeviceHooks = {
@@ -216,7 +219,8 @@ device_ioctl(void *data, uint32 op, void *buffer, size_t bufferLength)
sizeof(intel_allocate_graphics_memory)) < B_OK) sizeof(intel_allocate_graphics_memory)) < B_OK)
return B_BAD_ADDRESS; return B_BAD_ADDRESS;
#else #else
memcpy(&allocMemory, buffer, sizeof(intel_allocate_graphics_memory)); memcpy(&allocMemory, buffer,
sizeof(intel_allocate_graphics_memory));
#endif #endif
if (allocMemory.magic != INTEL_PRIVATE_DATA_MAGIC) if (allocMemory.magic != INTEL_PRIVATE_DATA_MAGIC)
@@ -274,7 +278,8 @@ device_read(void */*data*/, off_t /*pos*/, void */*buffer*/, size_t *_length)
static status_t static status_t
device_write(void */*data*/, off_t /*pos*/, const void */*buffer*/, size_t *_length) device_write(void* /*data*/, off_t /*pos*/, const void* /*buffer*/,
size_t* _length)
{ {
*_length = 0; *_length = 0;
return B_NOT_ALLOWED; return B_NOT_ALLOWED;
src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
+5 -3
View File
@@ -162,7 +162,8 @@ init_interrupt_handler(intel_info &info)
info.fake_interrupts = true; info.fake_interrupts = true;
// TODO: fake interrupts! // TODO: fake interrupts!
TRACE((DEVICE_NAME "Fake interrupt mode (no PCI interrupt line assigned)")); TRACE((DEVICE_NAME "Fake interrupt mode (no PCI interrupt line "
"assigned)"));
status = B_ERROR; status = B_ERROR;
} }
@@ -278,8 +279,9 @@ intel_extreme_init(intel_info &info)
} }
// make sure bus master, memory-mapped I/O, and frame buffer is enabled // make sure bus master, memory-mapped I/O, and frame buffer is enabled
set_pci_config(info.pci, PCI_command, 2, get_pci_config(info.pci, PCI_command, 2) set_pci_config(info.pci, PCI_command, 2, get_pci_config(info.pci,
| PCI_command_io | PCI_command_memory | PCI_command_master); PCI_command, 2) | PCI_command_io | PCI_command_memory
| PCI_command_master);
// reserve ring buffer memory (currently, this memory is placed in // reserve ring buffer memory (currently, this memory is placed in
// the graphics memory), but this could bring us problems with // the graphics memory), but this could bring us problems with