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Intel_extreme: fixed DPLL pgming (Sandy+), prevent black display by not killing PIPE (Ivy+). Chkd GMA(Q33G/Q45) OK. Added defines.

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This commit is contained in:
Rudolf Cornelissen
2021-05-29 08:41:32 +00:00
parent 5cad57c43b
commit c7d83a174c
3 changed files with 103 additions and 34 deletions
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headers/private/graphics/intel_extreme/intel_extreme.h
+77
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@@ -571,6 +571,34 @@ struct intel_free_graphics_memory {
#define INTEL_TRANSCODER_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT)
// transcoder M/N DATA AND LINK VALUES (refreshrate)
#define INTEL_TRANSCODER_A_DATA_M1 (0x0030 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_A_DATA_M2 (0x0038 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_B_DATA_M1 (0x1030 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_B_DATA_M2 (0x1038 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_C_DATA_M1 (0x2030 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_C_DATA_M2 (0x2038 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_A_DATA_N1 (0x0034 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_A_DATA_N2 (0x003c | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_B_DATA_N1 (0x1034 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_B_DATA_N2 (0x103c | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_C_DATA_N1 (0x2034 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_C_DATA_N2 (0x203c | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_A_LINK_M1 (0x0040 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_A_LINK_M2 (0x0048 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_B_LINK_M1 (0x1040 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_B_LINK_M2 (0x1048 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_C_LINK_M1 (0x2040 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_C_LINK_M2 (0x2048 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_A_LINK_N1 (0x0044 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_A_LINK_N2 (0x004c | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_B_LINK_N1 (0x1044 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_B_LINK_N2 (0x104c | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_C_LINK_N1 (0x2044 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_C_LINK_N2 (0x204c | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_MN_TU_SIZE_MASK (0x3f << 25)
#define INTEL_TRANSCODER_MN_VALUE_MASK (0xffffff << 0)
#define INTEL_TRANSCODER_A_IMAGE_SIZE (0x001c | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_TRANSCODER_B_IMAGE_SIZE (0x101c | REGS_SOUTH_TRANSCODER_PORT)
@@ -655,9 +683,14 @@ struct intel_free_graphics_memory {
#define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_B_PIPE_CONTROL (0x1008 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_C_PIPE_CONTROL (0x2008 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_A_PIPE_STATUS (0x0024 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_B_PIPE_STATUS (0x1024 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_A_PIPE_WATERMARK (0x5100 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_B_PIPE_WATERMARK (0x5104 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_C_PIPE_WATERMARK (0x5200 | REGS_NORTH_PLANE_CONTROL)
#define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17)
#define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1)
@@ -884,6 +917,14 @@ struct intel_free_graphics_memory {
#define FDI_RX_ENABLE (1 << 31)
#define FDI_RX_PLL_ENABLED (1 << 13)
// Transcoder - same base as FDI_RX
#define PCH_TRANS_CONF_A 0x0008
#define PCH_TRANS_CONF_B 0x1008
#define PCH_TRANS_CONF_C 0x2008
#define TRANS_ENABLE (1 << 31)
#define TRANS_ENABLED (1 << 30)
// FDI_tX interrupt register
#define FDI_RX_INTER_LANE_ALIGN (1 << 10)
#define FDI_RX_SYMBOL_LOCK (1 << 9)
@@ -936,6 +977,34 @@ struct intel_free_graphics_memory {
#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
//FDI PIPE M/N DATA AND LINK VALUES (refreshrate)
#define PCH_FDI_PIPE_A_DATA_M1 0x0030
#define PCH_FDI_PIPE_A_DATA_M2 0x0038
#define PCH_FDI_PIPE_B_DATA_M1 0x1030
#define PCH_FDI_PIPE_B_DATA_M2 0x1038
#define PCH_FDI_PIPE_C_DATA_M1 0x2030
#define PCH_FDI_PIPE_C_DATA_M2 0x2038
#define PCH_FDI_PIPE_A_DATA_N1 0x0034
#define PCH_FDI_PIPE_A_DATA_N2 0x003c
#define PCH_FDI_PIPE_B_DATA_N1 0x1034
#define PCH_FDI_PIPE_B_DATA_N2 0x103c
#define PCH_FDI_PIPE_C_DATA_N1 0x2034
#define PCH_FDI_PIPE_C_DATA_N2 0x203c
#define PCH_FDI_PIPE_A_LINK_M1 0x0040
#define PCH_FDI_PIPE_A_LINK_M2 0x0048
#define PCH_FDI_PIPE_B_LINK_M1 0x1040
#define PCH_FDI_PIPE_B_LINK_M2 0x1048
#define PCH_FDI_PIPE_C_LINK_M1 0x2040
#define PCH_FDI_PIPE_C_LINK_M2 0x2048
#define PCH_FDI_PIPE_A_LINK_N1 0x0044
#define PCH_FDI_PIPE_A_LINK_N2 0x004c
#define PCH_FDI_PIPE_B_LINK_N1 0x1044
#define PCH_FDI_PIPE_B_LINK_N2 0x104c
#define PCH_FDI_PIPE_C_LINK_N1 0x2044
#define PCH_FDI_PIPE_C_LINK_N2 0x204c
#define FDI_PIPE_MN_TU_SIZE_MASK (0x3f << 25)
#define FDI_PIPE_MN_VALUE_MASK (0xffffff << 0)
// SNB A stepping
#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
@@ -998,6 +1067,14 @@ struct intel_free_graphics_memory {
#define PANEL_FITTER_SCALING_MODE_MASK (7 << 26)
#define PANEL_FITTER_FILTER_MASK (3 << 24)
// panel fitters again, more directly
#define INTEL_PANELFITTER_0_CTRL (0x8080 | REGS_NORTH_PIPE_AND_PORT)
#define INTEL_PANELFITTER_1_CTRL (0x8880 | REGS_NORTH_PIPE_AND_PORT)
#define INTEL_PANELFITTER_2_CTRL (0x9080 | REGS_NORTH_PIPE_AND_PORT)
#define INTEL_PANELFITTER_0_WINDOW_SIZE (0x8074 | REGS_NORTH_PIPE_AND_PORT)
#define INTEL_PANELFITTER_1_WINDOW_SIZE (0x8874 | REGS_NORTH_PIPE_AND_PORT)
#define INTEL_PANELFITTER_2_WINDOW_SIZE (0x9074 | REGS_NORTH_PIPE_AND_PORT)
struct overlay_scale {
uint32 _reserved0 : 3;
uint32 horizontal_scale_fraction : 12;