* add initial set of Northern Island cards
* add igp property to pciid map * add disabled bios pull for r700 and ni cards * refactor model numbering as >R700 AMD switched to named card families git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42596 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
@@ -25,11 +25,16 @@
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#include <PCI.h>
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#define VENDOR_ID_ATI 0x1002
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#define VENDOR_ID_ATI 0x1002
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#define RADEON_R600 0x0600
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#define RADEON_R700 0x0700
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#define RADEON_R800 0x0800
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#define RADEON_R520 0x0520 // Fudo
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#define RADEON_R580 0x0580 // Rodin
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#define RADEON_R600 0x0600 // Pele
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#define RADEON_R700 0x0700 // Wekiva
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#define RADEON_R1000 0x1000 // Evergreen
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#define RADEON_R2000 0x2000 // Northern Islands
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#define RADEON_R3000 0x3000 // Southern Islands
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#define RADEON_R4000 0x4000 // Not yet known / used
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#define RADEON_VBIOS_SIZE 0x10000
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@@ -33,7 +33,7 @@ init_registers(register_info* regs, uint8 crtid)
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radeon_shared_info &info = *gInfo->shared_info;
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if (info.device_chipset >= RADEON_R800) {
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if (info.device_chipset >= RADEON_R1000) {
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uint32 offset = 0;
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// AMD Eyefinity on Evergreen GPUs
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@@ -89,7 +89,7 @@ init_registers(register_info* regs, uint8 crtid)
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regs->viewportSize = offset + EVERGREEN_VIEWPORT_SIZE;
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} else if (info.device_chipset >= RADEON_R600
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&& info.device_chipset < RADEON_R800) {
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&& info.device_chipset < RADEON_R1000) {
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// r600 - r700 are D1 or D2 based on primary / secondary crt
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regs->vgaControl
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@@ -39,87 +39,123 @@
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const struct supported_device {
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uint32 device_id;
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uint16 chipset;
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bool igp;
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const char* name;
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} kSupportedDevices[] = {
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// R600 series (HD24xx - HD42xx)
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// Codename: Pele
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{0x94c7, RADEON_R600 | 0x10, "Radeon HD 2350"}, /*RV610*/
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{0x94c1, RADEON_R600 | 0x10, "Radeon HD 2400"}, /*RV610, IGP*/
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{0x94c3, RADEON_R600 | 0x10, "Radeon HD 2400"}, /*RV610*/
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{0x94cc, RADEON_R600 | 0x10, "Radeon HD 2400"}, /*RV610*/
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{0x9586, RADEON_R600 | 0x30, "Radeon HD 2600"}, /*RV630*/
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{0x9588, RADEON_R600 | 0x30, "Radeon HD 2600"}, /*RV630*/
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{0x958a, RADEON_R600 | 0x30, "Radeon HD 2600 X2"},/*RV630*/
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{0x94c7, RADEON_R600 | 0x10, false, "Radeon HD 2350"},
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{0x94c1, RADEON_R600 | 0x10, true, "Radeon HD 2400"},
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{0x94c3, RADEON_R600 | 0x10, false, "Radeon HD 2400"},
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{0x94cc, RADEON_R600 | 0x10, false, "Radeon HD 2400"},
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{0x9586, RADEON_R600 | 0x30, false, "Radeon HD 2600"},
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{0x9588, RADEON_R600 | 0x30, false, "Radeon HD 2600"},
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{0x958a, RADEON_R600 | 0x30, false, "Radeon HD 2600 X2"},
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// Radeon 2700 - RV630
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{0x9400, RADEON_R600 | 0x0, "Radeon HD 2900"}, /*RV600*/
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{0x9405, RADEON_R600 | 0x0, "Radeon HD 2900"}, /*RV600*/
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{0x9611, RADEON_R600 | 0x20, "Radeon HD 3100"}, /*RV620, IGP*/
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{0x9613, RADEON_R600 | 0x20, "Radeon HD 3100"}, /*RV620, IGP*/
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{0x9610, RADEON_R600 | 0x10, "Radeon HD 3200"}, /*RV610, IGP*/
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{0x9612, RADEON_R600 | 0x10, "Radeon HD 3200"}, /*RV610, IGP*/
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{0x9615, RADEON_R600 | 0x10, "Radeon HD 3200"}, /*RV610, IGP*/
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{0x9614, RADEON_R600 | 0x10, "Radeon HD 3300"}, /*RV610, IGP*/
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{0x9400, RADEON_R600 | 0x00, false, "Radeon HD 2900"},
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{0x9405, RADEON_R600 | 0x00, false, "Radeon HD 2900"},
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{0x9611, RADEON_R600 | 0x20, true, "Radeon HD 3100"},
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{0x9613, RADEON_R600 | 0x20, true, "Radeon HD 3100"},
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{0x9610, RADEON_R600 | 0x10, true, "Radeon HD 3200"},
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{0x9612, RADEON_R600 | 0x10, true, "Radeon HD 3200"},
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{0x9615, RADEON_R600 | 0x10, true, "Radeon HD 3200"},
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{0x9614, RADEON_R600 | 0x10, true, "Radeon HD 3300"},
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// Radeon 3430 - RV620
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{0x95c5, RADEON_R600 | 0x20, "Radeon HD 3450"}, /*RV620*/
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{0x95c6, RADEON_R600 | 0x20, "Radeon HD 3450"}, /*RV620*/
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{0x95c7, RADEON_R600 | 0x20, "Radeon HD 3450"}, /*RV620*/
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{0x95c9, RADEON_R600 | 0x20, "Radeon HD 3450"}, /*RV620*/
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{0x95c4, RADEON_R600 | 0x20, "Radeon HD 3470"}, /*RV620*/
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{0x95c0, RADEON_R600 | 0x20, "Radeon HD 3550"}, /*RV620*/
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{0x9581, RADEON_R600 | 0x30, "Radeon HD 3600"}, /*RV630*/
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{0x9583, RADEON_R600 | 0x30, "Radeon HD 3600"}, /*RV630*/
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{0x9598, RADEON_R600 | 0x30, "Radeon HD 3600"}, /*RV630*/
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{0x9591, RADEON_R600 | 0x35, "Radeon HD 3600"}, /*RV635*/
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{0x9589, RADEON_R600 | 0x30, "Radeon HD 3610"}, /*RV630*/
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{0x95c5, RADEON_R600 | 0x20, false, "Radeon HD 3450"},
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{0x95c6, RADEON_R600 | 0x20, false, "Radeon HD 3450"},
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{0x95c7, RADEON_R600 | 0x20, false, "Radeon HD 3450"},
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{0x95c9, RADEON_R600 | 0x20, false, "Radeon HD 3450"},
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{0x95c4, RADEON_R600 | 0x20, false, "Radeon HD 3470"},
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{0x95c0, RADEON_R600 | 0x20, false, "Radeon HD 3550"},
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{0x9581, RADEON_R600 | 0x30, false, "Radeon HD 3600"},
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{0x9583, RADEON_R600 | 0x30, false, "Radeon HD 3600"},
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{0x9598, RADEON_R600 | 0x30, false, "Radeon HD 3600"},
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{0x9591, RADEON_R600 | 0x35, false, "Radeon HD 3600"},
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{0x9589, RADEON_R600 | 0x30, false, "Radeon HD 3610"},
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// Radeon 3650 - RV635
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// Radeon 3670 - RV635
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{0x9507, RADEON_R600 | 0x70, "Radeon HD 3830"}, /*RV670*/
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{0x9505, RADEON_R600 | 0x70, "Radeon HD 3850"}, /*RV670, IGP*/
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{0x9513, RADEON_R600 | 0x80, "Radeon HD 3850 X2"},/*RV670*/
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{0x9501, RADEON_R600 | 0x70, "Radeon HD 3870"}, /*RV670*/
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{0x950F, RADEON_R600 | 0x80, "Radeon HD 3870 X2"},/*R680*/
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{0x9710, RADEON_R600 | 0x20, "Radeon HD 4200"}, /*RV620, IGP*/
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{0x9715, RADEON_R600 | 0x20, "Radeon HD 4250"}, /*RV620, IGP*/
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{0x9712, RADEON_R600 | 0x20, "Radeon HD 4270"}, /*RV620, IGP*/
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{0x9714, RADEON_R600 | 0x20, "Radeon HD 4290"}, /*RV620, IGP*/
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{0x9507, RADEON_R600 | 0x70, false, "Radeon HD 3830"},
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{0x9505, RADEON_R600 | 0x70, false, "Radeon HD 3850"},
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{0x9513, RADEON_R600 | 0x80, false, "Radeon HD 3850 X2"},
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{0x9501, RADEON_R600 | 0x70, false, "Radeon HD 3870"},
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{0x950F, RADEON_R600 | 0x80, false, "Radeon HD 3870 X2"},
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{0x9710, RADEON_R600 | 0x20, true, "Radeon HD 4200"},
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{0x9715, RADEON_R600 | 0x20, true, "Radeon HD 4250"},
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{0x9712, RADEON_R600 | 0x20, true, "Radeon HD 4270"},
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{0x9714, RADEON_R600 | 0x20, true, "Radeon HD 4290"},
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// R700 series (HD4330 - HD4890, HD51xx, HD5xxV)
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// Codename: Wekiva
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// Radeon 4330 - RV710
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{0x954f, RADEON_R700 | 0x10, "Radeon HD 4300"}, /*RV710*/
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{0x9552, RADEON_R700 | 0x10, "Radeon HD 4300"}, /*RV710*/
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{0x9555, RADEON_R700 | 0x10, "Radeon HD 4350"}, /*RV710*/
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{0x9540, RADEON_R700 | 0x10, "Radeon HD 4550"}, /*RV710*/
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{0x9498, RADEON_R700 | 0x30, "Radeon HD 4650"}, /*RV740*/
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{0x94b4, RADEON_R700 | 0x40, "Radeon HD 4700"}, /*RV740*/
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{0x9490, RADEON_R700 | 0x30, "Radeon HD 4710"}, /*RV740*/
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{0x94b3, RADEON_R700 | 0x40, "Radeon HD 4770"}, /*RV740*/
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{0x94b5, RADEON_R700 | 0x40, "Radeon HD 4770"}, /*RV740*/
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{0x944a, RADEON_R700 | 0x70, "Radeon HD 4800"}, /*RV740*/
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{0x944e, RADEON_R700 | 0x70, "Radeon HD 4810"}, /*RV740*/
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{0x944c, RADEON_R700 | 0x70, "Radeon HD 4830"}, /*RV740*/
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{0x9442, RADEON_R700 | 0x70, "Radeon HD 4850"}, /*RV770*/
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{0x9443, RADEON_R700 | 0x70, "Radeon HD 4850 X2"},/*RV770*/
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{0x94a1, RADEON_R700 | 0x90, "Radeon HD 4860"}, /*RV780, IGP*/
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{0x9440, RADEON_R700 | 0x70, "Radeon HD 4870"}, /*RV770*/
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{0x9441, RADEON_R700 | 0x70, "Radeon HD 4870 X2"},/*RV770*/
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{0x954f, RADEON_R700 | 0x10, true, "Radeon HD 4300"},
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{0x9552, RADEON_R700 | 0x10, true, "Radeon HD 4300"},
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{0x9555, RADEON_R700 | 0x10, false, "Radeon HD 4350"},
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{0x9540, RADEON_R700 | 0x10, false, "Radeon HD 4550"},
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{0x9498, RADEON_R700 | 0x30, false, "Radeon HD 4650"},
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{0x94b4, RADEON_R700 | 0x40, false, "Radeon HD 4700"},
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{0x9490, RADEON_R700 | 0x30, false, "Radeon HD 4710"},
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{0x94b3, RADEON_R700 | 0x40, false, "Radeon HD 4770"},
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{0x94b5, RADEON_R700 | 0x40, false, "Radeon HD 4770"},
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{0x944a, RADEON_R700 | 0x70, false, "Radeon HD 4800"},
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{0x944e, RADEON_R700 | 0x70, false, "Radeon HD 4810"},
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{0x944c, RADEON_R700 | 0x70, false, "Radeon HD 4830"},
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{0x9442, RADEON_R700 | 0x70, false, "Radeon HD 4850"},
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{0x9443, RADEON_R700 | 0x70, false, "Radeon HD 4850 X2"},
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{0x94a1, RADEON_R700 | 0x90, true, "Radeon HD 4860"},
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{0x9440, RADEON_R700 | 0x70, false, "Radeon HD 4870"},
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{0x9441, RADEON_R700 | 0x70, false, "Radeon HD 4870 X2"},
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// R800 series (HD54xx - HD59xx)
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// From here on AMD no longer used numeric identifiers
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// R1000 series (HD54xx - HD59xx)
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// Codename: Evergreen
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{0x68e1, RADEON_R800 | 0x0, "Radeon HD 5430"}, /*RV8XX*/
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{0x68f9, RADEON_R800 | 0x0, "Radeon HD 5450"}, /*RV8XX*/
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{0x68e0, RADEON_R800 | 0x0, "Radeon HD 5470"}, /*RV8XX*/
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{0x68da, RADEON_R800 | 0x0, "Radeon HD 5500"}, /*RV8XX*/
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{0x68d9, RADEON_R800 | 0x0, "Radeon HD 5570"}, /*RV8XX*/
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{0x68b9, RADEON_R800 | 0x0, "Radeon HD 5600"}, /*RV8XX*/
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{0x68c1, RADEON_R800 | 0x0, "Radeon HD 5650"}, /*RV8XX*/
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{0x68d8, RADEON_R800 | 0x0, "Radeon HD 5670"}, /*RV8XX*/
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{0x68be, RADEON_R800 | 0x0, "Radeon HD 5700"}, /*RV8XX*/
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{0x68b8, RADEON_R800 | 0x0, "Radeon HD 5770"}, /*RV8XX*/
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{0x689e, RADEON_R800 | 0x0, "Radeon HD 5800"}, /*RV8XX*/
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{0x6899, RADEON_R800 | 0x0, "Radeon HD 5850"}, /*RV8XX*/
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{0x6898, RADEON_R800 | 0x0, "Radeon HD 5870"}, /*RV8XX*/
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{0x689c, RADEON_R800 | 0x0, "Radeon HD 5900"} /*RV8XX*/
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// Cedar
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{0x68e1, RADEON_R1000 | 0x00, false, "Radeon HD 5430"},
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{0x68f9, RADEON_R1000 | 0x00, false, "Radeon HD 5450"},
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{0x68e0, RADEON_R1000 | 0x00, true, "Radeon HD 5470"},
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// Redwood
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{0x68da, RADEON_R1000 | 0x10, false, "Radeon HD 5500"},
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{0x68d9, RADEON_R1000 | 0x10, false, "Radeon HD 5570"},
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{0x68b9, RADEON_R1000 | 0x10, false, "Radeon HD 5600"},
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{0x68c1, RADEON_R1000 | 0x10, false, "Radeon HD 5650"},
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{0x68d8, RADEON_R1000 | 0x10, false, "Radeon HD 5670"},
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// Juniper
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{0x68be, RADEON_R1000 | 0x20, false, "Radeon HD 5700"},
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{0x68b8, RADEON_R1000 | 0x20, false, "Radeon HD 5770"},
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// Cypress
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{0x689e, RADEON_R1000 | 0x30, false, "Radeon HD 5800"},
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{0x6899, RADEON_R1000 | 0x30, false, "Radeon HD 5850"},
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{0x6898, RADEON_R1000 | 0x30, false, "Radeon HD 5870"},
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// Hemlock
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{0x689c, RADEON_R1000 | 0x40, false, "Radeon HD 5900"},
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// R2000 series (HD64xx - HD69xx)
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// Codename: Nothern Islands
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// Caicos
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{0x6770, RADEON_R2000 | 0x00, true, "Radeon HD 6400"},
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{0x6779, RADEON_R2000 | 0x00, false, "Radeon HD 6450"},
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// Turks
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{0x6759, RADEON_R2000 | 0x10, false, "Radeon HD 6570"},
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{0x6741, RADEON_R2000 | 0x10, true, "Radeon HD 6650M"},
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// Barts
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{0x673e, RADEON_R2000 | 0x20, false, "Radeon HD 6790"},
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{0x6739, RADEON_R2000 | 0x20, false, "Radeon HD 6850"},
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{0x6738, RADEON_R2000 | 0x20, false, "Radeon HD 6870"},
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// Cayman
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{0x6718, RADEON_R2000 | 0x30, false, "Radeon HD 6970"},
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// Antilles
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{0x671d, RADEON_R2000 | 0x40, false, "Radeon HD 6990"}
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// R3000 series (HD74xx - HD79xx)
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// Codename: Southern Islands
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// Lombok
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// R3000 | 0x00
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// Thames
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// R3000 | 0x10
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// Tahiti
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// R3000 | 0x20
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// New Zealand
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// R3000 | 0x30
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};
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@@ -155,6 +155,89 @@ radeon_hd_getbios(radeon_info &info)
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}
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status_t
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radeon_hd_getbios_ni(radeon_info &info)
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{
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TRACE("card(%ld): %s: called\n", info.id, __func__);
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uint32 bus_cntl = read32(info.registers + R600_BUS_CNTL);
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uint32 d1vga_control = read32(info.registers + AVIVO_D1VGA_CONTROL);
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uint32 d2vga_control = read32(info.registers + AVIVO_D2VGA_CONTROL);
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uint32 vga_render_control
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= read32(info.registers + AVIVO_VGA_RENDER_CONTROL);
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uint32 rom_cntl = read32(info.registers + R600_ROM_CNTL);
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// enable the rom
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write32(info.registers + R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
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// disable VGA mode
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write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control
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& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
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| AVIVO_DVGA_CONTROL_TIMING_SELECT)));
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write32(info.registers + D2VGA_CONTROL, (d2vga_control
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& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
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| AVIVO_DVGA_CONTROL_TIMING_SELECT)));
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write32(info.registers + AVIVO_VGA_RENDER_CONTROL,
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(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
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write32(info.registers + R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
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// try to grab the bios
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status_t result = radeon_hd_getbios(info);
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// restore regs
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write32(info.registers + R600_BUS_CNTL, bus_cntl);
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write32(info.registers + AVIVO_D1VGA_CONTROL, d1vga_control);
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write32(info.registers + AVIVO_D2VGA_CONTROL, d2vga_control);
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write32(info.registers + AVIVO_VGA_RENDER_CONTROL, vga_render_control);
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write32(info.registers + R600_ROM_CNTL, rom_cntl);
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return result;
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}
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status_t
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radeon_hd_getbios_r700(radeon_info &info)
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{
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TRACE("card(%ld): %s: called\n", info.id, __func__);
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uint32 viph_control = read32(info.registers + RADEON_VIPH_CONTROL);
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uint32 bus_cntl = read32(info.registers + R600_BUS_CNTL);
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uint32 d1vga_control = read32(info.registers + AVIVO_D1VGA_CONTROL);
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uint32 d2vga_control = read32(info.registers + AVIVO_D2VGA_CONTROL);
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uint32 vga_render_control
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= read32(info.registers + AVIVO_VGA_RENDER_CONTROL);
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uint32 rom_cntl = read32(info.registers + R600_ROM_CNTL);
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// disable VIP
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write32(info.registers + RADEON_VIPH_CONTROL,
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(viph_control & ~RADEON_VIPH_EN));
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// enable the rom
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write32(info.registers + R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
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// disable VGA mode
|
||||
write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control
|
||||
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
||||
| AVIVO_DVGA_CONTROL_TIMING_SELECT)));
|
||||
write32(info.registers + D2VGA_CONTROL, (d2vga_control
|
||||
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
||||
| AVIVO_DVGA_CONTROL_TIMING_SELECT)));
|
||||
write32(info.registers + AVIVO_VGA_RENDER_CONTROL,
|
||||
(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
|
||||
|
||||
write32(info.registers + R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
|
||||
|
||||
// try to grab the bios
|
||||
status_t result = radeon_hd_getbios(info);
|
||||
|
||||
// restore regs
|
||||
write32(info.registers + RADEON_VIPH_CONTROL, viph_control);
|
||||
write32(info.registers + R600_BUS_CNTL, bus_cntl);
|
||||
write32(info.registers + AVIVO_D1VGA_CONTROL, d1vga_control);
|
||||
write32(info.registers + AVIVO_D2VGA_CONTROL, d2vga_control);
|
||||
write32(info.registers + AVIVO_VGA_RENDER_CONTROL, vga_render_control);
|
||||
write32(info.registers + R600_ROM_CNTL, rom_cntl);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
status_t
|
||||
radeon_hd_getbios_r600(radeon_info &info)
|
||||
{
|
||||
@@ -304,7 +387,13 @@ radeon_hd_init(radeon_info &info)
|
||||
status_t biosStatus = radeon_hd_getbios(info);
|
||||
if (biosStatus != B_OK) {
|
||||
// If the active read fails, we do a disabled read
|
||||
if (info.device_chipset > RADEON_R600)
|
||||
|
||||
// TODO : IGP read
|
||||
if (info.device_chipset >= (RADEON_R1000 | 0x20))
|
||||
biosStatus = radeon_hd_getbios_ni(info);
|
||||
else if (info.device_chipset >= (RADEON_R700 | 0x70))
|
||||
biosStatus = radeon_hd_getbios_r700(info);
|
||||
else if (info.device_chipset >= RADEON_R600)
|
||||
biosStatus = radeon_hd_getbios_r600(info);
|
||||
}
|
||||
|
||||
@@ -330,7 +419,7 @@ radeon_hd_init(radeon_info &info)
|
||||
}
|
||||
|
||||
// *** Populate graphics_memory/aperture_size with KB
|
||||
if (info.shared_info->device_chipset >= RADEON_R800) {
|
||||
if (info.shared_info->device_chipset >= RADEON_R1000) {
|
||||
// R800+ has memory stored in MB
|
||||
info.shared_info->graphics_memory_size
|
||||
= read32(info.registers + R6XX_CONFIG_MEMSIZE) * 1024;
|
||||
|
||||
Reference in New Issue
Block a user