updated mii, msk to freebsd current
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@31018 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Jérôme Duval
@@ -14,3 +14,6 @@ KernelStaticLibrary marvell_yukon_mii.a
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ukphy_subr.c
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;
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ObjectHdrs [ FGristFiles e1000phy$(SUFOBJ) ]
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: [ FDirName $(TARGET_COMMON_DEBUG_OBJECT_DIR) libs compat freebsd_network ] ;
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Includes [ FGristFiles e1000phy.c ] : <src!libs!compat!freebsd_network>miidevs.h ;
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@@ -30,7 +30,7 @@
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD: src/sys/dev/mii/e1000phy.c,v 1.18 2006/12/11 11:09:48 yongari Exp $");
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__FBSDID("$FreeBSD$");
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/*
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* driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
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@@ -105,7 +105,9 @@ static const struct mii_phydesc e1000phys[] = {
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MII_PHY_DESC(MARVELL, E1149),
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MII_PHY_DESC(MARVELL, E1111),
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MII_PHY_DESC(MARVELL, E1116),
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MII_PHY_DESC(MARVELL, E1116R),
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MII_PHY_DESC(MARVELL, E1118),
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MII_PHY_DESC(MARVELL, E3016),
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MII_PHY_DESC(xxMARVELL, E1000),
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MII_PHY_DESC(xxMARVELL, E1011),
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MII_PHY_DESC(xxMARVELL, E1000_3),
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@@ -128,7 +130,6 @@ e1000phy_attach(device_t dev)
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struct mii_softc *sc;
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struct mii_attach_args *ma;
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struct mii_data *mii;
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int fast_ether;
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esc = device_get_softc(dev);
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sc = &esc->mii_sc;
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@@ -141,10 +142,8 @@ e1000phy_attach(device_t dev)
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sc->mii_phy = ma->mii_phyno;
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sc->mii_service = e1000phy_service;
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sc->mii_pdata = mii;
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sc->mii_anegticks = MII_ANEGTICKS_GIGE;
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mii->mii_instance++;
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fast_ether = 0;
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esc->mii_model = MII_MODEL(ma->mii_id2);
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switch (esc->mii_model) {
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case MII_MODEL_MARVELL_E1011:
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@@ -152,54 +151,30 @@ e1000phy_attach(device_t dev)
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if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK)
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sc->mii_flags |= MIIF_HAVEFIBER;
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break;
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case MII_MODEL_MARVELL_E3082:
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/* 88E3082 10/100 Fast Ethernet PHY. */
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sc->mii_anegticks = MII_ANEGTICKS;
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fast_ether = 1;
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case MII_MODEL_MARVELL_E1149:
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/*
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* Some 88E1149 PHY's page select is initialized to
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* point to other bank instead of copper/fiber bank
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* which in turn resulted in wrong registers were
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* accessed during PHY operation. It is believed that
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* page 0 should be used for copper PHY so reinitialize
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* E1000_EADR to select default copper PHY. If parent
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* device know the type of PHY(either copper or fiber),
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* that information should be used to select default
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* type of PHY.
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*/
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PHY_WRITE(sc, E1000_EADR, 0);
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break;
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}
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e1000phy_reset(sc);
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sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
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if (sc->mii_capabilities & BMSR_EXTSTAT)
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sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
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device_printf(dev, " ");
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#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
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E1000_CR_ISOLATE);
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if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst),
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E1000_CR_SPEED_10);
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printf("10baseT, ");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
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E1000_CR_SPEED_10 | E1000_CR_FULL_DUPLEX);
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printf("10baseT-FDX, ");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst),
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E1000_CR_SPEED_100);
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printf("100baseTX, ");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
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E1000_CR_SPEED_100 | E1000_CR_FULL_DUPLEX);
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printf("100baseTX-FDX, ");
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if (fast_ether == 0) {
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/*
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* 1000BT-simplex not supported; driver must ignore
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* this entry, but it must be present in order to
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* manually set full-duplex.
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*/
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0,
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sc->mii_inst), E1000_CR_SPEED_1000);
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX,
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sc->mii_inst),
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E1000_CR_SPEED_1000 | E1000_CR_FULL_DUPLEX);
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printf("1000baseTX-FDX, ");
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}
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} else {
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
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E1000_CR_SPEED_1000 | E1000_CR_FULL_DUPLEX);
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printf("1000baseSX-FDX, ");
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}
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
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printf("auto\n");
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#undef ADD
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mii_phy_add_media(sc);
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printf("\n");
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MIIBUS_MEDIAINIT(sc->mii_dev);
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return (0);
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@@ -209,7 +184,7 @@ static void
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e1000phy_reset(struct mii_softc *sc)
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{
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struct e1000phy_softc *esc;
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uint16_t reg;
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uint16_t reg, page;
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esc = (struct e1000phy_softc *)sc;
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reg = PHY_READ(sc, E1000_SCR);
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@@ -218,12 +193,13 @@ e1000phy_reset(struct mii_softc *sc)
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PHY_WRITE(sc, E1000_SCR, reg);
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if (esc->mii_model == MII_MODEL_MARVELL_E1112) {
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/* Select 1000BASE-X only mode. */
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page = PHY_READ(sc, E1000_EADR);
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PHY_WRITE(sc, E1000_EADR, 2);
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reg = PHY_READ(sc, E1000_SCR);
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reg &= ~E1000_SCR_MODE_MASK;
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reg |= E1000_SCR_MODE_1000BX;
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PHY_WRITE(sc, E1000_SCR, reg);
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PHY_WRITE(sc, E1000_EADR, 1);
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PHY_WRITE(sc, E1000_EADR, page);
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}
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} else {
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switch (esc->mii_model) {
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@@ -235,27 +211,71 @@ e1000phy_reset(struct mii_softc *sc)
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/* Disable energy detect mode. */
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reg &= ~E1000_SCR_EN_DETECT_MASK;
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reg |= E1000_SCR_AUTO_X_MODE;
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if (esc->mii_model == MII_MODEL_MARVELL_E1116)
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reg &= ~E1000_SCR_POWER_DOWN;
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reg |= E1000_SCR_ASSERT_CRS_ON_TX;
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break;
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case MII_MODEL_MARVELL_E3082:
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reg |= (E1000_SCR_AUTO_X_MODE >> 1);
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reg |= E1000_SCR_ASSERT_CRS_ON_TX;
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break;
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case MII_MODEL_MARVELL_E3016:
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reg |= E1000_SCR_AUTO_MDIX;
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reg &= ~(E1000_SCR_EN_DETECT |
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E1000_SCR_SCRAMBLER_DISABLE);
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reg |= E1000_SCR_LPNP;
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/* XXX Enable class A driver for Yukon FE+ A0. */
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PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001);
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break;
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default:
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reg &= ~E1000_SCR_AUTO_X_MODE;
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reg |= E1000_SCR_ASSERT_CRS_ON_TX;
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break;
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}
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/* Enable CRS on TX. */
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reg |= E1000_SCR_ASSERT_CRS_ON_TX;
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/* Auto correction for reversed cable polarity. */
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reg &= ~E1000_SCR_POLARITY_REVERSAL;
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if (esc->mii_model != MII_MODEL_MARVELL_E3016) {
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/* Auto correction for reversed cable polarity. */
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reg &= ~E1000_SCR_POLARITY_REVERSAL;
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}
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PHY_WRITE(sc, E1000_SCR, reg);
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if (esc->mii_model == MII_MODEL_MARVELL_E1116 ||
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esc->mii_model == MII_MODEL_MARVELL_E1149) {
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page = PHY_READ(sc, E1000_EADR);
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/* Select page 2, MAC specific control register. */
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PHY_WRITE(sc, E1000_EADR, 2);
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reg = PHY_READ(sc, E1000_SCR);
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reg |= E1000_SCR_RGMII_POWER_UP;
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PHY_WRITE(sc, E1000_SCR, reg);
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PHY_WRITE(sc, E1000_EADR, page);
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}
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}
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switch (MII_MODEL(esc->mii_model)) {
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case MII_MODEL_MARVELL_E3082:
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case MII_MODEL_MARVELL_E1112:
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case MII_MODEL_MARVELL_E1116:
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case MII_MODEL_MARVELL_E1118:
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break;
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case MII_MODEL_MARVELL_E1116:
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case MII_MODEL_MARVELL_E1149:
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page = PHY_READ(sc, E1000_EADR);
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/* Select page 3, LED control register. */
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PHY_WRITE(sc, E1000_EADR, 3);
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PHY_WRITE(sc, E1000_SCR,
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E1000_SCR_LED_LOS(1) | /* Link/Act */
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E1000_SCR_LED_INIT(8) | /* 10Mbps */
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E1000_SCR_LED_STAT1(7) | /* 100Mbps */
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E1000_SCR_LED_STAT0(7)); /* 1000Mbps */
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/* Set blink rate. */
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PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) |
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E1000_BLINK_RATE(E1000_BLINK_84MS));
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PHY_WRITE(sc, E1000_EADR, page);
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break;
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case MII_MODEL_MARVELL_E3016:
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/* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */
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PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04);
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/* Integrated register calibration workaround. */
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PHY_WRITE(sc, 0x1D, 17);
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PHY_WRITE(sc, 0x1E, 0x3F60);
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break;
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default:
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/* Force TX_CLK to 25MHz clock. */
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@@ -313,12 +333,14 @@ e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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speed = 0;
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_1000_T:
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if (esc->mii_model == MII_MODEL_MARVELL_E3082)
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if ((sc->mii_extcapabilities &
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(EXTSR_1000TFDX | EXTSR_1000THDX)) == 0)
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return (EINVAL);
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speed = E1000_CR_SPEED_1000;
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break;
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case IFM_1000_SX:
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if (esc->mii_model == MII_MODEL_MARVELL_E3082)
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if ((sc->mii_extcapabilities &
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(EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0)
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return (EINVAL);
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speed = E1000_CR_SPEED_1000;
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break;
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@@ -364,7 +386,8 @@ e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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PHY_WRITE(sc, E1000_1GCR, gig |
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E1000_1GCR_MS_ENABLE);
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} else {
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if (esc->mii_model != MII_MODEL_MARVELL_E3082)
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if ((sc->mii_extcapabilities &
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(EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
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PHY_WRITE(sc, E1000_1GCR, 0);
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}
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PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD);
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@@ -387,8 +410,10 @@ done:
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/*
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* Only used for autonegotiation.
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*/
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
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sc->mii_ticks = 0;
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break;
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}
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/*
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* check for link.
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@@ -401,8 +426,10 @@ done:
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}
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/* Announce link loss right after it happens. */
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if (sc->mii_ticks++ == 0)
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break;
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if (sc->mii_ticks <= sc->mii_anegticks)
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return (0);
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break;
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sc->mii_ticks = 0;
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e1000phy_reset(sc);
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@@ -422,18 +449,14 @@ static void
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e1000phy_status(struct mii_softc *sc)
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{
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struct mii_data *mii = sc->mii_pdata;
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int bmsr, bmcr, esr, gsr, ssr, isr, ar, lpar;
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int bmcr, bmsr, gsr, ssr, ar, lpar;
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR);
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esr = PHY_READ(sc, E1000_ESR);
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bmcr = PHY_READ(sc, E1000_CR);
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ssr = PHY_READ(sc, E1000_SSR);
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isr = PHY_READ(sc, E1000_ISR);
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ar = PHY_READ(sc, E1000_AR);
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lpar = PHY_READ(sc, E1000_LPAR);
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if (bmsr & E1000_SR_LINK_STATUS)
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mii->mii_media_status |= IFM_ACTIVE;
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@@ -441,22 +464,28 @@ e1000phy_status(struct mii_softc *sc)
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if (bmcr & E1000_CR_LOOPBACK)
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mii->mii_media_active |= IFM_LOOP;
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if ((((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0) &&
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((bmsr & E1000_SR_AUTO_NEG_COMPLETE) == 0)) ||
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((ssr & E1000_SSR_LINK) == 0) ||
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((ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0)) {
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if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 &&
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(ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) {
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/* Erg, still trying, I guess... */
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
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if (ssr & E1000_SSR_1000MBS)
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switch (ssr & E1000_SSR_SPEED) {
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case E1000_SSR_1000MBS:
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mii->mii_media_active |= IFM_1000_T;
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else if (ssr & E1000_SSR_100MBS)
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break;
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case E1000_SSR_100MBS:
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mii->mii_media_active |= IFM_100_TX;
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else
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break;
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case E1000_SSR_10MBS:
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mii->mii_media_active |= IFM_10_T;
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break;
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default:
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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} else {
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if (ssr & E1000_SSR_1000MBS)
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mii->mii_media_active |= IFM_1000_SX;
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@@ -468,6 +497,8 @@ e1000phy_status(struct mii_softc *sc)
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mii->mii_media_active |= IFM_HDX;
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if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
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ar = PHY_READ(sc, E1000_AR);
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lpar = PHY_READ(sc, E1000_LPAR);
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/* FLAG0==rx-flow-control FLAG1==tx-flow-control */
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if ((ar & E1000_AR_PAUSE) && (lpar & E1000_LPAR_PAUSE)) {
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mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1;
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@@ -494,16 +525,19 @@ static int
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e1000phy_mii_phy_auto(struct e1000phy_softc *esc)
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{
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struct mii_softc *sc;
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uint16_t reg;
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sc = &esc->mii_sc;
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if ((sc->mii_flags & MIIF_HAVEFIBER) == 0)
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PHY_WRITE(sc, E1000_AR, E1000_AR_10T | E1000_AR_10T_FD |
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if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
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reg = PHY_READ(sc, E1000_AR);
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reg |= E1000_AR_10T | E1000_AR_10T_FD |
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E1000_AR_100TX | E1000_AR_100TX_FD |
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E1000_AR_PAUSE | E1000_AR_ASM_DIR);
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else
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E1000_AR_PAUSE | E1000_AR_ASM_DIR;
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PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD);
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} else
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PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X |
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E1000_FA_SYM_PAUSE | E1000_FA_ASYM_PAUSE);
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if (esc->mii_model != MII_MODEL_MARVELL_E3082)
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if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
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PHY_WRITE(sc, E1000_1GCR,
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E1000_1GCR_1000T_FD | E1000_1GCR_1000T);
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PHY_WRITE(sc, E1000_CR,
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@@ -1,4 +1,4 @@
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/* $FreeBSD: src/sys/dev/mii/e1000phyreg.h,v 1.4 2006/12/11 10:43:32 yongari Exp $ */
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/* $FreeBSD$ */
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/*-
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* Principal Author: Parag Patel
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* Copyright (c) 2001
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@@ -236,6 +236,16 @@
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#define E1000_SCR_TX_FIFO_DEPTH_10 0x8000
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#define E1000_SCR_TX_FIFO_DEPTH_12 0xC000
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||||
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/* 88E3016 only */
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||||
#define E1000_SCR_AUTO_MDIX 0x0030
|
||||
#define E1000_SCR_SIGDET_POLARITY 0x0040
|
||||
#define E1000_SCR_EXT_DISTANCE 0x0080
|
||||
#define E1000_SCR_FEFI_DISABLE 0x0100
|
||||
#define E1000_SCR_NLP_GEN_DISABLE 0x0800
|
||||
#define E1000_SCR_LPNP 0x1000
|
||||
#define E1000_SCR_NLP_CHK_DISABLE 0x2000
|
||||
#define E1000_SCR_EN_DETECT 0x4000
|
||||
|
||||
#define E1000_SCR_EN_DETECT_MASK 0x0300
|
||||
|
||||
/* 88E1112 page 2 */
|
||||
@@ -244,6 +254,21 @@
|
||||
#define E1000_SCR_MODE_COPPER 0x0280
|
||||
#define E1000_SCR_MODE_1000BX 0x0380
|
||||
|
||||
/* 88E1116 page 0 */
|
||||
#define E1000_SCR_POWER_DOWN 0x0004
|
||||
/* 88E1116, 88E1149 page 2 */
|
||||
#define E1000_SCR_RGMII_POWER_UP 0x0008
|
||||
|
||||
/* 88E1116, 88E1149 page 3 */
|
||||
#define E1000_SCR_LED_STAT0_MASK 0x000F
|
||||
#define E1000_SCR_LED_STAT1_MASK 0x00F0
|
||||
#define E1000_SCR_LED_INIT_MASK 0x0F00
|
||||
#define E1000_SCR_LED_LOS_MASK 0xF000
|
||||
#define E1000_SCR_LED_STAT0(x) ((x) & E1000_SCR_LED_STAT0_MASK)
|
||||
#define E1000_SCR_LED_STAT1(x) ((x) & E1000_SCR_LED_STAT1_MASK)
|
||||
#define E1000_SCR_LED_INIT(x) ((x) & E1000_SCR_LED_INIT_MASK)
|
||||
#define E1000_SCR_LED_LOS(x) ((x) & E1000_SCR_LED_LOS_MASK)
|
||||
|
||||
#define E1000_SSR 0x11 /* special status register */
|
||||
#define E1000_SSR_JABBER 0x0001
|
||||
#define E1000_SSR_REV_POLARITY 0x0002
|
||||
@@ -271,6 +296,26 @@
|
||||
#define E1000_IER_SPEED_CHANGED 0x4000
|
||||
#define E1000_IER_AUTO_NEG_ERR 0x8000
|
||||
|
||||
/* 88E1116, 88E1149 page 3, LED timer control. */
|
||||
#define E1000_PULSE_MASK 0x7000
|
||||
#define E1000_PULSE_NO_STR 0 /* no pulse stretching */
|
||||
#define E1000_PULSE_21MS 1 /* 21 ms to 42 ms */
|
||||
#define E1000_PULSE_42MS 2 /* 42 ms to 84 ms */
|
||||
#define E1000_PULSE_84MS 3 /* 84 ms to 170 ms */
|
||||
#define E1000_PULSE_170MS 4 /* 170 ms to 340 ms */
|
||||
#define E1000_PULSE_340MS 5 /* 340 ms to 670 ms */
|
||||
#define E1000_PULSE_670MS 6 /* 670 ms to 1300 ms */
|
||||
#define E1000_PULSE_1300MS 7 /* 1300 ms to 2700 ms */
|
||||
#define E1000_PULSE_DUR(x) ((x) & E1000_PULSE_MASK)
|
||||
|
||||
#define E1000_BLINK_MASK 0x0700
|
||||
#define E1000_BLINK_42MS 0 /* 42 ms */
|
||||
#define E1000_BLINK_84MS 1 /* 84 ms */
|
||||
#define E1000_BLINK_170MS 2 /* 170 ms */
|
||||
#define E1000_BLINK_340MS 3 /* 340 ms */
|
||||
#define E1000_BLINK_670MS 4 /* 670 ms */
|
||||
#define E1000_BLINK_RATE(x) ((x) & E1000_BLINK_MASK)
|
||||
|
||||
#define E1000_ISR 0x13 /* interrupt status reg */
|
||||
#define E1000_ISR_JABBER 0x0001
|
||||
#define E1000_ISR_POLARITY_CHANGE 0x0002
|
||||
|
||||
@@ -1,40 +0,0 @@
|
||||
#define MII_OUI_MARVELL 0x005043
|
||||
#define MII_OUI_xxMARVELL 0x000ac2
|
||||
|
||||
#define MII_MODEL_MARVELL_E1000 0x0000
|
||||
#define MII_MODEL_MARVELL_E1011 0x0002
|
||||
#define MII_MODEL_MARVELL_E1000_3 0x0003
|
||||
#define MII_MODEL_MARVELL_E1000S 0x0004
|
||||
#define MII_MODEL_MARVELL_E1000_5 0x0005
|
||||
#define MII_MODEL_MARVELL_E1000_6 0x0006
|
||||
#define MII_MODEL_MARVELL_E3082 0x0008
|
||||
#define MII_MODEL_MARVELL_E1112 0x0009
|
||||
#define MII_MODEL_MARVELL_E1149 0x000b
|
||||
#define MII_MODEL_MARVELL_E1111 0x000c
|
||||
#define MII_MODEL_MARVELL_E1116 0x0021
|
||||
#define MII_MODEL_MARVELL_E1118 0x0022
|
||||
|
||||
#define MII_MODEL_xxMARVELL_E1000 0x0005
|
||||
#define MII_MODEL_xxMARVELL_E1011 0x0002
|
||||
#define MII_MODEL_xxMARVELL_E1000_3 0x0003
|
||||
#define MII_MODEL_xxMARVELL_E1000_5 0x0005
|
||||
#define MII_MODEL_xxMARVELL_E1111 0x000c
|
||||
|
||||
#define MII_STR_MARVELL_E1000 "Marvell 88E1000 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1011 "Marvell 88E1011 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1000S "Marvell 88E1000S Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1000_6 "Marvell 88E1000 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E3082 "Marvell 88E3082 10/100 Fast Ethernet PHY"
|
||||
#define MII_STR_MARVELL_E1112 "Marvell 88E1112 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1149 "Marvell 88E1149 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1116 "Marvell 88E1116 Gigabit PHY"
|
||||
#define MII_STR_MARVELL_E1118 "Marvell 88E1118 Gigabit PHY"
|
||||
|
||||
#define MII_STR_xxMARVELL_E1000 "Marvell 88E1000 Gigabit PHY"
|
||||
#define MII_STR_xxMARVELL_E1011 "Marvell 88E1011 Gigabit PHY"
|
||||
#define MII_STR_xxMARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY"
|
||||
#define MII_STR_xxMARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY"
|
||||
#define MII_STR_xxMARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
|
||||
@@ -67,7 +67,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy.c,v 1.20 2007/01/20 00:52:29 marius Exp $");
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
/*
|
||||
* driver for generic unknown PHYs
|
||||
|
||||
@@ -38,7 +38,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy_subr.c,v 1.8.8.1 2006/07/19 04:40:26 yongari Exp $");
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
/*
|
||||
* Subroutines shared by the ukphy driver and other PHY drivers.
|
||||
@@ -112,10 +112,10 @@ ukphy_status(struct mii_softc *phy)
|
||||
else if ((gtcr & GTCR_ADV_1000THDX) &&
|
||||
(gtsr & GTSR_LP_1000THDX))
|
||||
mii->mii_media_active |= IFM_1000_T;
|
||||
else if (anlpar & ANLPAR_T4)
|
||||
mii->mii_media_active |= IFM_100_T4;
|
||||
else if (anlpar & ANLPAR_TX_FD)
|
||||
mii->mii_media_active |= IFM_100_TX|IFM_FDX;
|
||||
else if (anlpar & ANLPAR_T4)
|
||||
mii->mii_media_active |= IFM_100_T4;
|
||||
else if (anlpar & ANLPAR_TX)
|
||||
mii->mii_media_active |= IFM_100_TX;
|
||||
else if (anlpar & ANLPAR_10_FD)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -93,7 +93,7 @@
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*$FreeBSD: src/sys/dev/msk/if_mskreg.h,v 1.11 2007/12/05 09:41:58 remko Exp $*/
|
||||
/*$FreeBSD$*/
|
||||
|
||||
/*
|
||||
* SysKonnect PCI vendor ID
|
||||
@@ -130,13 +130,19 @@
|
||||
#define DEVICEID_MRVL_8035 0x4350
|
||||
#define DEVICEID_MRVL_8036 0x4351
|
||||
#define DEVICEID_MRVL_8038 0x4352
|
||||
#define DEVICEID_MRVL_8039 0X4353
|
||||
#define DEVICEID_MRVL_8039 0x4353
|
||||
#define DEVICEID_MRVL_8040 0x4354
|
||||
#define DEVICEID_MRVL_8040T 0x4355
|
||||
#define DEVICEID_MRVL_8048 0x435A
|
||||
#define DEVICEID_MRVL_4360 0x4360
|
||||
#define DEVICEID_MRVL_4361 0x4361
|
||||
#define DEVICEID_MRVL_4362 0x4362
|
||||
#define DEVICEID_MRVL_4363 0x4363
|
||||
#define DEVICEID_MRVL_4364 0x4364
|
||||
#define DEVICEID_MRVL_4365 0x4365
|
||||
#define DEVICEID_MRVL_436A 0x436A
|
||||
#define DEVICEID_MRVL_436B 0x436B
|
||||
#define DEVICEID_MRVL_436C 0x436C
|
||||
|
||||
/*
|
||||
* D-Link gigabit ethernet device ID
|
||||
@@ -221,6 +227,8 @@
|
||||
#define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */
|
||||
#define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */
|
||||
#define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */
|
||||
#define PCI_CFG_REG_0 0x90 /* 32 bit Config Register 0 */
|
||||
#define PCI_CFG_REG_1 0x94 /* 32 bit Config Register 1 */
|
||||
|
||||
/* PCI Express Capability */
|
||||
#define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */
|
||||
@@ -321,6 +329,56 @@
|
||||
#define PCI_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */
|
||||
#define PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */
|
||||
|
||||
/* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
|
||||
/* Bit 31..27: for A3 & later */
|
||||
#define PCI_CTL_DIV_CORE_CLK_ENA BIT_31 /* Divide Core Clock Enable */
|
||||
#define PCI_CTL_SRESET_VMAIN_AV BIT_30 /* Soft Reset for Vmain_av De-Glitch */
|
||||
#define PCI_CTL_BYPASS_VMAIN_AV BIT_29 /* Bypass En. for Vmain_av De-Glitch */
|
||||
#define PCI_CTL_TIM_VMAIN_AV1 BIT_28 /* Bit 28..27: Timer Vmain_av Mask */
|
||||
#define PCI_CTL_TIM_VMAIN_AV0 BIT_27 /* Bit 28..27: Timer Vmain_av Mask */
|
||||
#define PCI_CTL_TIM_VMAIN_AV_MSK (BIT_28 | BIT_27)
|
||||
/* Bit 26..16: Release Clock on Event */
|
||||
#define PCI_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */
|
||||
#define PCI_REL_GPHY_REC_PACKET BIT_25 /* GPHY Received Packet */
|
||||
#define PCI_REL_INT_FIFO_N_EMPTY BIT_24 /* Internal FIFO Not Empty */
|
||||
#define PCI_REL_MAIN_PWR_AVAIL BIT_23 /* Main Power Available */
|
||||
#define PCI_REL_CLKRUN_REQ_REL BIT_22 /* CLKRUN Request Release */
|
||||
#define PCI_REL_PCIE_RESET_ASS BIT_21 /* PCIe Reset Asserted */
|
||||
#define PCI_REL_PME_ASSERTED BIT_20 /* PME Asserted */
|
||||
#define PCI_REL_PCIE_EXIT_L1_ST BIT_19 /* PCIe Exit L1 State */
|
||||
#define PCI_REL_LOADER_NOT_FIN BIT_18 /* EPROM Loader Not Finished */
|
||||
#define PCI_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */
|
||||
#define PCI_REL_GPHY_LINK_UP BIT_16 /* GPHY Link Up */
|
||||
/* Bit 10.. 0: Mask for Gate Clock */
|
||||
#define PCI_GAT_PCIE_RST_ASSERTED BIT_10 /* PCIe Reset Asserted */
|
||||
#define PCI_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */
|
||||
#define PCI_GAT_INT_FIFO_EMPTY BIT_8 /* Internal FIFO Empty */
|
||||
#define PCI_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */
|
||||
#define PCI_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */
|
||||
#define PCI_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */
|
||||
#define PCI_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */
|
||||
#define PCI_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */
|
||||
#define PCI_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */
|
||||
#define PCI_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */
|
||||
#define PCI_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */
|
||||
|
||||
/* PCI_CFG_REG_1 32 bit Config Register 1 */
|
||||
#define PCI_CF1_DIS_REL_EVT_RST BIT_24 /* Dis. Rel. Event during PCIE reset */
|
||||
/* Bit 23..21: Release Clock on Event */
|
||||
#define PCI_CF1_REL_LDR_NOT_FIN BIT_23 /* EEPROM Loader Not Finished */
|
||||
#define PCI_CF1_REL_VMAIN_AVLBL BIT_22 /* Vmain available */
|
||||
#define PCI_CF1_REL_PCIE_RESET BIT_21 /* PCI-E reset */
|
||||
/* Bit 20..18: Gate Clock on Event */
|
||||
#define PCI_CF1_GAT_LDR_NOT_FIN BIT_20 /* EEPROM Loader Finished */
|
||||
#define PCI_CF1_GAT_PCIE_RX_IDLE BIT_19 /* PCI-E Rx Electrical idle */
|
||||
#define PCI_CF1_GAT_PCIE_RESET BIT_18 /* PCI-E Reset */
|
||||
#define PCI_CF1_PRST_PHY_CLKREQ BIT_17 /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
|
||||
#define PCI_CF1_PCIE_RST_CLKREQ BIT_16 /* Enable PCI-E rst generate CLKREQ */
|
||||
|
||||
#define PCI_CF1_ENA_CFG_LDR_DONE BIT_8 /* Enable core level Config loader done */
|
||||
#define PCI_CF1_ENA_TXBMU_RD_IDLE BIT_1 /* Enable TX BMU Read IDLE for ASPM */
|
||||
#define PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0 /* Enable TX BMU Write IDLE for ASPM */
|
||||
|
||||
/* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */
|
||||
#define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */
|
||||
#define PEX_DC_EN_NO_SNOOP BIT_11 /* Enable No Snoop */
|
||||
@@ -617,6 +675,7 @@
|
||||
#define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */
|
||||
#define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */
|
||||
#define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */
|
||||
#define B28_Y2_ASF_HCU_CCSR 0x0e68 /* 32 bit ASF HCU CCSR (Yukon EX) */
|
||||
#define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */
|
||||
#define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */
|
||||
#define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */
|
||||
@@ -826,8 +885,10 @@
|
||||
#define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */
|
||||
#define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */
|
||||
#define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */
|
||||
#define CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */
|
||||
#define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */
|
||||
#define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */
|
||||
#define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */
|
||||
|
||||
#define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */
|
||||
#define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */
|
||||
@@ -841,6 +902,11 @@
|
||||
#define CHIP_REV_YU_EC_U_A0 1
|
||||
#define CHIP_REV_YU_EC_U_A1 2
|
||||
|
||||
#define CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */
|
||||
|
||||
#define CHIP_REV_YU_EX_A0 1 /* Chip Rev. for Yukon-2 EX A0 */
|
||||
#define CHIP_REV_YU_EX_B0 2 /* Chip Rev. for Yukon-2 EX B0 */
|
||||
|
||||
/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
|
||||
#define Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */
|
||||
#define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */
|
||||
@@ -905,6 +971,18 @@
|
||||
#define TST_CFG_WRITE_ON BIT_1 /* Enable Config Reg WR */
|
||||
#define TST_CFG_WRITE_OFF BIT_0 /* Disable Config Reg WR */
|
||||
|
||||
/* B2_GP_IO */
|
||||
#define GLB_GPIO_CLK_DEB_ENA BIT_31 /* Clock Debug Enable */
|
||||
#define GLB_GPIO_CLK_DBG_MSK 0x3c000000 /* Clock Debug */
|
||||
|
||||
#define GLB_GPIO_INT_RST_D3_DIS BIT_15 /* Disable Internal Reset After D3 to D0 */
|
||||
#define GLB_GPIO_LED_PAD_SPEED_UP BIT_14 /* LED PAD Speed Up */
|
||||
#define GLB_GPIO_STAT_RACE_DIS BIT_13 /* Status Race Disable */
|
||||
#define GLB_GPIO_TEST_SEL_MSK 0x00001800 /* Testmode Select */
|
||||
#define GLB_GPIO_TEST_SEL_BASE BIT_11
|
||||
#define GLB_GPIO_RAND_ENA BIT_10 /* Random Enable */
|
||||
#define GLB_GPIO_RAND_BIT_1 BIT_9 /* Random Bit 1 */
|
||||
|
||||
/* B2_I2C_CTRL 32 bit I2C HW Control Register */
|
||||
#define I2C_FLAG BIT_31 /* Start read/write if WR */
|
||||
#define I2C_ADDR (0x7fff<<16) /* Bit 30..16: Addr to be RD/WR */
|
||||
@@ -1026,13 +1104,16 @@
|
||||
/* Bit 10..0: same as for Rx */
|
||||
|
||||
/* Q_F 32 bit Flag Register */
|
||||
#define F_ALM_FULL BIT_27 /* Rx FIFO: almost full */
|
||||
#define F_EMPTY BIT_27 /* Tx FIFO: empty flag */
|
||||
#define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */
|
||||
#define F_WM_REACHED BIT_25 /* Watermark reached */
|
||||
#define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */
|
||||
#define F_FIFO_LEVEL (0x1f<<16) /* Bit 23..16: # of Qwords in FIFO */
|
||||
#define F_WATER_MARK 0x0007ff /* Bit 10.. 0: Watermark */
|
||||
#define F_TX_CHK_AUTO_OFF BIT_31 /* Tx checksum auto-calc Off(Yukon EX)*/
|
||||
#define F_TX_CHK_AUTO_ON BIT_30 /* Tx checksum auto-calc On(Yukon EX)*/
|
||||
#define F_ALM_FULL BIT_28 /* Rx FIFO: almost full */
|
||||
#define F_EMPTY BIT_27 /* Tx FIFO: empty flag */
|
||||
#define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */
|
||||
#define F_WM_REACHED BIT_25 /* Watermark reached */
|
||||
#define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */
|
||||
#define F_FIFO_LEVEL (0x1f<<16)
|
||||
/* Bit 23..16: # of Qwords in FIFO */
|
||||
#define F_WATER_MARK 0x0007ff/* Bit 10.. 0: Watermark */
|
||||
|
||||
/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
|
||||
/* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */
|
||||
@@ -1614,6 +1695,8 @@
|
||||
(GM_MIB_CNT_BASE + 24) /* Multicast Frames Received OK */
|
||||
#define GM_RXF_FCS_ERR \
|
||||
(GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */
|
||||
#define GM_RXF_SPARE1 \
|
||||
(GM_MIB_CNT_BASE + 40) /* Rx spare 1 */
|
||||
#define GM_RXO_OK_LO \
|
||||
(GM_MIB_CNT_BASE + 48) /* Octets Received OK Low */
|
||||
#define GM_RXO_OK_HI \
|
||||
@@ -1644,8 +1727,12 @@
|
||||
(GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */
|
||||
#define GM_RXF_JAB_PKT \
|
||||
(GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */
|
||||
#define GM_RXF_SPARE2 \
|
||||
(GM_MIB_CNT_BASE + 168) /* Rx spare 2 */
|
||||
#define GM_RXE_FIFO_OV \
|
||||
(GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */
|
||||
#define GM_RXF_SPARE3 \
|
||||
(GM_MIB_CNT_BASE + 184) /* Rx spare 3 */
|
||||
#define GM_TXF_UC_OK \
|
||||
(GM_MIB_CNT_BASE + 192) /* Unicast Frames Xmitted OK */
|
||||
#define GM_TXF_BC_OK \
|
||||
@@ -1672,6 +1759,8 @@
|
||||
(GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */
|
||||
#define GM_TXF_MAX_SZ \
|
||||
(GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */
|
||||
#define GM_TXF_SPARE1 \
|
||||
(GM_MIB_CNT_BASE + 296) /* Tx spare 1 */
|
||||
#define GM_TXF_COL \
|
||||
(GM_MIB_CNT_BASE + 304) /* Tx Collision */
|
||||
#define GM_TXF_LAT_COL \
|
||||
@@ -1818,6 +1907,7 @@
|
||||
GMR_FS_LONG_ERR | \
|
||||
GMR_FS_MII_ERR | \
|
||||
GMR_FS_BAD_FC | \
|
||||
GMR_FS_GOOD_FC | \
|
||||
GMR_FS_UN_SIZE | \
|
||||
GMR_FS_JABBER)
|
||||
|
||||
@@ -1846,6 +1936,10 @@
|
||||
#define RX_TRUNC_OFF BIT_26 /* disable packet truncation */
|
||||
#define RX_VLAN_STRIP_ON BIT_25 /* enable VLAN stripping */
|
||||
#define RX_VLAN_STRIP_OFF BIT_24 /* disable VLAN stripping */
|
||||
#define GMF_RX_OVER_ON BIT_19 /* enable flushing on receive overrun */
|
||||
#define GMF_RX_OVER_OFF BIT_18 /* disable flushing on receive overrun */
|
||||
#define GMF_ASF_RX_OVER_ON BIT_17 /* enable flushing of ASF when overrun */
|
||||
#define GMF_ASF_RX_OVER_OFF BIT_16 /* disable flushing of ASF when overrun */
|
||||
#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */
|
||||
#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */
|
||||
#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */
|
||||
@@ -1907,6 +2001,28 @@
|
||||
#define Y2_ASF_UC_STATE (3<<2) /* ASF uC State */
|
||||
#define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */
|
||||
|
||||
/* B28_Y2_ASF_HCU_CCSR 32bit CPU Control and Status Register (Yukon EX) */
|
||||
#define Y2_ASF_HCU_CCSR_SMBALERT_MONITOR BIT_27 /* SMBALERT pin monitor */
|
||||
#define Y2_ASF_HCU_CCSR_CPU_SLEEP BIT_26 /* CPU sleep status */
|
||||
#define Y2_ASF_HCU_CCSR_CS_TO BIT_25 /* Clock Stretching Timeout */
|
||||
#define Y2_ASF_HCU_CCSR_WDOG BIT_24 /* Watchdog Reset */
|
||||
#define Y2_ASF_HCU_CCSR_CLR_IRQ_HOST BIT_17 /* Clear IRQ_HOST */
|
||||
#define Y2_ASF_HCU_CCSR_SET_IRQ_HCU BIT_16 /* Set IRQ_HCU */
|
||||
#define Y2_ASF_HCU_CCSR_AHB_RST BIT_9 /* Reset AHB bridge */
|
||||
#define Y2_ASF_HCU_CCSR_CPU_RST_MODE BIT_8 /* CPU Reset Mode */
|
||||
#define Y2_ASF_HCU_CCSR_SET_SYNC_CPU BIT_5
|
||||
#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE1 BIT_4
|
||||
#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE0 BIT_3
|
||||
#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK (BIT_4 | BIT_3) /* CPU Clock Divide */
|
||||
#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_BASE BIT_3
|
||||
#define Y2_ASF_HCU_CCSR_OS_PRSNT BIT_2 /* ASF OS Present */
|
||||
/* Microcontroller State */
|
||||
#define Y2_ASF_HCU_CCSR_UC_STATE_MSK 3
|
||||
#define Y2_ASF_HCU_CCSR_UC_STATE_BASE BIT_0
|
||||
#define Y2_ASF_HCU_CCSR_ASF_RESET 0
|
||||
#define Y2_ASF_HCU_CCSR_ASF_HALTED BIT_1
|
||||
#define Y2_ASF_HCU_CCSR_ASF_RUNNING BIT_0
|
||||
|
||||
/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
|
||||
/* This register is used by the ASF firmware */
|
||||
#define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */
|
||||
@@ -1920,6 +2036,14 @@
|
||||
#define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */
|
||||
|
||||
/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
|
||||
#define GMC_SEC_RST BIT_15 /* MAC SEC RST */
|
||||
#define GMC_SEC_RST_OFF BIT_14 /* MAC SEC RST Off */
|
||||
#define GMC_BYP_MACSECRX_ON BIT_13 /* Bypass MAC SEC RX */
|
||||
#define GMC_BYP_MACSECRX_OFF BIT_12 /* Bypass MAC SEC RX Off */
|
||||
#define GMC_BYP_MACSECTX_ON BIT_11 /* Bypass MAC SEC TX */
|
||||
#define GMC_BYP_MACSECTX_OFF BIT_10 /* Bypass MAC SEC TX Off */
|
||||
#define GMC_BYP_RETR_ON BIT_9 /* Bypass MAC retransmit FIFO On */
|
||||
#define GMC_BYP_RETR_OFF BIT_8 /* Bypass MAC retransmit FIFO Off */
|
||||
#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */
|
||||
#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */
|
||||
#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */
|
||||
@@ -2113,6 +2237,8 @@ struct msk_stat_desc {
|
||||
#define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN)
|
||||
#define OP_LRGLEN 0x24000000
|
||||
#define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN)
|
||||
#define OP_MSS 0x28000000
|
||||
#define OP_MSSVLAN (OP_MSS | OP_VLAN)
|
||||
#define OP_BUFFER 0x40000000
|
||||
#define OP_PACKET 0x41000000
|
||||
#define OP_LARGESEND 0x43000000
|
||||
@@ -2131,8 +2257,19 @@ struct msk_stat_desc {
|
||||
#define OP_PUTIDX 0x70000000
|
||||
|
||||
#define STLE_OP_MASK 0xff000000
|
||||
#define STLE_CSS_MASK 0x00ff0000
|
||||
#define STLE_LEN_MASK 0x0000ffff
|
||||
|
||||
/* CSS defined in status LE(valid for descriptor V2 format). */
|
||||
#define CSS_TCPUDP_CSUM_OK 0x00800000
|
||||
#define CSS_UDP 0x00400000
|
||||
#define CSS_TCP 0x00200000
|
||||
#define CSS_IPFRAG 0x00100000
|
||||
#define CSS_IPV6 0x00080000
|
||||
#define CSS_IPV4_CSUM_OK 0x00040000
|
||||
#define CSS_IPV4 0x00020000
|
||||
#define CSS_PORT 0x00010000
|
||||
|
||||
/* Descriptor Bit Definition */
|
||||
/* TxCtrl Transmit Buffer Control Field */
|
||||
/* RxCtrl Receive Buffer Control Field */
|
||||
@@ -2157,12 +2294,12 @@ struct msk_stat_desc {
|
||||
|
||||
#define MSK_TX_RING_CNT 256
|
||||
#define MSK_RX_RING_CNT 256
|
||||
#define MSK_RX_BUF_ALIGN 8
|
||||
#define MSK_JUMBO_RX_RING_CNT MSK_RX_RING_CNT
|
||||
#define MSK_STAT_RING_CNT ((1 + 3) * (MSK_TX_RING_CNT + MSK_RX_RING_CNT))
|
||||
#define MSK_MAXTXSEGS 32
|
||||
#define MSK_TSO_MAXSGSIZE 4096
|
||||
#define MSK_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header))
|
||||
#define MSK_MAXRXSEGS 32
|
||||
|
||||
/*
|
||||
* It seems that the hardware requires extra decriptors(LEs) to offload
|
||||
@@ -2189,20 +2326,6 @@ struct msk_stat_desc {
|
||||
#define MSK_MAX_FRAMELEN \
|
||||
(ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)
|
||||
#define MSK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
|
||||
#define MSK_JSLOTS ((MSK_RX_RING_CNT * 3) / 2)
|
||||
|
||||
#define MSK_JRAWLEN (MSK_JUMBO_FRAMELEN + ETHER_ALIGN)
|
||||
#define MSK_JLEN (MSK_JRAWLEN + (sizeof(uint64_t) - \
|
||||
(MSK_JRAWLEN % sizeof(uint64_t))))
|
||||
#define MSK_JPAGESZ PAGE_SIZE
|
||||
#define MSK_RESID \
|
||||
(MSK_JPAGESZ - (MSK_JLEN * MSK_JSLOTS) % MSK_JPAGESZ)
|
||||
#define MSK_JMEM ((MSK_JLEN * MSK_JSLOTS) + MSK_RESID)
|
||||
|
||||
struct msk_jpool_entry {
|
||||
int slot;
|
||||
SLIST_ENTRY(msk_jpool_entry) jpool_entries;
|
||||
};
|
||||
|
||||
struct msk_txdesc {
|
||||
struct mbuf *tx_m;
|
||||
@@ -2228,10 +2351,6 @@ struct msk_chain_data {
|
||||
bus_dmamap_t msk_rx_ring_map;
|
||||
bus_dmamap_t msk_rx_sparemap;
|
||||
bus_dma_tag_t msk_jumbo_rx_tag;
|
||||
bus_dma_tag_t msk_jumbo_tag;
|
||||
bus_dmamap_t msk_jumbo_map;
|
||||
bus_dma_tag_t msk_jumbo_mtag;
|
||||
caddr_t msk_jslots[MSK_JSLOTS];
|
||||
struct msk_rxdesc msk_jumbo_rxdesc[MSK_JUMBO_RX_RING_CNT];
|
||||
bus_dma_tag_t msk_jumbo_rx_ring_tag;
|
||||
bus_dmamap_t msk_jumbo_rx_ring_map;
|
||||
@@ -2253,8 +2372,6 @@ struct msk_ring_data {
|
||||
bus_addr_t msk_rx_ring_paddr;
|
||||
struct msk_rx_desc *msk_jumbo_rx_ring;
|
||||
bus_addr_t msk_jumbo_rx_ring_paddr;
|
||||
void *msk_jumbo_buf;
|
||||
bus_addr_t msk_jumbo_buf_paddr;
|
||||
};
|
||||
|
||||
#define MSK_TX_RING_ADDR(sc, i) \
|
||||
@@ -2289,6 +2406,52 @@ struct msk_ring_data {
|
||||
/* Forward decl. */
|
||||
struct msk_if_softc;
|
||||
|
||||
struct msk_hw_stats {
|
||||
/* Rx stats. */
|
||||
uint32_t rx_ucast_frames;
|
||||
uint32_t rx_bcast_frames;
|
||||
uint32_t rx_pause_frames;
|
||||
uint32_t rx_mcast_frames;
|
||||
uint32_t rx_crc_errs;
|
||||
uint32_t rx_spare1;
|
||||
uint64_t rx_good_octets;
|
||||
uint64_t rx_bad_octets;
|
||||
uint32_t rx_runts;
|
||||
uint32_t rx_runt_errs;
|
||||
uint32_t rx_pkts_64;
|
||||
uint32_t rx_pkts_65_127;
|
||||
uint32_t rx_pkts_128_255;
|
||||
uint32_t rx_pkts_256_511;
|
||||
uint32_t rx_pkts_512_1023;
|
||||
uint32_t rx_pkts_1024_1518;
|
||||
uint32_t rx_pkts_1519_max;
|
||||
uint32_t rx_pkts_too_long;
|
||||
uint32_t rx_pkts_jabbers;
|
||||
uint32_t rx_spare2;
|
||||
uint32_t rx_fifo_oflows;
|
||||
uint32_t rx_spare3;
|
||||
/* Tx stats. */
|
||||
uint32_t tx_ucast_frames;
|
||||
uint32_t tx_bcast_frames;
|
||||
uint32_t tx_pause_frames;
|
||||
uint32_t tx_mcast_frames;
|
||||
uint64_t tx_octets;
|
||||
uint32_t tx_pkts_64;
|
||||
uint32_t tx_pkts_65_127;
|
||||
uint32_t tx_pkts_128_255;
|
||||
uint32_t tx_pkts_256_511;
|
||||
uint32_t tx_pkts_512_1023;
|
||||
uint32_t tx_pkts_1024_1518;
|
||||
uint32_t tx_pkts_1519_max;
|
||||
uint32_t tx_spare1;
|
||||
uint32_t tx_colls;
|
||||
uint32_t tx_late_colls;
|
||||
uint32_t tx_excess_colls;
|
||||
uint32_t tx_multi_colls;
|
||||
uint32_t tx_single_colls;
|
||||
uint32_t tx_underflows;
|
||||
};
|
||||
|
||||
/* Softc for the Marvell Yukon II controller. */
|
||||
struct msk_softc {
|
||||
struct resource *msk_res[1]; /* I/O resource */
|
||||
@@ -2306,9 +2469,8 @@ struct msk_softc {
|
||||
uint32_t msk_coppertype;
|
||||
uint32_t msk_intrmask;
|
||||
uint32_t msk_intrhwemask;
|
||||
int msk_suspended;
|
||||
uint32_t msk_pflags;
|
||||
int msk_clock;
|
||||
int msk_msi;
|
||||
struct msk_if_softc *msk_if[2];
|
||||
device_t msk_devs[2];
|
||||
int msk_txqsize;
|
||||
@@ -2346,7 +2508,20 @@ struct msk_if_softc {
|
||||
int msk_framesize;
|
||||
int msk_phytype;
|
||||
int msk_phyaddr;
|
||||
int msk_link;
|
||||
uint32_t msk_flags;
|
||||
#define MSK_FLAG_MSI 0x0001
|
||||
#define MSK_FLAG_FASTETHER 0x0004
|
||||
#define MSK_FLAG_JUMBO 0x0008
|
||||
#define MSK_FLAG_JUMBO_NOCSUM 0x0010
|
||||
#define MSK_FLAG_RAMBUF 0x0020
|
||||
#define MSK_FLAG_DESCV2 0x0040
|
||||
#define MSK_FLAG_AUTOTX_CSUM 0x0080
|
||||
#define MSK_FLAG_NOHWVLAN 0x0100
|
||||
#define MSK_FLAG_NORXCHK 0x0200
|
||||
#define MSK_FLAG_NORX_CSUM 0x0400
|
||||
#define MSK_FLAG_SUSPEND 0x2000
|
||||
#define MSK_FLAG_DETACH 0x4000
|
||||
#define MSK_FLAG_LINK 0x8000
|
||||
struct callout msk_tick_ch;
|
||||
int msk_watchdog_timer;
|
||||
uint32_t msk_txq; /* Tx. Async Queue offset */
|
||||
@@ -2355,19 +2530,12 @@ struct msk_if_softc {
|
||||
struct msk_chain_data msk_cdata;
|
||||
struct msk_ring_data msk_rdata;
|
||||
struct msk_softc *msk_softc; /* parent controller */
|
||||
struct task msk_link_task;
|
||||
struct msk_hw_stats msk_stats;
|
||||
struct task msk_tx_task;
|
||||
int msk_if_flags;
|
||||
int msk_detach;
|
||||
uint16_t msk_vtag; /* VLAN tag id. */
|
||||
SLIST_HEAD(__msk_jfreehead, msk_jpool_entry) msk_jfree_listhead;
|
||||
SLIST_HEAD(__msk_jinusehead, msk_jpool_entry) msk_jinuse_listhead;
|
||||
struct mtx msk_jlist_mtx;
|
||||
};
|
||||
|
||||
#define MSK_JLIST_LOCK(_sc) mtx_lock(&(_sc)->msk_jlist_mtx)
|
||||
#define MSK_JLIST_UNLOCK(_sc) mtx_unlock(&(_sc)->msk_jlist_mtx)
|
||||
|
||||
#define MSK_TIMEOUT 1000
|
||||
#define MSK_PHY_POWERUP 1
|
||||
#define MSK_PHY_POWERDOWN 0
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
$FreeBSD: src/sys/dev/mii/miidevs,v 1.62 2008/10/23 01:27:15 yongari Exp $
|
||||
$FreeBSD$
|
||||
/*$NetBSD: miidevs,v 1.6 1999/05/14 11:37:30 drochner Exp $*/
|
||||
|
||||
/*-
|
||||
@@ -52,6 +52,7 @@ $FreeBSD: src/sys/dev/mii/miidevs,v 1.62 2008/10/23 01:27:15 yongari Exp $
|
||||
oui AGERE 0x00a0bc Agere Systems
|
||||
oui ALTIMA 0x0010a9 Altima Communications
|
||||
oui AMD 0x00001a Advanced Micro Devices
|
||||
oui ASIX 0x00602e Asix Semiconductor
|
||||
oui ATHEROS 0x001374 Atheros Communications
|
||||
oui BROADCOM 0x001018 Broadcom Corporation
|
||||
oui BROADCOM2 0x000af7 Broadcom Corporation
|
||||
@@ -120,6 +121,9 @@ model AMD 79c973phy 0x0036 Am79c973 internal PHY
|
||||
model AMD 79c978 0x0039 Am79c978 HomePNA PHY
|
||||
model xxAMD 79C873 0x0000 Am79C873/DM9101 10/100 media interface
|
||||
|
||||
/* Asix semiconductor PHYs. */
|
||||
model ASIX AX88X9X 0x0031 Ax88x9x internal PHY
|
||||
|
||||
/* Atheros Communications/Attansic PHYs. */
|
||||
model ATHEROS F1 0x0001 Atheros F1 10/100/1000 PHY
|
||||
model ATHEROS F2 0x0002 Atheros F2 10/100 PHY
|
||||
@@ -243,6 +247,7 @@ model MARVELL E1111 0x000c Marvell 88E1111 Gigabit PHY
|
||||
model MARVELL E1116 0x0021 Marvell 88E1116 Gigabit PHY
|
||||
model MARVELL E1116R 0x0024 Marvell 88E1116R Gigabit PHY
|
||||
model MARVELL E1118 0x0022 Marvell 88E1118 Gigabit PHY
|
||||
model MARVELL E3016 0x0026 Marvell 88E3016 10/100 Fast Ethernet PHY
|
||||
model xxMARVELL E1000 0x0005 Marvell 88E1000 Gigabit PHY
|
||||
model xxMARVELL E1011 0x0002 Marvell 88E1011 Gigabit PHY
|
||||
model xxMARVELL E1000_3 0x0003 Marvell 88E1000 Gigabit PHY
|
||||
|
||||
Reference in New Issue
Block a user