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intel_extreme: Add IvyBridge fixups

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* Add initial clock gating fix (may need tweaking)
This commit is contained in:
Alexander von Gluck IV
2012-12-28 19:01:02 +00:00
parent 50efc4c719
commit d1043dfa07
3 changed files with 9 additions and 3 deletions
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src/add-ons/accelerants/intel_extreme/hooks.cpp
+2 -1
View File
@@ -117,7 +117,8 @@ get_accelerant_hook(uint32 feature, void* data)
|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_G4x)
|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)
|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_ILK)
|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_SNB))
|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_SNB)
|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IVB))
return NULL;
return (void*)intel_allocate_overlay_buffer;
src/add-ons/accelerants/intel_extreme/mode.cpp
+4 -2
View File
@@ -138,7 +138,8 @@ set_frame_buffer_base()
if (sharedInfo.device_type.InGroup(INTEL_TYPE_96x)
|| sharedInfo.device_type.InGroup(INTEL_TYPE_G4x)
|| sharedInfo.device_type.InGroup(INTEL_TYPE_ILK)
|| sharedInfo.device_type.InGroup(INTEL_TYPE_SNB)) {
|| sharedInfo.device_type.InGroup(INTEL_TYPE_SNB)
|| sharedInfo.device_type.InGroup(INTEL_TYPE_IVB)) {
write32(baseRegister, mode.v_display_start * sharedInfo.bytes_per_row
+ mode.h_display_start * (sharedInfo.bits_per_pixel + 7) / 8);
read32(baseRegister);
@@ -241,7 +242,8 @@ get_pll_limits(pll_limits &limits)
// tested
if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_ILK)
|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_SNB)) {
|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_SNB)
|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IVB)) {
// TODO: support LVDS output limits as well
static const pll_limits kLimits = {
// p, p1, p2, high, n, m, m1, m2
src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
+3
View File
@@ -305,6 +305,9 @@ intel_extreme_init(intel_info &info)
} else if (info.device_type.InGroup(INTEL_TYPE_SNB)) {
TRACE("SandyBridge clock gating\n");
write32(info, 0x42020, (1L << 28) | (1L << 7) | (1L << 5));
} else if (info.device_type.InGroup(INTEL_TYPE_IVB)) {
TRACE("IvyBridge clock gating\n");
write32(info, 0x42020, (1L << 28));
} else if (info.device_type.InGroup(INTEL_TYPE_ILK)) {
TRACE("IronLake clock gating\n");
write32(info, 0x42020, (1L << 7) | (1L << 5));