ahci: Whitespace and line length cleanup only.
This commit is contained in:
Michael Lotz
@@ -29,20 +29,21 @@ enum {
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CAP_SALP = (1 << 26), // Supports Aggressive Link Power Management
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CAP_SAL = (1 << 25), // Supports Activity LED
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CAP_SCLO = (1 << 24), // Supports Command List Override
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CAP_ISS_MASK = 0xf, // Interface Speed Support
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CAP_ISS_MASK = 0xf, // Interface Speed Support
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CAP_ISS_SHIFT = 20,
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CAP_SNZO = (1 << 19), // Supports Non-Zero DMA Offsets
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CAP_SAM = (1 << 18), // Supports AHCI mode only
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CAP_SPM = (1 << 17), // Supports Port Multiplier
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CAP_FBSS = (1 << 16), // FIS-based Switching Supported
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CAP_PMD = (1 << 15), // PIO Multiple DRQ Block
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CAP_SSC = (1 << 14), // Slumber State Capable
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CAP_PSC = (1 << 13), // Partial State Capable
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CAP_NCS_MASK = 0x1f, // Number of Command Slots (zero-based number)
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CAP_SNZO = (1 << 19), // Supports Non-Zero DMA Offsets
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CAP_SAM = (1 << 18), // Supports AHCI mode only
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CAP_SPM = (1 << 17), // Supports Port Multiplier
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CAP_FBSS = (1 << 16), // FIS-based Switching Supported
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CAP_PMD = (1 << 15), // PIO Multiple DRQ Block
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CAP_SSC = (1 << 14), // Slumber State Capable
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CAP_PSC = (1 << 13), // Partial State Capable
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CAP_NCS_MASK = 0x1f, // Number of Command Slots
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// (zero-based number)
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CAP_NCS_SHIFT = 8,
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CAP_CCCS = (1 << 7), // Command Completion Coalescing Supported
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CAP_EMS = (1 << 6), // Enclosure Management Supported
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CAP_SXS = (1 << 5), // Supports External SATA
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CAP_CCCS = (1 << 7), // Command Completion Coalescing Supported
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CAP_EMS = (1 << 6), // Enclosure Management Supported
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CAP_SXS = (1 << 5), // Supports External SATA
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CAP_NP_MASK = 0x1f, // Number of Ports (zero-based number)
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CAP_NP_SHIFT = 0,
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};
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@@ -73,16 +74,17 @@ enum {
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INT_SDB = (1 << 3), // Set Device Bits Interrupt/Enable
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INT_DS = (1 << 2), // DMA Setup FIS Interrupt/Enable
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INT_PS = (1 << 1), // PIO Setup FIS Interrupt/Enable
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INT_DHR = (1 << 0), // Device to Host Register FIS Interrupt/Enable
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INT_DHR = (1 << 0), // Device to Host Register FIS
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// Interrupt/Enable
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};
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typedef struct {
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uint16 reserved : 12;
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uint8 pmp : 4; // Port Multiplier Port: Not used by AHCI
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uint8 spm : 4; // Select Power Management: Not used by AHCI
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uint8 ipm : 4; // Interface Power Management Transitions Allowed
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uint8 spd : 4; // Speed Allowed
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uint8 det : 4; // Device Detection Initialization
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uint8 pmp : 4; // Port Multiplier Port: Not used by AHCI
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uint8 spm : 4; // Select Power Management: Not used by AHCI
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uint8 ipm : 4; // Interface Power Management Transitions Allowed
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uint8 spd : 4; // Speed Allowed
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uint8 det : 4; // Device Detection Initialization
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} _PACKED scontrol;
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#define IPM_TRANSITIONS_TO_PARTIAL_DISABLED 0x1
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@@ -92,14 +94,15 @@ typedef struct {
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typedef struct {
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uint32 clb; // Command List Base Address (alignment 1024 byte)
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uint32 clb; // Command List Base Address
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// (alignment 1024 byte)
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uint32 clbu; // Command List Base Address Upper 32-Bits
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uint32 fb; // FIS Base Address (alignment 256 byte)
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uint32 fbu; // FIS Base Address Upper 32-Bits
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uint32 is; // Interrupt Status **RWC**
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uint32 ie; // Interrupt Enable
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uint32 cmd; // Command and Status
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uint32 res1; // Reserved
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uint32 res1; // Reserved
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uint32 tfd; // Task File Data
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uint32 sig; // Signature
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uint32 ssts; // Serial ATA Status (SCR0: SStatus)
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@@ -116,9 +119,9 @@ typedef struct {
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enum {
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PORT_CMD_ICC_ACTIVE = (1 << 28), // Interface Communication control
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PORT_CMD_ICC_SLUMBER = (6 << 28), // Interface Communication control
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PORT_CMD_ICC_MASK = (0xf<<28), // Interface Communication control
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PORT_CMD_ICC_ACTIVE = (1 << 28), // Interface Communication control
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PORT_CMD_ICC_SLUMBER = (6 << 28), // Interface Communication control
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PORT_CMD_ICC_MASK = (0xf<<28), // Interface Communication control
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PORT_CMD_ATAPI = (1 << 24), // Device is ATAPI
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PORT_CMD_CR = (1 << 15), // Command List Running (DMA active)
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PORT_CMD_FR = (1 << 14), // FIS Receive Running
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@@ -150,17 +153,17 @@ enum {
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PORT_INT_DHR = (1 << 0), // Device to Host Register FIS Interrupt
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};
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#define PORT_INT_ERROR (PORT_INT_TFE | PORT_INT_HBF | PORT_INT_HBD \
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| PORT_INT_IF | PORT_INT_INF | PORT_INT_OF \
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| PORT_INT_IPM | PORT_INT_PRC | PORT_INT_PC \
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| PORT_INT_UF)
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#define PORT_INT_ERROR (PORT_INT_TFE | PORT_INT_HBF | PORT_INT_HBD \
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| PORT_INT_IF | PORT_INT_INF | PORT_INT_OF \
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| PORT_INT_IPM | PORT_INT_PRC | PORT_INT_PC \
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| PORT_INT_UF)
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#define PORT_INT_MASK (PORT_INT_ERROR | PORT_INT_DP | PORT_INT_SDB \
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| PORT_INT_DS | PORT_INT_PS | PORT_INT_DHR)
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| PORT_INT_DS | PORT_INT_PS | PORT_INT_DHR)
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enum {
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ATA_BSY = 0x80,
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ATA_DF = 0x20,
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ATA_BSY = 0x80,
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ATA_DF = 0x20,
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ATA_DRQ = 0x08,
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ATA_ERR = 0x01,
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};
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@@ -168,11 +171,11 @@ enum {
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enum {
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PORT_FBS_DWE_SHIFT = 16, // Device With Error
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PORT_FBS_DWE_MASK = 0xf,
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PORT_FBS_DWE_MASK = 0xf,
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PORT_FBS_ADO_SHIFT = 12, // Active Device Optimization
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PORT_FBS_ADO_MASK = 0xf,
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PORT_FBS_ADO_MASK = 0xf,
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PORT_FBS_DEV_SHIFT = 8, // Device To Issue
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PORT_FBS_DEV_MASK = 0xf,
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PORT_FBS_DEV_MASK = 0xf,
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PORT_FBS_SDE = 0x04, // Single Device Error
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PORT_FBS_DEC = 0x02, // Device Error Clear
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PORT_FBS_EN = 0x01, // Enable
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@@ -181,7 +184,7 @@ enum {
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enum {
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PORT_DEVSLP_DM_SHIFT = 25, // DITO Multiplier
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PORT_DEVSLP_DM_MASK = 0xf,
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PORT_DEVSLP_DM_MASK = 0xf,
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PORT_DEVSLP_DITO_SHIFT = 15, // Device Sleep Idle Timeout
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PORT_DEVSLP_DITO_MASK = 0x3ff,
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PORT_DEVSLP_MDAT_SHIFT = 10, // Minimum Device Sleep Assertion Time
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@@ -194,12 +197,13 @@ enum {
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enum {
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CAP2_DESO = (1 << 5), // DevSleep Entrance from Slumber Only
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CAP2_SADM = (1 << 4), // Supports Aggressive Device Sleep Management
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CAP2_SDS = (1 << 3), // Supports Device Sleep
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CAP2_APST = (1 << 2), // Automatic Partial to Slumber Transitions
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CAP2_NVMP = (1 << 1), // NVMHCI Present
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CAP2_BOH = (1 << 0), // BIOS/OS Handoff
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CAP2_DESO = (1 << 5), // DevSleep Entrance from Slumber Only
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CAP2_SADM = (1 << 4), // Supports Aggressive Device Sleep
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// Management
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CAP2_SDS = (1 << 3), // Supports Device Sleep
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CAP2_APST = (1 << 2), // Automatic Partial to Slumber Transitions
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CAP2_NVMP = (1 << 1), // NVMHCI Present
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CAP2_BOH = (1 << 0), // BIOS/OS Handoff
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};
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@@ -235,21 +239,22 @@ typedef struct {
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typedef struct {
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union {
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struct {
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uint16 cfl : 5; // command FIS length
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uint16 a : 1; // ATAPI
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uint16 w : 1; // Write
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uint16 p : 1; // Prefetchable
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uint16 r : 1; // Reset
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uint16 b : 1; // Build In Self Test
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uint16 c : 1; // Clear Busy upon R_OK
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uint16 : 1;
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uint16 pmp : 4; // Port Multiplier Port
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uint16 prdtl; // physical region description table length;
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} _PACKED;
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uint32 prdtl_flags_cfl;
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} _PACKED;
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union {
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struct {
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uint16 cfl : 5; // command FIS length
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uint16 a : 1; // ATAPI
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uint16 w : 1; // Write
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uint16 p : 1; // Prefetchable
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uint16 r : 1; // Reset
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uint16 b : 1; // Build In Self Test
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uint16 c : 1; // Clear Busy upon R_OK
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uint16 : 1;
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uint16 pmp : 4; // Port Multiplier Port
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uint16 prdtl; // physical region description table
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// length;
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} _PACKED;
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uint32 prdtl_flags_cfl;
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} _PACKED;
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uint32 prdbc; // PRD Byte Count
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uint32 ctba; // command table desciptor base address
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// (alignment 128 byte)
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@@ -265,16 +270,16 @@ typedef struct {
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// 1 - C bit (0x80)
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// 2 - Command
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// 3 - Features
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// 4 - Sector Number (LBA Low, bits 0-7)
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// 5 - Cylinder Low (LBA Mid, bits 8-15)
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// 6 - Cylinder High (LBA High, bits 16-23)
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// 7 - Device / Head (for 28-bit LBA commands, bits 24-27)
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// 8 - Sector Number expanded (LBA Low-previous, bits 24-31)
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// 9 - Cylinder Low expanded (LBA Mid-previous, bits 32-39)
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// 10 - Cylinder High expanded (LBA High-previous, bits 40-47)
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// 4 - Sector Number (LBA Low, bits 0-7)
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// 5 - Cylinder Low (LBA Mid, bits 8-15)
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// 6 - Cylinder High (LBA High, bits 16-23)
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// 7 - Device / Head (for 28-bit LBA commands, bits 24-27)
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// 8 - Sector Number expanded (LBA Low-previous, bits 24-31)
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// 9 - Cylinder Low expanded (LBA Mid-previous, bits 32-39)
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// 10 - Cylinder High expanded (LBA High-previous, bits 40-47)
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// 11 - Features expanded
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// 12 - Sector Count (Sector count, bits 0-7)
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// 13 - Sector Count expanded (Sector count, bits 8-15)
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// 12 - Sector Count (Sector count, bits 0-7)
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// 13 - Sector Count expanded (Sector count, bits 8-15)
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// 14 - Reserved (0)
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// 15 - Control
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// 16 - Reserved (0)
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