ahci: Whitespace and line length cleanup only.
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@@ -38,7 +38,8 @@ enum {
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CAP_PMD = (1 << 15), // PIO Multiple DRQ Block
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CAP_PMD = (1 << 15), // PIO Multiple DRQ Block
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CAP_SSC = (1 << 14), // Slumber State Capable
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CAP_SSC = (1 << 14), // Slumber State Capable
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CAP_PSC = (1 << 13), // Partial State Capable
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CAP_PSC = (1 << 13), // Partial State Capable
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CAP_NCS_MASK = 0x1f, // Number of Command Slots (zero-based number)
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CAP_NCS_MASK = 0x1f, // Number of Command Slots
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// (zero-based number)
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CAP_NCS_SHIFT = 8,
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CAP_NCS_SHIFT = 8,
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CAP_CCCS = (1 << 7), // Command Completion Coalescing Supported
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CAP_CCCS = (1 << 7), // Command Completion Coalescing Supported
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CAP_EMS = (1 << 6), // Enclosure Management Supported
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CAP_EMS = (1 << 6), // Enclosure Management Supported
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@@ -73,7 +74,8 @@ enum {
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INT_SDB = (1 << 3), // Set Device Bits Interrupt/Enable
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INT_SDB = (1 << 3), // Set Device Bits Interrupt/Enable
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INT_DS = (1 << 2), // DMA Setup FIS Interrupt/Enable
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INT_DS = (1 << 2), // DMA Setup FIS Interrupt/Enable
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INT_PS = (1 << 1), // PIO Setup FIS Interrupt/Enable
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INT_PS = (1 << 1), // PIO Setup FIS Interrupt/Enable
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INT_DHR = (1 << 0), // Device to Host Register FIS Interrupt/Enable
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INT_DHR = (1 << 0), // Device to Host Register FIS
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// Interrupt/Enable
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};
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};
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typedef struct {
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typedef struct {
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@@ -92,7 +94,8 @@ typedef struct {
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typedef struct {
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typedef struct {
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uint32 clb; // Command List Base Address (alignment 1024 byte)
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uint32 clb; // Command List Base Address
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// (alignment 1024 byte)
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uint32 clbu; // Command List Base Address Upper 32-Bits
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uint32 clbu; // Command List Base Address Upper 32-Bits
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uint32 fb; // FIS Base Address (alignment 256 byte)
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uint32 fb; // FIS Base Address (alignment 256 byte)
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uint32 fbu; // FIS Base Address Upper 32-Bits
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uint32 fbu; // FIS Base Address Upper 32-Bits
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@@ -195,7 +198,8 @@ enum {
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enum {
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enum {
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CAP2_DESO = (1 << 5), // DevSleep Entrance from Slumber Only
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CAP2_DESO = (1 << 5), // DevSleep Entrance from Slumber Only
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CAP2_SADM = (1 << 4), // Supports Aggressive Device Sleep Management
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CAP2_SADM = (1 << 4), // Supports Aggressive Device Sleep
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// Management
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CAP2_SDS = (1 << 3), // Supports Device Sleep
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CAP2_SDS = (1 << 3), // Supports Device Sleep
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CAP2_APST = (1 << 2), // Automatic Partial to Slumber Transitions
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CAP2_APST = (1 << 2), // Automatic Partial to Slumber Transitions
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CAP2_NVMP = (1 << 1), // NVMHCI Present
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CAP2_NVMP = (1 << 1), // NVMHCI Present
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@@ -246,7 +250,8 @@ typedef struct {
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uint16 c : 1; // Clear Busy upon R_OK
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uint16 c : 1; // Clear Busy upon R_OK
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uint16 : 1;
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uint16 : 1;
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uint16 pmp : 4; // Port Multiplier Port
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uint16 pmp : 4; // Port Multiplier Port
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uint16 prdtl; // physical region description table length;
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uint16 prdtl; // physical region description table
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// length;
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} _PACKED;
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} _PACKED;
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uint32 prdtl_flags_cfl;
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uint32 prdtl_flags_cfl;
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} _PACKED;
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} _PACKED;
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