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* consolidate and remove unneeded Xorg headers

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* move mc code to more generic gpu source/header
* add gpu reset functions (with r600 documented)


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42616 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
2011-08-10 15:48:20 +00:00
parent fcde9a3249
commit d356bf5033
12 changed files with 392 additions and 3834 deletions
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headers/private/graphics/radeon_hd/r600_reg.h
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@@ -29,11 +29,6 @@
#define __R600_REG_H__
#include "r600_reg_auto_r6xx.h"
#include "r600_reg_r6xx.h"
#include "r600_reg_r7xx.h"
#define R600_PCIE_PORT_INDEX 0x0038
#define R600_PCIE_PORT_DATA 0x003c
headers/private/graphics/radeon_hd/r600_reg_auto_r6xx.h
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File diff suppressed because it is too large Load Diff
headers/private/graphics/radeon_hd/r600_reg_r6xx.h
-504
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@@ -1,504 +0,0 @@
/*
* RadeonHD R6xx, R7xx Register documentation
*
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
* Copyright (C) 2008-2009 Matthias Hopf
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _R600_REG_R6xx_H_
#define _R600_REG_R6xx_H_
/*
* Registers for R6xx chips that are not documented yet
*/
enum {
MM_INDEX = 0x0000,
MM_DATA = 0x0004,
SRBM_STATUS = 0x0e50,
RLC_RQ_PENDING_bit = 1 << 3,
RCU_RQ_PENDING_bit = 1 << 4,
GRBM_RQ_PENDING_bit = 1 << 5,
HI_RQ_PENDING_bit = 1 << 6,
IO_EXTERN_SIGNAL_bit = 1 << 7,
VMC_BUSY_bit = 1 << 8,
MCB_BUSY_bit = 1 << 9,
MCDZ_BUSY_bit = 1 << 10,
MCDY_BUSY_bit = 1 << 11,
MCDX_BUSY_bit = 1 << 12,
MCDW_BUSY_bit = 1 << 13,
SEM_BUSY_bit = 1 << 14,
SRBM_STATUS__RLC_BUSY_bit = 1 << 15,
PDMA_BUSY_bit = 1 << 16,
IH_BUSY_bit = 1 << 17,
CSC_BUSY_bit = 1 << 20,
CMC7_BUSY_bit = 1 << 21,
CMC6_BUSY_bit = 1 << 22,
CMC5_BUSY_bit = 1 << 23,
CMC4_BUSY_bit = 1 << 24,
CMC3_BUSY_bit = 1 << 25,
CMC2_BUSY_bit = 1 << 26,
CMC1_BUSY_bit = 1 << 27,
CMC0_BUSY_bit = 1 << 28,
BIF_BUSY_bit = 1 << 29,
IDCT_BUSY_bit = 1 << 30,
SRBM_READ_ERROR = 0x0e98,
READ_ADDRESS_mask = 0xffff << 2,
READ_ADDRESS_shift = 2,
READ_REQUESTER_HI_bit = 1 << 24,
READ_REQUESTER_GRBM_bit = 1 << 25,
READ_REQUESTER_RCU_bit = 1 << 26,
READ_REQUESTER_RLC_bit = 1 << 27,
READ_ERROR_bit = 1 << 31,
SRBM_INT_STATUS = 0x0ea4,
RDERR_INT_STAT_bit = 1 << 0,
GFX_CNTX_SWITCH_INT_STAT_bit = 1 << 1,
SRBM_INT_ACK = 0x0ea8,
RDERR_INT_ACK_bit = 1 << 0,
GFX_CNTX_SWITCH_INT_ACK_bit = 1 << 1,
/* R6XX_MC_VM_FB_LOCATION = 0x2180, */
VENDOR_DEVICE_ID = 0x4000,
HDP_MEM_COHERENCY_FLUSH_CNTL = 0x5480,
/* D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110, */
/* D1GRPH_PITCH = 0x6120, */
/* D1GRPH_Y_END = 0x6138, */
GRBM_STATUS = 0x8010,
R600_CMDFIFO_AVAIL_mask = 0x1f << 0,
R700_CMDFIFO_AVAIL_mask = 0xf << 0,
CMDFIFO_AVAIL_shift = 0,
SRBM_RQ_PENDING_bit = 1 << 5,
CP_RQ_PENDING_bit = 1 << 6,
CF_RQ_PENDING_bit = 1 << 7,
PF_RQ_PENDING_bit = 1 << 8,
GRBM_EE_BUSY_bit = 1 << 10,
GRBM_STATUS__VC_BUSY_bit = 1 << 11,
DB03_CLEAN_bit = 1 << 12,
CB03_CLEAN_bit = 1 << 13,
VGT_BUSY_NO_DMA_bit = 1 << 16,
GRBM_STATUS__VGT_BUSY_bit = 1 << 17,
TA03_BUSY_bit = 1 << 18,
GRBM_STATUS__TC_BUSY_bit = 1 << 19,
SX_BUSY_bit = 1 << 20,
SH_BUSY_bit = 1 << 21,
SPI03_BUSY_bit = 1 << 22,
SMX_BUSY_bit = 1 << 23,
SC_BUSY_bit = 1 << 24,
PA_BUSY_bit = 1 << 25,
DB03_BUSY_bit = 1 << 26,
CR_BUSY_bit = 1 << 27,
CP_COHERENCY_BUSY_bit = 1 << 28,
GRBM_STATUS__CP_BUSY_bit = 1 << 29,
CB03_BUSY_bit = 1 << 30,
GUI_ACTIVE_bit = 1 << 31,
GRBM_STATUS2 = 0x8014,
CR_CLEAN_bit = 1 << 0,
SMX_CLEAN_bit = 1 << 1,
SPI0_BUSY_bit = 1 << 8,
SPI1_BUSY_bit = 1 << 9,
SPI2_BUSY_bit = 1 << 10,
SPI3_BUSY_bit = 1 << 11,
TA0_BUSY_bit = 1 << 12,
TA1_BUSY_bit = 1 << 13,
TA2_BUSY_bit = 1 << 14,
TA3_BUSY_bit = 1 << 15,
DB0_BUSY_bit = 1 << 16,
DB1_BUSY_bit = 1 << 17,
DB2_BUSY_bit = 1 << 18,
DB3_BUSY_bit = 1 << 19,
CB0_BUSY_bit = 1 << 20,
CB1_BUSY_bit = 1 << 21,
CB2_BUSY_bit = 1 << 22,
CB3_BUSY_bit = 1 << 23,
GRBM_SOFT_RESET = 0x8020,
SOFT_RESET_CP_bit = 1 << 0,
SOFT_RESET_CB_bit = 1 << 1,
SOFT_RESET_CR_bit = 1 << 2,
SOFT_RESET_DB_bit = 1 << 3,
SOFT_RESET_PA_bit = 1 << 5,
SOFT_RESET_SC_bit = 1 << 6,
SOFT_RESET_SMX_bit = 1 << 7,
SOFT_RESET_SPI_bit = 1 << 8,
SOFT_RESET_SH_bit = 1 << 9,
SOFT_RESET_SX_bit = 1 << 10,
SOFT_RESET_TC_bit = 1 << 11,
SOFT_RESET_TA_bit = 1 << 12,
SOFT_RESET_VC_bit = 1 << 13,
SOFT_RESET_VGT_bit = 1 << 14,
SOFT_RESET_GRBM_GCA_bit = 1 << 15,
WAIT_UNTIL = 0x8040,
WAIT_CP_DMA_IDLE_bit = 1 << 8,
WAIT_CMDFIFO_bit = 1 << 10,
WAIT_2D_IDLE_bit = 1 << 14,
WAIT_3D_IDLE_bit = 1 << 15,
WAIT_2D_IDLECLEAN_bit = 1 << 16,
WAIT_3D_IDLECLEAN_bit = 1 << 17,
WAIT_EXTERN_SIG_bit = 1 << 19,
CMDFIFO_ENTRIES_mask = 0x1f << 20,
CMDFIFO_ENTRIES_shift = 20,
GRBM_READ_ERROR = 0x8058,
/* READ_ADDRESS_mask = 0xffff << 2, */
/* READ_ADDRESS_shift = 2, */
READ_REQUESTER_SRBM_bit = 1 << 28,
READ_REQUESTER_CP_bit = 1 << 29,
READ_REQUESTER_WU_POLL_bit = 1 << 30,
/* READ_ERROR_bit = 1 << 31, */
SCRATCH_REG0 = 0x8500,
SCRATCH_REG1 = 0x8504,
SCRATCH_REG2 = 0x8508,
SCRATCH_REG3 = 0x850c,
SCRATCH_REG4 = 0x8510,
SCRATCH_REG5 = 0x8514,
SCRATCH_REG6 = 0x8518,
SCRATCH_REG7 = 0x851c,
SCRATCH_UMSK = 0x8540,
SCRATCH_ADDR = 0x8544,
CP_COHER_CNTL = 0x85f0,
DEST_BASE_0_ENA_bit = 1 << 0,
DEST_BASE_1_ENA_bit = 1 << 1,
SO0_DEST_BASE_ENA_bit = 1 << 2,
SO1_DEST_BASE_ENA_bit = 1 << 3,
SO2_DEST_BASE_ENA_bit = 1 << 4,
SO3_DEST_BASE_ENA_bit = 1 << 5,
CB0_DEST_BASE_ENA_bit = 1 << 6,
CB1_DEST_BASE_ENA_bit = 1 << 7,
CB2_DEST_BASE_ENA_bit = 1 << 8,
CB3_DEST_BASE_ENA_bit = 1 << 9,
CB4_DEST_BASE_ENA_bit = 1 << 10,
CB5_DEST_BASE_ENA_bit = 1 << 11,
CB6_DEST_BASE_ENA_bit = 1 << 12,
CB7_DEST_BASE_ENA_bit = 1 << 13,
DB_DEST_BASE_ENA_bit = 1 << 14,
CR_DEST_BASE_ENA_bit = 1 << 15,
TC_ACTION_ENA_bit = 1 << 23,
VC_ACTION_ENA_bit = 1 << 24,
CB_ACTION_ENA_bit = 1 << 25,
DB_ACTION_ENA_bit = 1 << 26,
SH_ACTION_ENA_bit = 1 << 27,
SMX_ACTION_ENA_bit = 1 << 28,
CR0_ACTION_ENA_bit = 1 << 29,
CR1_ACTION_ENA_bit = 1 << 30,
CR2_ACTION_ENA_bit = 1 << 31,
CP_COHER_SIZE = 0x85f4,
CP_COHER_BASE = 0x85f8,
CP_COHER_STATUS = 0x85fc,
MATCHING_GFX_CNTX_mask = 0xff << 0,
MATCHING_GFX_CNTX_shift = 0,
MATCHING_CR_CNTX_mask = 0xffff << 8,
MATCHING_CR_CNTX_shift = 8,
STATUS_bit = 1 << 31,
CP_STALLED_STAT1 = 0x8674,
RBIU_TO_DMA_NOT_RDY_TO_RCV_bit = 1 << 0,
RBIU_TO_IBS_NOT_RDY_TO_RCV_bit = 1 << 1,
RBIU_TO_SEM_NOT_RDY_TO_RCV_bit = 1 << 2,
RBIU_TO_2DREGS_NOT_RDY_TO_RCV_bit = 1 << 3,
RBIU_TO_MEMWR_NOT_RDY_TO_RCV_bit = 1 << 4,
RBIU_TO_MEMRD_NOT_RDY_TO_RCV_bit = 1 << 5,
RBIU_TO_EOPD_NOT_RDY_TO_RCV_bit = 1 << 6,
RBIU_TO_RECT_NOT_RDY_TO_RCV_bit = 1 << 7,
RBIU_TO_STRMO_NOT_RDY_TO_RCV_bit = 1 << 8,
RBIU_TO_PSTAT_NOT_RDY_TO_RCV_bit = 1 << 9,
MIU_WAITING_ON_RDREQ_FREE_bit = 1 << 16,
MIU_WAITING_ON_WRREQ_FREE_bit = 1 << 17,
MIU_NEEDS_AVAIL_WRREQ_PHASE_bit = 1 << 18,
RCIU_WAITING_ON_GRBM_FREE_bit = 1 << 24,
RCIU_WAITING_ON_VGT_FREE_bit = 1 << 25,
RCIU_STALLED_ON_ME_READ_bit = 1 << 26,
RCIU_STALLED_ON_DMA_READ_bit = 1 << 27,
RCIU_HALTED_BY_REG_VIOLATION_bit = 1 << 28,
CP_STALLED_STAT2 = 0x8678,
PFP_TO_CSF_NOT_RDY_TO_RCV_bit = 1 << 0,
PFP_TO_MEQ_NOT_RDY_TO_RCV_bit = 1 << 1,
PFP_TO_VGT_NOT_RDY_TO_RCV_bit = 1 << 2,
PFP_HALTED_BY_INSTR_VIOLATION_bit = 1 << 3,
MULTIPASS_IB_PENDING_IN_PFP_bit = 1 << 4,
ME_BRUSH_WC_NOT_RDY_TO_RCV_bit = 1 << 8,
ME_STALLED_ON_BRUSH_LOGIC_bit = 1 << 9,
CR_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 10,
GFX_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 11,
ME_RCIU_NOT_RDY_TO_RCV_bit = 1 << 12,
ME_TO_CONST_NOT_RDY_TO_RCV_bit = 1 << 13,
ME_WAITING_DATA_FROM_PFP_bit = 1 << 14,
ME_WAITING_ON_PARTIAL_FLUSH_bit = 1 << 15,
RECT_FIFO_NEEDS_CR_RECT_DONE_bit = 1 << 16,
RECT_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 17,
EOPD_FIFO_NEEDS_SC_EOP_DONE_bit = 1 << 18,
EOPD_FIFO_NEEDS_SMX_EOP_DONE_bit = 1 << 19,
EOPD_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 20,
EOPD_FIFO_NEEDS_SIGNAL_SEM_bit = 1 << 21,
SO_NUMPRIM_FIFO_NEEDS_SOADDR_bit = 1 << 22,
SO_NUMPRIM_FIFO_NEEDS_NUMPRIM_bit = 1 << 23,
PIPE_STATS_FIFO_NEEDS_SAMPLE_bit = 1 << 24,
SURF_SYNC_NEEDS_IDLE_CNTXS_bit = 1 << 30,
SURF_SYNC_NEEDS_ALL_CLEAN_bit = 1 << 31,
CP_BUSY_STAT = 0x867c,
REG_BUS_FIFO_BUSY_bit = 1 << 0,
RING_FETCHING_DATA_bit = 1 << 1,
INDR1_FETCHING_DATA_bit = 1 << 2,
INDR2_FETCHING_DATA_bit = 1 << 3,
STATE_FETCHING_DATA_bit = 1 << 4,
PRED_FETCHING_DATA_bit = 1 << 5,
COHER_CNTR_NEQ_ZERO_bit = 1 << 6,
PFP_PARSING_PACKETS_bit = 1 << 7,
ME_PARSING_PACKETS_bit = 1 << 8,
RCIU_PFP_BUSY_bit = 1 << 9,
RCIU_ME_BUSY_bit = 1 << 10,
OUTSTANDING_READ_TAGS_bit = 1 << 11,
SEM_CMDFIFO_NOT_EMPTY_bit = 1 << 12,
SEM_FAILED_AND_HOLDING_bit = 1 << 13,
SEM_POLLING_FOR_PASS_bit = 1 << 14,
_3D_BUSY_bit = 1 << 15,
_2D_BUSY_bit = 1 << 16,
CP_STAT = 0x8680,
CSF_RING_BUSY_bit = 1 << 0,
CSF_WPTR_POLL_BUSY_bit = 1 << 1,
CSF_INDIRECT1_BUSY_bit = 1 << 2,
CSF_INDIRECT2_BUSY_bit = 1 << 3,
CSF_STATE_BUSY_bit = 1 << 4,
CSF_PREDICATE_BUSY_bit = 1 << 5,
CSF_BUSY_bit = 1 << 6,
MIU_RDREQ_BUSY_bit = 1 << 7,
MIU_WRREQ_BUSY_bit = 1 << 8,
ROQ_RING_BUSY_bit = 1 << 9,
ROQ_INDIRECT1_BUSY_bit = 1 << 10,
ROQ_INDIRECT2_BUSY_bit = 1 << 11,
ROQ_STATE_BUSY_bit = 1 << 12,
ROQ_PREDICATE_BUSY_bit = 1 << 13,
ROQ_ALIGN_BUSY_bit = 1 << 14,
PFP_BUSY_bit = 1 << 15,
MEQ_BUSY_bit = 1 << 16,
ME_BUSY_bit = 1 << 17,
QUERY_BUSY_bit = 1 << 18,
SEMAPHORE_BUSY_bit = 1 << 19,
INTERRUPT_BUSY_bit = 1 << 20,
SURFACE_SYNC_BUSY_bit = 1 << 21,
DMA_BUSY_bit = 1 << 22,
RCIU_BUSY_bit = 1 << 23,
CP_STAT__CP_BUSY_bit = 1 << 31,
CP_ME_CNTL = 0x86d8,
ME_STATMUX_mask = 0xff << 0,
ME_STATMUX_shift = 0,
ME_HALT_bit = 1 << 28,
CP_ME_STATUS = 0x86dc,
CP_RB_RPTR = 0x8700,
RB_RPTR_mask = 0xfffff << 0,
RB_RPTR_shift = 0,
CP_RB_WPTR_DELAY = 0x8704,
PRE_WRITE_TIMER_mask = 0xfffffff << 0,
PRE_WRITE_TIMER_shift = 0,
PRE_WRITE_LIMIT_mask = 0x0f << 28,
PRE_WRITE_LIMIT_shift = 28,
CP_ROQ_RB_STAT = 0x8780,
ROQ_RPTR_PRIMARY_mask = 0x3ff << 0,
ROQ_RPTR_PRIMARY_shift = 0,
ROQ_WPTR_PRIMARY_mask = 0x3ff << 16,
ROQ_WPTR_PRIMARY_shift = 16,
CP_ROQ_IB1_STAT = 0x8784,
ROQ_RPTR_INDIRECT1_mask = 0x3ff << 0,
ROQ_RPTR_INDIRECT1_shift = 0,
ROQ_WPTR_INDIRECT1_mask = 0x3ff << 16,
ROQ_WPTR_INDIRECT1_shift = 16,
CP_ROQ_IB2_STAT = 0x8788,
ROQ_RPTR_INDIRECT2_mask = 0x3ff << 0,
ROQ_RPTR_INDIRECT2_shift = 0,
ROQ_WPTR_INDIRECT2_mask = 0x3ff << 16,
ROQ_WPTR_INDIRECT2_shift = 16,
CP_MEQ_STAT = 0x8794,
MEQ_RPTR_mask = 0x3ff << 0,
MEQ_RPTR_shift = 0,
MEQ_WPTR_mask = 0x3ff << 16,
MEQ_WPTR_shift = 16,
CC_GC_SHADER_PIPE_CONFIG = 0x8950,
INACTIVE_QD_PIPES_mask = 0xff << 8,
INACTIVE_QD_PIPES_shift = 8,
R6XX_MAX_QD_PIPES = 8,
INACTIVE_SIMDS_mask = 0xff << 16,
INACTIVE_SIMDS_shift = 16,
R6XX_MAX_SIMDS = 8,
GC_USER_SHADER_PIPE_CONFIG = 0x8954,
VC_ENHANCE = 0x9714,
DB_DEBUG = 0x9830,
PREZ_MUST_WAIT_FOR_POSTZ_DONE = 1 << 31,
DB_WATERMARKS = 0x00009838,
DEPTH_FREE_mask = 0x1f << 0,
DEPTH_FREE_shift = 0,
DEPTH_FLUSH_mask = 0x3f << 5,
DEPTH_FLUSH_shift = 5,
FORCE_SUMMARIZE_mask = 0x0f << 11,
FORCE_SUMMARIZE_shift = 11,
DEPTH_PENDING_FREE_mask = 0x1f << 15,
DEPTH_PENDING_FREE_shift = 15,
DEPTH_CACHELINE_FREE_mask = 0x1f << 20,
DEPTH_CACHELINE_FREE_shift = 20,
EARLY_Z_PANIC_DISABLE_bit = 1 << 25,
LATE_Z_PANIC_DISABLE_bit = 1 << 26,
RE_Z_PANIC_DISABLE_bit = 1 << 27,
DB_EXTRA_DEBUG_mask = 0x0f << 28,
DB_EXTRA_DEBUG_shift = 28,
CP_RB_BASE = 0xc100,
CP_RB_CNTL = 0xc104,
RB_BUFSZ_mask = 0x3f << 0,
CP_RB_WPTR = 0xc114,
RB_WPTR_mask = 0xfffff << 0,
RB_WPTR_shift = 0,
CP_RB_RPTR_WR = 0xc108,
RB_RPTR_WR_mask = 0xfffff << 0,
RB_RPTR_WR_shift = 0,
CP_INT_STATUS = 0xc128,
DISABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 0,
ENABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 1,
SEM_SIGNAL_INT_STAT_bit = 1 << 18,
CNTX_BUSY_INT_STAT_bit = 1 << 19,
CNTX_EMPTY_INT_STAT_bit = 1 << 20,
WAITMEM_SEM_INT_STAT_bit = 1 << 21,
PRIV_INSTR_INT_STAT_bit = 1 << 22,
PRIV_REG_INT_STAT_bit = 1 << 23,
OPCODE_ERROR_INT_STAT_bit = 1 << 24,
SCRATCH_INT_STAT_bit = 1 << 25,
TIME_STAMP_INT_STAT_bit = 1 << 26,
RESERVED_BIT_ERROR_INT_STAT_bit = 1 << 27,
DMA_INT_STAT_bit = 1 << 28,
IB2_INT_STAT_bit = 1 << 29,
IB1_INT_STAT_bit = 1 << 30,
RB_INT_STAT_bit = 1 << 31,
/* SX_ALPHA_TEST_CONTROL = 0x00028410, */
ALPHA_FUNC__REF_NEVER = 0,
ALPHA_FUNC__REF_ALWAYS = 7,
/* DB_SHADER_CONTROL = 0x0002880c, */
Z_ORDER__EARLY_Z_THEN_LATE_Z = 2,
/* PA_SU_SC_MODE_CNTL = 0x00028814, */
/* POLY_MODE_mask = 0x03 << 3, */
POLY_MODE__TRIANGLES = 0, POLY_MODE__DUAL_MODE,
/* POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, */
POLYMODE_PTYPE__POINTS = 0, POLYMODE_PTYPE__LINES, POLYMODE_PTYPE__TRIANGLES,
PA_SC_AA_SAMPLE_LOCS_8S_WD1_M = 0x00028c20,
DB_SRESULTS_COMPARE_STATE0 = 0x00028d28, /* See autoregs: DB_SRESULTS_COMPARE_STATE1 */
/* DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c, */
DB_ALPHA_TO_MASK = 0x00028d44,
ALPHA_TO_MASK_ENABLE = 1 << 0,
ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8,
ALPHA_TO_MASK_OFFSET0_shift = 8,
ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 8,
ALPHA_TO_MASK_OFFSET1_shift = 10,
ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 8,
ALPHA_TO_MASK_OFFSET2_shift = 12,
ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 8,
ALPHA_TO_MASK_OFFSET3_shift = 14,
/* SQ_VTX_CONSTANT_WORD2_0 = 0x00038008, */
/* SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, */
FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2,
FMT_16=5, FMT_16_FLOAT, FMT_8_8,
FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4,
FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16,
FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8,
FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10,
FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2,
FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16,
FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT,
FMT_1 = 37, FMT_GB_GR=39,
FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP,
FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32,
FMT_32_32_32_FLOAT=48,
/* High level register file lengths */
SQ_ALU_CONSTANT = SQ_ALU_CONSTANT0_0, /* 256 PS, 256 VS */
SQ_ALU_CONSTANT_ps_num = 256,
SQ_ALU_CONSTANT_vs_num = 256,
SQ_ALU_CONSTANT_all_num = 512,
SQ_ALU_CONSTANT_offset = 16,
SQ_ALU_CONSTANT_ps = 0,
SQ_ALU_CONSTANT_vs = SQ_ALU_CONSTANT_ps + SQ_ALU_CONSTANT_ps_num,
SQ_TEX_RESOURCE = SQ_TEX_RESOURCE_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */
SQ_TEX_RESOURCE_ps_num = 160,
SQ_TEX_RESOURCE_vs_num = 160,
SQ_TEX_RESOURCE_fs_num = 16,
SQ_TEX_RESOURCE_gs_num = 160,
SQ_TEX_RESOURCE_all_num = 496,
SQ_TEX_RESOURCE_offset = 28,
SQ_TEX_RESOURCE_ps = 0,
SQ_TEX_RESOURCE_vs = SQ_TEX_RESOURCE_ps + SQ_TEX_RESOURCE_ps_num,
SQ_TEX_RESOURCE_fs = SQ_TEX_RESOURCE_vs + SQ_TEX_RESOURCE_vs_num,
SQ_TEX_RESOURCE_gs = SQ_TEX_RESOURCE_fs + SQ_TEX_RESOURCE_fs_num,
SQ_VTX_RESOURCE = SQ_VTX_CONSTANT_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */
SQ_VTX_RESOURCE_ps_num = 160,
SQ_VTX_RESOURCE_vs_num = 160,
SQ_VTX_RESOURCE_fs_num = 16,
SQ_VTX_RESOURCE_gs_num = 160,
SQ_VTX_RESOURCE_all_num = 496,
SQ_VTX_RESOURCE_offset = 28,
SQ_VTX_RESOURCE_ps = 0,
SQ_VTX_RESOURCE_vs = SQ_VTX_RESOURCE_ps + SQ_VTX_RESOURCE_ps_num,
SQ_VTX_RESOURCE_fs = SQ_VTX_RESOURCE_vs + SQ_VTX_RESOURCE_vs_num,
SQ_VTX_RESOURCE_gs = SQ_VTX_RESOURCE_fs + SQ_VTX_RESOURCE_fs_num,
SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0, /* 18 per PS, VS, GS */
SQ_TEX_SAMPLER_WORD_ps_num = 18,
SQ_TEX_SAMPLER_WORD_vs_num = 18,
SQ_TEX_SAMPLER_WORD_gs_num = 18,
SQ_TEX_SAMPLER_WORD_all_num = 54,
SQ_TEX_SAMPLER_WORD_offset = 12,
SQ_TEX_SAMPLER_WORD_ps = 0,
SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num,
SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num,
SQ_LOOP_CONST = SQ_LOOP_CONST_0, /* 32 per PS, VS, GS */
SQ_LOOP_CONST_ps_num = 32,
SQ_LOOP_CONST_vs_num = 32,
SQ_LOOP_CONST_gs_num = 32,
SQ_LOOP_CONST_all_num = 96,
SQ_LOOP_CONST_offset = 4,
SQ_LOOP_CONST_ps = 0,
SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num,
SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num,
SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits per PS, VS, GS */
SQ_BOOL_CONST_ps_num = 1,
SQ_BOOL_CONST_vs_num = 1,
SQ_BOOL_CONST_gs_num = 1,
SQ_BOOL_CONST_all_num = 3,
SQ_BOOL_CONST_offset = 4,
SQ_BOOL_CONST_ps = 0,
SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num,
SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num
};
#endif
headers/private/graphics/radeon_hd/r600_reg_r7xx.h
-149
View File
@@ -1,149 +0,0 @@
/*
* RadeonHD R6xx, R7xx Register documentation
*
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
* Copyright (C) 2008-2009 Matthias Hopf
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _R600_REG_R7xx_H_
#define _R600_REG_R7xx_H_
/*
* Register update for R7xx chips
*/
enum {
/* R7XX_MC_VM_FB_LOCATION = 0x00002024, */
/* GRBM_STATUS = 0x00008010, */
R7XX_TA_BUSY_bit = 1 << 14,
R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x00008d8c,
RING0_OFFSET_mask = 0xff << 0,
RING0_OFFSET_shift = 0,
ISOLATE_ES_ENABLE_bit = 1 << 12,
ISOLATE_GS_ENABLE_bit = 1 << 13,
VS_PC_LIMIT_ENABLE_bit = 1 << 14,
/* SQ_ALU_WORD0 = 0x00008dfc, */
/* SRC0_SEL_mask = 0x1ff << 0, */
/* SRC1_SEL_mask = 0x1ff << 13, */
R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4,
R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5,
R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6,
R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7,
/* INDEX_MODE_mask = 0x07 << 26, */
R7xx_SQ_INDEX_GLOBAL = 0x05,
R7xx_SQ_INDEX_GLOBAL_AR_X = 0x06,
R6xx_SQ_ALU_WORD1_OP2 = 0x00008dfc,
R7xx_SQ_ALU_WORD1_OP2_V2 = 0x00008dfc,
R6xx_FOG_MERGE_bit = 1 << 5,
R6xx_OMOD_mask = 0x03 << 6,
R7xx_OMOD_mask = 0x03 << 5,
R6xx_OMOD_shift = 6,
R7xx_OMOD_shift = 5,
R6xx_SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x3ff << 8,
R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_mask = 0x7ff << 7,
R6xx_SQ_ALU_WORD1_OP2__ALU_INST_shift = 8,
R7xx_SQ_ALU_WORD1_OP2_V2__ALU_INST_shift = 7,
R7xx_SQ_OP2_INST_FREXP_64 = 0x07,
R7xx_SQ_OP2_INST_ADD_64 = 0x17,
R7xx_SQ_OP2_INST_MUL_64 = 0x1b,
R7xx_SQ_OP2_INST_FLT64_TO_FLT32 = 0x1c,
R7xx_SQ_OP2_INST_FLT32_TO_FLT64 = 0x1d,
R7xx_SQ_OP2_INST_LDEXP_64 = 0x7a,
R7xx_SQ_OP2_INST_FRACT_64 = 0x7b,
R7xx_SQ_OP2_INST_PRED_SETGT_64 = 0x7c,
R7xx_SQ_OP2_INST_PRED_SETE_64 = 0x7d,
R7xx_SQ_OP2_INST_PRED_SETGE_64 = 0x7e,
/* SQ_ALU_WORD1_OP3 = 0x00008dfc, */
/* SRC2_SEL_mask = 0x1ff << 0, */
/* R7xx_SQ_ALU_SRC_1_DBL_L = 0xf4, */
/* R7xx_SQ_ALU_SRC_1_DBL_M = 0xf5, */
/* R7xx_SQ_ALU_SRC_0_5_DBL_L = 0xf6, */
/* R7xx_SQ_ALU_SRC_0_5_DBL_M = 0xf7, */
/* SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13, */
R7xx_SQ_OP3_INST_MULADD_64 = 0x08,
R7xx_SQ_OP3_INST_MULADD_64_M2 = 0x09,
R7xx_SQ_OP3_INST_MULADD_64_M4 = 0x0a,
R7xx_SQ_OP3_INST_MULADD_64_D2 = 0x0b,
/* SQ_CF_ALU_WORD1 = 0x00008dfc, */
R6xx_USES_WATERFALL_bit = 1 << 25,
R7xx_SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25,
/* SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc, */
/* ARRAY_BASE_mask = 0x1fff << 0, */
/* TYPE_mask = 0x03 << 13, */
/* SQ_EXPORT_PARAM = 0x02, */
/* X_UNUSED_FOR_SX_EXPORTS = 0x03, */
/* ELEM_SIZE_mask = 0x03 << 30, */
/* SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc, */
/* SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0x7f << 23, */
R7xx_SQ_CF_INST_MEM_EXPORT = 0x3a,
/* SQ_CF_WORD1 = 0x00008dfc, */
/* SQ_CF_WORD1__COUNT_mask = 0x07 << 10, */
R7xx_COUNT_3_bit = 1 << 19,
/* SQ_CF_WORD1__CF_INST_mask = 0x7f << 23, */
R7xx_SQ_CF_INST_END_PROGRAM = 0x19,
R7xx_SQ_CF_INST_WAIT_ACK = 0x1a,
R7xx_SQ_CF_INST_TEX_ACK = 0x1b,
R7xx_SQ_CF_INST_VTX_ACK = 0x1c,
R7xx_SQ_CF_INST_VTX_TC_ACK = 0x1d,
/* SQ_VTX_WORD0 = 0x00008dfc, */
/* VTX_INST_mask = 0x1f << 0, */
R7xx_SQ_VTX_INST_MEM = 0x02,
/* SQ_VTX_WORD2 = 0x00008dfc, */
R7xx_SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20,
/* SQ_TEX_WORD0 = 0x00008dfc, */
/* TEX_INST_mask = 0x1f << 0, */
R7xx_X_MEMORY_READ = 0x02,
R7xx_SQ_TEX_INST_KEEP_GRADIENTS = 0x0a,
R7xx_X_FETCH4_LOAD4_INSTRUCTION_FOR_DX10_1 = 0x0f,
R7xx_SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24,
R7xx_PA_SC_EDGERULE = 0x00028230,
R7xx_SPI_THREAD_GROUPING = 0x000286c8,
PS_GROUPING_mask = 0x1f << 0,
PS_GROUPING_shift = 0,
VS_GROUPING_mask = 0x1f << 8,
VS_GROUPING_shift = 8,
GS_GROUPING_mask = 0x1f << 16,
GS_GROUPING_shift = 16,
ES_GROUPING_mask = 0x1f << 24,
ES_GROUPING_shift = 24,
R7xx_CB_SHADER_CONTROL = 0x000287a0,
RT0_ENABLE_bit = 1 << 0,
RT1_ENABLE_bit = 1 << 1,
RT2_ENABLE_bit = 1 << 2,
RT3_ENABLE_bit = 1 << 3,
RT4_ENABLE_bit = 1 << 4,
RT5_ENABLE_bit = 1 << 5,
RT6_ENABLE_bit = 1 << 6,
RT7_ENABLE_bit = 1 << 7,
/* DB_ALPHA_TO_MASK = 0x00028d44, */
R7xx_OFFSET_ROUND_bit = 1 << 16,
/* SQ_TEX_SAMPLER_MISC_0 = 0x0003d03c, */
R7xx_TRUNCATE_COORD_bit = 1 << 9,
R7xx_DISABLE_CUBE_WRAP_bit = 1 << 10
} ;
#endif /* _R600_REG_R7xx_H_ */
src/add-ons/accelerants/radeon_hd/Jamfile
+1 -1
View File
@@ -11,11 +11,11 @@ UsePrivateHeaders [ FDirName graphics common ] ;
Addon radeon_hd.accelerant :
atom.cpp
gpu.cpp
accelerant.cpp
engine.cpp
hooks.cpp
pll.cpp
mc.cpp
dac.cpp
display.cpp
tmds.cpp
src/add-ons/accelerants/radeon_hd/accelerant.cpp
+1 -1
View File
@@ -13,7 +13,7 @@
#include "bios.h"
#include "display.h"
#include "mc.h"
#include "gpu.h"
#include "pll.h"
#include "utility.h"
src/add-ons/accelerants/radeon_hd/bios.cpp
+4
View File
@@ -110,6 +110,10 @@ radeon_init_bios(uint8* bios)
radeon_bios_init_scratch();
atom_allocate_fb_scratch(gAtomContext);
// TODO : this is only *required* on cards <= r500
// is it ok to run on cards > r500 before asic_init?
radeon_gpu_reset();
atom_asic_init(gAtomContext);
// Post card
src/add-ons/accelerants/radeon_hd/gpu.cpp
+217
View File
@@ -0,0 +1,217 @@
/*
* Copyright 2006-2011, Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License.
*
* Authors:
* Alexander von Gluck, kallisti5@unixzen.com
*/
#include "accelerant_protos.h"
#include "accelerant.h"
#include "utility.h"
#include "gpu.h"
#include <Debug.h>
#undef TRACE
#define TRACE_GPU
#ifdef TRACE_GPU
# define TRACE(x...) _sPrintf("radeon_hd: " x)
#else
# define TRACE(x...) ;
#endif
#define ERROR(x...) _sPrintf("radeon_hd: " x)
status_t
radeon_gpu_reset()
{
radeon_shared_info &info = *gInfo->shared_info;
// Read GRBM Command Processor status
if (!(Read32(OUT, GRBM_STATUS) & GUI_ACTIVE))
return B_ERROR;
TRACE("%s: GPU software reset in progress...\n", __func__);
// TODO : mc stop
if (radeon_gpu_mc_idle() > 0) {
ERROR("%s: Timeout waiting for MC to idle!\n", __func__);
}
if (info.device_chipset < RADEON_R1000) {
Write32(OUT, CP_ME_CNTL, CP_ME_HALT);
// Disable Command Processor parsing / prefetching
// Register busy masks for early Radeon HD cards
// GRBM Command Processor Status
uint32 grbm_busy_mask = VC_BUSY;
// Vertex Cache Busy
grbm_busy_mask |= VGT_BUSY_NO_DMA | VGT_BUSY;
// Vertex Grouper Tessellator Busy
grbm_busy_mask |= TA03_BUSY;
// unknown
grbm_busy_mask |= TC_BUSY;
// Texture Cache Busy
grbm_busy_mask |= SX_BUSY;
// Shader Export Busy
grbm_busy_mask |= SH_BUSY;
// Sequencer Instruction Cache Busy
grbm_busy_mask |= SPI_BUSY;
// Shader Processor Interpolator Busy
grbm_busy_mask |= SMX_BUSY;
// Shader Memory Exchange
grbm_busy_mask |= SC_BUSY;
// Scan Converter Busy
grbm_busy_mask |= PA_BUSY;
// Primitive Assembler Busy
grbm_busy_mask |= DB_BUSY;
// Depth Block Busy
grbm_busy_mask |= CR_BUSY;
// unknown
grbm_busy_mask |= CB_BUSY;
// Color Block Busy
grbm_busy_mask |= GUI_ACTIVE;
// unknown (graphics pipeline active?)
// GRBM Command Processor Detailed Status
uint32 grbm2_busy_mask = SPI0_BUSY | SPI1_BUSY | SPI2_BUSY | SPI3_BUSY;
// Shader Processor Interpolator 0 - 3 Busy
grbm2_busy_mask |= TA0_BUSY | TA1_BUSY | TA2_BUSY | TA3_BUSY;
// unknown 0 - 3 Busy
grbm2_busy_mask |= DB0_BUSY | DB1_BUSY | DB2_BUSY | DB3_BUSY;
// Depth Block 0 - 3 Busy
grbm2_busy_mask |= CB0_BUSY | CB1_BUSY | CB2_BUSY | CB3_BUSY;
// Color Block 0 - 3 Busy
uint32 tmp;
/* Check if any of the rendering block is busy and reset it */
if ((Read32(OUT, GRBM_STATUS) & grbm_busy_mask)
|| (Read32(OUT, GRBM_STATUS2) & grbm2_busy_mask)) {
tmp = SOFT_RESET_CR
| SOFT_RESET_DB
| SOFT_RESET_CB
| SOFT_RESET_PA
| SOFT_RESET_SC
| SOFT_RESET_SMX
| SOFT_RESET_SPI
| SOFT_RESET_SX
| SOFT_RESET_SH
| SOFT_RESET_TC
| SOFT_RESET_TA
| SOFT_RESET_VC
| SOFT_RESET_VGT;
Write32(OUT, GRBM_SOFT_RESET, tmp);
Read32(OUT, GRBM_SOFT_RESET);
snooze(15000);
Write32(OUT, GRBM_SOFT_RESET, 0);
}
// Reset CP
tmp = SOFT_RESET_CP;
Write32(OUT, GRBM_SOFT_RESET, tmp);
Read32(OUT, GRBM_SOFT_RESET);
snooze(15000);
Write32(OUT, GRBM_SOFT_RESET, 0);
// Let things settle
snooze(1000);
} else {
// Northern Islands and higher
Write32(OUT, CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
// Disable Command Processor parsing / prefetching
// reset the graphics pipeline components
uint32 grbm_reset = (SOFT_RESET_CP
| SOFT_RESET_CB
| SOFT_RESET_DB
| SOFT_RESET_GDS
| SOFT_RESET_PA
| SOFT_RESET_SC
| SOFT_RESET_SPI
| SOFT_RESET_SH
| SOFT_RESET_SX
| SOFT_RESET_TC
| SOFT_RESET_TA
| SOFT_RESET_VGT
| SOFT_RESET_IA);
Write32(OUT, GRBM_SOFT_RESET, grbm_reset);
Read32(OUT, GRBM_SOFT_RESET);
snooze(50);
Write32(OUT, GRBM_SOFT_RESET, 0);
Read32(OUT, GRBM_SOFT_RESET);
snooze(50);
}
// TODO : mc resume
return B_OK;
}
uint32
radeon_gpu_mc_idle()
{
uint32 idleStatus;
if (!((idleStatus = Read32(MC, SRBM_STATUS)) &
(VMC_BUSY | MCB_BUSY |
MCDZ_BUSY | MCDY_BUSY | MCDX_BUSY | MCDW_BUSY)))
return 0;
return idleStatus;
}
status_t
radeon_gpu_mc_setup()
{
uint32 fb_location_int = gInfo->shared_info->frame_buffer_int;
uint32 fb_location = Read32(OUT, R6XX_MC_VM_FB_LOCATION);
uint16 fb_size = (fb_location >> 16) - (fb_location & 0xFFFF);
uint32 fb_location_tmp = fb_location_int >> 24;
fb_location_tmp |= (fb_location_tmp + fb_size) << 16;
uint32 fb_offset_tmp = (fb_location_int >> 8) & 0xff0000;
uint32 idleState = radeon_gpu_mc_idle();
if (idleState > 0) {
TRACE("%s: Cannot modify non-idle MC! idleState: 0x%" B_PRIX32 "\n",
__func__, idleState);
return B_ERROR;
}
TRACE("%s: Setting frame buffer from 0x%" B_PRIX32
" to 0x%" B_PRIX32 " [size 0x%" B_PRIX16 "]\n",
__func__, fb_location, fb_location_tmp, fb_size);
// The MC Write32 will handle cards needing a special MC read/write register
Write32(MC, R6XX_MC_VM_FB_LOCATION, fb_location_tmp);
Write32(MC, R6XX_HDP_NONSURFACE_BASE, fb_offset_tmp);
return B_OK;
}
status_t
radeon_gpu_irq_setup()
{
// TODO : Stub for IRQ setup
// allocate rings via r600_ih_ring_alloc
// disable irq's via r600_disable_interrupts
// r600_rlc_init
// setup interrupt control
return B_ERROR;
}
src/add-ons/accelerants/radeon_hd/gpu.h
+168
View File
@@ -0,0 +1,168 @@
/*
* Copyright 2006-2011, Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License.
*
* Authors:
* Alexander von Gluck, kallisti5@unixzen.com
*/
#ifndef RADEON_HD_MC_H
#define RADEON_HD_MC_H
// GPU Control registers. These are combined as
// the registers exist on all models, some flags
// are different though and are commented as such
#define CP_ME_CNTL 0x86D8
#define CP_ME_HALT (1 << 28)
#define CP_PFP_HALT (1 << 26)
#define CP_ME_RAM_DATA 0xC160
#define CP_ME_RAM_RADDR 0xC158
#define CP_ME_RAM_WADDR 0xC15C
#define CP_MEQ_THRESHOLDS 0x8764
#define STQ_SPLIT(x) ((x) << 0)
#define CP_PERFMON_CNTL 0x87FC
#define CP_PFP_UCODE_ADDR 0xC150
#define CP_PFP_UCODE_DATA 0xC154
#define CP_QUEUE_THRESHOLDS 0x8760
#define ROQ_IB1_START(x) ((x) << 0)
#define ROQ_IB2_START(x) ((x) << 8)
#define CP_RB_BASE 0xC100
#define CP_RB_CNTL 0xC104
#define RB_BUFSZ(x) ((x) << 0)
#define RB_BLKSZ(x) ((x) << 8)
#define RB_NO_UPDATE (1 << 27)
#define RB_RPTR_WR_ENA (1 << 31)
#define BUF_SWAP_32BIT (2 << 16)
#define CP_RB_RPTR 0x8700
#define CP_RB_RPTR_ADDR 0xC10C
#define RB_RPTR_SWAP(x) ((x) << 0)
#define CP_RB_RPTR_ADDR_HI 0xC110
#define CP_RB_RPTR_WR 0xC108
#define CP_RB_WPTR 0xC114
#define CP_RB_WPTR_ADDR 0xC118
#define CP_RB_WPTR_ADDR_HI 0xC11C
#define CP_RB_WPTR_DELAY 0x8704
#define CP_SEM_WAIT_TIMER 0x85BC
#define CP_DEBUG 0xC1FC
#define NI_GRBM_CNTL 0x8000
#define GRBM_READ_TIMEOUT(x) ((x) << 0)
#define GRBM_STATUS 0x8010
#define CMDFIFO_AVAIL_MASK 0x0000000F
#define RING2_RQ_PENDING (1 << 4)
#define SRBM_RQ_PENDING (1 << 5)
#define RING1_RQ_PENDING (1 << 6)
#define CF_RQ_PENDING (1 << 7)
#define PF_RQ_PENDING (1 << 8)
#define GDS_DMA_RQ_PENDING (1 << 9)
#define GRBM_EE_BUSY (1 << 10)
#define SX_CLEAN (1 << 11) // ni
#define VC_BUSY (1 << 11) // r600
#define DB_CLEAN (1 << 12)
#define CB_CLEAN (1 << 13)
#define TA_BUSY (1 << 14)
#define GDS_BUSY (1 << 15)
#define VGT_BUSY_NO_DMA (1 << 16)
#define VGT_BUSY (1 << 17)
#define IA_BUSY_NO_DMA (1 << 18) // ni
#define TA03_BUSY (1 << 18) // r600
#define IA_BUSY (1 << 19) // ni
#define TC_BUSY (1 << 19) // r600
#define SX_BUSY (1 << 20)
#define SH_BUSY (1 << 21)
#define SPI_BUSY (1 << 22) // AKA SPI03_BUSY r600
#define SMX_BUSY (1 << 23)
#define SC_BUSY (1 << 24)
#define PA_BUSY (1 << 25)
#define DB_BUSY (1 << 26) // AKA DB03_BUSY r600
#define CR_BUSY (1 << 27)
#define CP_COHERENCY_BUSY (1 << 28)
#define CP_BUSY (1 << 29)
#define CB_BUSY (1 << 30)
#define GUI_ACTIVE (1 << 31)
#define GRBM_STATUS2 0x8014 // AKA GRBM_STATUS_SE0 ON NI
#define CR_CLEAN (1 << 0)
#define SMX_CLEAN (1 << 1)
#define SPI0_BUSY (1 << 8)
#define SPI1_BUSY (1 << 9)
#define SPI2_BUSY (1 << 10)
#define SPI3_BUSY (1 << 11)
#define TA0_BUSY (1 << 12)
#define TA1_BUSY (1 << 13)
#define TA2_BUSY (1 << 14)
#define TA3_BUSY (1 << 15)
#define DB0_BUSY (1 << 16)
#define DB1_BUSY (1 << 17)
#define DB2_BUSY (1 << 18)
#define DB3_BUSY (1 << 19)
#define CB0_BUSY (1 << 20)
#define CB1_BUSY (1 << 21)
#define CB2_BUSY (1 << 22)
#define CB3_BUSY (1 << 23)
#define NI_GRBM_STATUS_SE1 0x8018
#define SE_SX_CLEAN (1 << 0)
#define SE_DB_CLEAN (1 << 1)
#define SE_CB_CLEAN (1 << 2)
#define SE_VGT_BUSY (1 << 23)
#define SE_PA_BUSY (1 << 24)
#define SE_TA_BUSY (1 << 25)
#define SE_SX_BUSY (1 << 26)
#define SE_SPI_BUSY (1 << 27)
#define SE_SH_BUSY (1 << 28)
#define SE_SC_BUSY (1 << 29)
#define SE_DB_BUSY (1 << 30)
#define SE_CB_BUSY (1 << 31)
#define GRBM_SOFT_RESET 0x8020
#define SRBM_STATUS 0x0E50
#define RLC_RQ_PENDING (1 << 3)
#define RCU_RQ_PENDING (1 << 4)
#define GRBM_RQ_PENDING (1 << 5)
#define HI_RQ_PENDING (1 << 6)
#define IO_EXTERN_SIGNAL (1 << 7)
#define VMC_BUSY (1 << 8)
#define MCB_BUSY (1 << 9)
#define MCDZ_BUSY (1 << 10)
#define MCDY_BUSY (1 << 11)
#define MCDX_BUSY (1 << 12)
#define MCDW_BUSY (1 << 13)
#define SEM_BUSY (1 << 14)
#define SRBM_STATUS__RLC_BUSY (1 << 15)
#define PDMA_BUSY (1 << 16)
#define IH_BUSY (1 << 17)
#define CSC_BUSY (1 << 20)
#define CMC7_BUSY (1 << 21)
#define CMC6_BUSY (1 << 22)
#define CMC5_BUSY (1 << 23)
#define CMC4_BUSY (1 << 24)
#define CMC3_BUSY (1 << 25)
#define CMC2_BUSY (1 << 26)
#define CMC1_BUSY (1 << 27)
#define CMC0_BUSY (1 << 28)
#define BIF_BUSY (1 << 29)
#define IDCT_BUSY (1 << 30)
#define SRBM_SOFT_RESET 0x0E60
#define SOFT_RESET_CP (1 << 0)
#define SOFT_RESET_CB (1 << 1)
#define SOFT_RESET_CR (1 << 2)
#define SOFT_RESET_DB (1 << 3)
#define SOFT_RESET_GDS (1 << 4)
#define SOFT_RESET_PA (1 << 5)
#define SOFT_RESET_SC (1 << 6)
#define SOFT_RESET_SMX (1 << 7)
#define SOFT_RESET_SPI (1 << 8)
#define SOFT_RESET_SH (1 << 9)
#define SOFT_RESET_SX (1 << 10)
#define SOFT_RESET_TC (1 << 11)
#define SOFT_RESET_TA (1 << 12)
#define SOFT_RESET_VC (1 << 13)
#define SOFT_RESET_VGT (1 << 14)
#define SOFT_RESET_IA (1 << 15)
status_t radeon_gpu_reset();
uint32 radeon_gpu_mc_idle();
status_t radeon_gpu_mc_setup();
status_t radeon_gpu_irq_setup();
#endif
src/add-ons/accelerants/radeon_hd/mc.cpp
-70
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@@ -1,70 +0,0 @@
/*
* Copyright 2006-2011, Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License.
*
* Authors:
* Alexander von Gluck, kallisti5@unixzen.com
*/
#include "accelerant_protos.h"
#include "accelerant.h"
#include "utility.h"
#include "mc.h"
/* Read32/Write32 for MC can hande the fact that some cards need to write
to a special MC interface, while others just write to the card directly.
As of R600 - R800 though the special MC interface doesn't seem to exist
*/
#define TRACE_MC
#ifdef TRACE_MC
extern "C" void _sPrintf(const char *format, ...);
# define TRACE(x...) _sPrintf("radeon_hd: " x)
#else
# define TRACE(x...) ;
#endif
uint32
MCIdle()
{
uint32 turboencabulator;
if (!((turboencabulator = Read32(MC, SRBM_STATUS)) &
(VMC_BUSY_bit | MCB_BUSY_bit |
MCDZ_BUSY_bit | MCDY_BUSY_bit | MCDX_BUSY_bit | MCDW_BUSY_bit)))
return 0;
return turboencabulator;
}
status_t
MCFBSetup()
{
uint32 fb_location_int = gInfo->shared_info->frame_buffer_int;
uint32 fb_location = Read32(OUT, R6XX_MC_VM_FB_LOCATION);
uint16 fb_size = (fb_location >> 16) - (fb_location & 0xFFFF);
uint32 fb_location_tmp = fb_location_int >> 24;
fb_location_tmp |= (fb_location_tmp + fb_size) << 16;
uint32 fb_offset_tmp = (fb_location_int >> 8) & 0xff0000;
uint32 idleState = MCIdle();
if (idleState > 0) {
TRACE("%s: Cannot modify non-idle MC! idleState: %X\n",
__func__, idleState);
return B_ERROR;
}
TRACE("%s: Setting frame buffer from 0x%08X to 0x%08X [size 0x%08X]\n",
__func__, fb_location, fb_location_tmp, fb_size);
// The MC Write32 will handle cards needing a special MC read/write register
Write32(MC, R6XX_MC_VM_FB_LOCATION, fb_location_tmp);
Write32(MC, R6XX_HDP_NONSURFACE_BASE, fb_offset_tmp);
return B_OK;
}
src/add-ons/accelerants/radeon_hd/mc.h
-16
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@@ -1,16 +0,0 @@
/*
* Copyright 2006-2011, Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License.
*
* Authors:
* Alexander von Gluck, kallisti5@unixzen.com
*/
#ifndef RADEON_HD_MC_H
#define RADEON_HD_MC_H
uint32 MCIdle();
status_t MCFBSetup();
#endif
src/add-ons/accelerants/radeon_hd/mode.h
+1 -1
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@@ -13,7 +13,7 @@
#include <ddc.h>
#include <edid.h>
#include "mc.h"
#include "gpu.h"
#define T_POSITIVE_SYNC (B_POSITIVE_HSYNC | B_POSITIVE_VSYNC)