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more DMA related info, modified PLL type detection: all NV40+ have extended PLL's.

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10591 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2005-01-06 15:09:11 +00:00
parent 2bfa04fe4a
commit d96acb0dde
2 changed files with 13 additions and 14 deletions
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src/add-ons/accelerants/nvidia/engine/nv_acc.c
+6 -2
View File
@@ -93,7 +93,10 @@ status_t nv_acc_init()
/* cache1 DMA instance adress = none (b0-15); /* cache1 DMA instance adress = none (b0-15);
* instance being b4-19 with baseadress NV_PRAMIN_CTX_0 (0x00700000). */ * instance being b4-19 with baseadress NV_PRAMIN_CTX_0 (0x00700000). */
/* note: /* note:
* should point to a DMA definition in CTX register space (which is sort of RAM) */ * should point to a DMA definition in CTX register space (which is sort of RAM).
* This define tells the engine where the DMA cmd buffer is and what it's size is;
* inside that cmd buffer you'll find the engine handles for the FIFO channels,
* followed by actual issued engine commands. */
ACCW(PF_CACH1_DMAI, 0x00000000); ACCW(PF_CACH1_DMAI, 0x00000000);
/* cache0 push0 access disabled */ /* cache0 push0 access disabled */
@@ -205,7 +208,8 @@ status_t nv_acc_init()
/* note: /* note:
* CTX determines which HT handles point to what engine commands. * CTX determines which HT handles point to what engine commands.
* (CTX registers are actually a sort of RAM space.) */ * (CTX registers are actually a sort of RAM space.) */
/* (setup a DMA define 'set') */ /* setup a DMA define for use by command defines below.
* (would currently be used by CTX 'sets' 0x6 upto/including 0xe: 3D stuff.) */
ACCW(PR_CTX0_R, 0x00003000); /* DMA page table present and of linear type; ACCW(PR_CTX0_R, 0x00003000); /* DMA page table present and of linear type;
* DMA target node is NVM (non-volatile memory?) * DMA target node is NVM (non-volatile memory?)
* (instead of doing PCI or AGP transfers) */ * (instead of doing PCI or AGP transfers) */
src/add-ons/accelerants/nvidia/engine/nv_info.c
+7 -12
View File
@@ -1,7 +1,7 @@
/* Read initialisation information from card */ /* Read initialisation information from card */
/* some bits are hacks, where PINS is not known */ /* some bits are hacks, where PINS is not known */
/* Author: /* Author:
Rudolf Cornelissen 7/2003-12/2004 Rudolf Cornelissen 7/2003-1/2005
*/ */
#define MODULE_BIT 0x00002000 #define MODULE_BIT 0x00002000
@@ -2801,22 +2801,17 @@ static void pinsnv20_arch_fake(void)
static void pinsnv30_arch_fake(void) static void pinsnv30_arch_fake(void)
{ {
/* determine PLL type */ /* determine PLL type */
LOG(8,("INFO: NV30 architecture chip, PIXPLLC2 DAC1 = $%08x, DAC2 = $%08x\n", if ((si->ps.card_type == NV31) ||
DACR(PIXPLLC2), DAC2R(PIXPLLC2))); (si->ps.card_type == NV36) ||
switch (si->ps.card_type) (si->ps.card_type >= NV40))
{ {
case NV31:
case NV36:
/* fixme? could be all >= NV40 cards have extended PLL's... (these 2 are confirmed) */
case NV40:
case NV43:
/* we have a extended PLL */ /* we have a extended PLL */
si->ps.ext_pll = true; si->ps.ext_pll = true;
break; }
default: else
{
/* we have a standard PLL */ /* we have a standard PLL */
si->ps.ext_pll = false; si->ps.ext_pll = false;
break;
} }
/* carefull not to take to high limits, and high should be >= 2x low. */ /* carefull not to take to high limits, and high should be >= 2x low. */
si->ps.max_system_vco = 350; si->ps.max_system_vco = 350;