radeon_hd: re-rework some pll code

* Grab pseudo pll SS info for early
  Spread Spectrum access
* display_crtc_ss now takes a pll vs
  a display for easy pll access

src/add-ons/accelerants/radeon_hd/accelerant.cpp

@@ -255,9 +255,6 @@ radeon_init_accelerant(int device)
 	// probe firmware information
 	radeon_gpu_probe();
 
-	// program external pll clock
-	pll_external_init();
-
 	// find GPIO pins from AtomBIOS
 	gpio_probe();
 
@@ -280,6 +277,9 @@ radeon_init_accelerant(int device)
 	// setup encoders on each connector if needed
 	encoder_init();
 
+	// program external pll clock
+	pll_external_init();
+
 	// setup link on any DisplayPort connectors
 	dp_setup_connectors();
 

src/add-ons/accelerants/radeon_hd/display.cpp

@@ -843,7 +843,7 @@ display_crtc_set_dtd(uint8 crtcID, display_mode* mode)
 
 
 void
-display_crtc_ss(uint8 crtcID, int command)
+display_crtc_ss(pll_info* pll, int command)
 {
 	TRACE("%s\n", __func__);
 	radeon_shared_info &info = *gInfo->shared_info;
@@ -867,9 +867,6 @@ display_crtc_ss(uint8 crtcID, int command)
 	union enableSS args;
 	memset(&args, 0, sizeof(args));
 
-	uint32 connectorIndex = gDisplay[crtcID]->connectorIndex;
-	pll_info* pll = &gConnector[connectorIndex]->encoder.pll;
-
 	if (info.dceMajor >= 5) {
 		args.v3.usSpreadSpectrumAmountFrac = B_HOST_TO_LENDIAN_INT16(0);
 		args.v3.ucSpreadSpectrumType

src/add-ons/accelerants/radeon_hd/display.h

@@ -12,6 +12,7 @@
 #include <video_configuration.h>
 
 #include "accelerant.h"
+#include "pll.h"
 
 
 status_t init_registers(register_info* reg, uint8 crtid);
@@ -20,7 +21,7 @@ status_t detect_displays();
 void debug_displays();
 
 uint32 display_get_encoder_mode(uint32 connectorIndex);
-void display_crtc_ss(uint8 crtcID, int command);
+void display_crtc_ss(pll_info* pll, int command);
 void display_crtc_lock(uint8 crtcID, int command);
 void display_crtc_blank(uint8 crtcID, int command);
 void display_crtc_dpms(uint8 crtcID, int mode);

src/add-ons/accelerants/radeon_hd/pll.cpp

@@ -691,7 +691,7 @@ pll_set(display_mode* mode, uint8 crtcID)
 			break;
 	}
 
-	display_crtc_ss(crtcID, ATOM_DISABLE);
+	display_crtc_ss(pll, ATOM_DISABLE);
 		// disable ss
 
 	uint8 tableMajor;
@@ -826,7 +826,7 @@ pll_set(display_mode* mode, uint8 crtcID)
 
 	status_t result = atom_execute_table(gAtomContext, index, (uint32*)&args);
 
-	//display_crtc_ss(crtcID, ATOM_ENABLE);
+	//display_crtc_ss(pll, ATOM_ENABLE);
 	// Not yet, lets avoid this.
 
 	return result;
@@ -906,9 +906,17 @@ pll_external_init()
 	if (info.dceMajor >= 6) {
 		pll_external_set(gInfo->displayClockFrequency);
 	} else if (info.dceMajor >= 4) {
-		// TODO: SS enabled? disable
+		// Create our own pseudo pll
+		pll_info pll;
+		bool ssPresent = pll_asic_ss_probe(&pll, ASIC_INTERNAL_SS_ON_DCPLL)
+			== B_OK ? true : false;
+		if (ssPresent)
+			display_crtc_ss(&pll, ATOM_DISABLE);
 		pll_external_set(gInfo->displayClockFrequency);
-		// TODO: SS enabled? enable
+		#if 0
+		if (ssPresent)
+			display_crtc_ss(&pll, ATOM_ENABLE);
+		#endif
 	}
 }