Updating the atheroswifi driver to the FreeBSD HEAD svn rev 204100. This enables
support for some of the newer 9k chipsets. For example my Eee PC 1005 HA can now be used with WiFi. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@35747 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Colin Günther
@@ -93,6 +93,7 @@ KernelMergeObject atheroswifi_hal.o :
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# AR5416 support
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ah_eeprom_v14.c
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ah_eeprom_v4k.c
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ar5416_ani.c
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ar5416_attach.c
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ar5416_beacon.c
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@@ -111,9 +112,14 @@ KernelMergeObject atheroswifi_hal.o :
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ar5416_reset.c
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ar5416_xmit.c
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# AR9160 support
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# AR9k support
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ar9160_attach.c
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ar9280.c
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ar9280_attach.c
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ar9285.c
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ar9285_attach.c
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ar9285_reset.c
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# RF backend for 5416 and 9160
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ar2133.c
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;
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@@ -110,7 +110,7 @@ ath_hal_malloc(size_t size)
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void
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ath_hal_free(void* p)
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{
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return free(p, M_ATH_HAL);
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free(p, M_ATH_HAL);
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}
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void
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@@ -638,7 +638,11 @@ struct ath_hal {
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HAL_BOOL longCal, HAL_BOOL *isCalDone);
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HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *,
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const struct ieee80211_channel *);
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HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *,
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const struct ieee80211_channel *, uint16_t *);
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HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t);
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HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *,
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const struct ieee80211_channel *);
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/* Transmit functions */
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HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
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@@ -14,7 +14,7 @@
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $Id: ah_eeprom_v14.h,v 1.3 2008/11/10 04:08:00 sam Exp $
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* $FreeBSD$
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*/
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#ifndef _AH_EEPROM_V14_H_
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#define _AH_EEPROM_V14_H_
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@@ -76,6 +76,7 @@
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#define AR5416_EEPMISC_BIG_ENDIAN 0x01
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#define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
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#define AR5416_MAX_CHAINS 3
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#define AR5416_PWR_TABLE_OFFSET_DB -5
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#define AR5416_ANT_16S 25
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#define AR5416_NUM_ANT_CHAIN_FIELDS 7
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@@ -1759,7 +1759,7 @@ legacyEepromDetach(struct ath_hal *ah)
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HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
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if (ee->ee_version >= AR_EEPROM_VER4_0 && ee->ee_eepMap == 1)
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return freeEepromRawPowerCalInfo5112(ah, ee);
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freeEepromRawPowerCalInfo5112(ah, ee);
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ath_hal_free(ee);
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AH_PRIVATE(ah)->ah_eeprom = AH_NULL;
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}
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@@ -0,0 +1,404 @@
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/*
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* Copyright (c) 2009 Rui Paulo <rpaulo@FreeBSD.org>
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* Copyright (c) 2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_eeprom_v14.h"
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#include "ah_eeprom_v4k.h"
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static HAL_STATUS
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v4kEepromGet(struct ath_hal *ah, int param, void *val)
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{
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#define CHAN_A_IDX 0
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#define CHAN_B_IDX 1
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#define IS_VERS(op, v) ((pBase->version & AR5416_EEP_VER_MINOR_MASK) op (v))
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HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
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const MODAL_EEP4K_HEADER *pModal = &ee->ee_base.modalHeader;
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const BASE_EEP4K_HEADER *pBase = &ee->ee_base.baseEepHeader;
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uint32_t sum;
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uint8_t *macaddr;
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int i;
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switch (param) {
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case AR_EEP_NFTHRESH_5:
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*(int16_t *)val = pModal[0].noiseFloorThreshCh[0];
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return HAL_OK;
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case AR_EEP_NFTHRESH_2:
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*(int16_t *)val = pModal[1].noiseFloorThreshCh[0];
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return HAL_OK;
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case AR_EEP_MACADDR: /* Get MAC Address */
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sum = 0;
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macaddr = val;
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for (i = 0; i < 6; i++) {
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macaddr[i] = pBase->macAddr[i];
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sum += pBase->macAddr[i];
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}
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if (sum == 0 || sum == 0xffff*3) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad mac address %s\n",
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__func__, ath_hal_ether_sprintf(macaddr));
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return HAL_EEBADMAC;
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}
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return HAL_OK;
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case AR_EEP_REGDMN_0:
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return pBase->regDmn[0];
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case AR_EEP_REGDMN_1:
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return pBase->regDmn[1];
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case AR_EEP_OPCAP:
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return pBase->deviceCap;
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case AR_EEP_OPMODE:
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return pBase->opCapFlags;
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case AR_EEP_RFSILENT:
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return pBase->rfSilent;
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case AR_EEP_OB_5:
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return pModal[CHAN_A_IDX].ob;
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case AR_EEP_DB_5:
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return pModal[CHAN_A_IDX].db;
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case AR_EEP_OB_2:
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return pModal[CHAN_B_IDX].ob;
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case AR_EEP_DB_2:
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return pModal[CHAN_B_IDX].db;
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case AR_EEP_TXMASK:
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return pBase->txMask;
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case AR_EEP_RXMASK:
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return pBase->rxMask;
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case AR_EEP_RXGAIN_TYPE:
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return AR5416_EEP_RXGAIN_ORIG;
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case AR_EEP_TXGAIN_TYPE:
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return IS_VERS(>=, AR5416_EEP_MINOR_VER_19) ?
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pBase->txGainType : AR5416_EEP_TXGAIN_ORIG;
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#if 0
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case AR_EEP_OL_PWRCTRL:
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HALASSERT(val == AH_NULL);
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return pBase->openLoopPwrCntl ? HAL_OK : HAL_EIO;
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#endif
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case AR_EEP_AMODE:
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HALASSERT(val == AH_NULL);
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return pBase->opCapFlags & AR5416_OPFLAGS_11A ?
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HAL_OK : HAL_EIO;
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case AR_EEP_BMODE:
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case AR_EEP_GMODE:
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HALASSERT(val == AH_NULL);
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return pBase->opCapFlags & AR5416_OPFLAGS_11G ?
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HAL_OK : HAL_EIO;
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case AR_EEP_32KHZCRYSTAL:
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case AR_EEP_COMPRESS:
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case AR_EEP_FASTFRAME: /* XXX policy decision, h/w can do it */
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case AR_EEP_WRITEPROTECT: /* NB: no write protect bit */
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HALASSERT(val == AH_NULL);
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/* fall thru... */
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case AR_EEP_MAXQCU: /* NB: not in opCapFlags */
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case AR_EEP_KCENTRIES: /* NB: not in opCapFlags */
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return HAL_EIO;
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case AR_EEP_AES:
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case AR_EEP_BURST:
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case AR_EEP_RFKILL:
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case AR_EEP_TURBO5DISABLE:
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case AR_EEP_TURBO2DISABLE:
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HALASSERT(val == AH_NULL);
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return HAL_OK;
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case AR_EEP_ANTGAINMAX_2:
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*(int8_t *) val = ee->ee_antennaGainMax[1];
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return HAL_OK;
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case AR_EEP_ANTGAINMAX_5:
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*(int8_t *) val = ee->ee_antennaGainMax[0];
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return HAL_OK;
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default:
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HALASSERT(0);
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return HAL_EINVAL;
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}
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#undef IS_VERS
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#undef CHAN_A_IDX
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#undef CHAN_B_IDX
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}
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static HAL_BOOL
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v4kEepromSet(struct ath_hal *ah, int param, int v)
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{
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HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
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switch (param) {
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case AR_EEP_ANTGAINMAX_2:
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ee->ee_antennaGainMax[1] = (int8_t) v;
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return HAL_OK;
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case AR_EEP_ANTGAINMAX_5:
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ee->ee_antennaGainMax[0] = (int8_t) v;
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return HAL_OK;
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}
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return HAL_EINVAL;
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}
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static HAL_BOOL
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v4kEepromDiag(struct ath_hal *ah, int request,
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const void *args, uint32_t argsize, void **result, uint32_t *resultsize)
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{
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HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
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switch (request) {
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case HAL_DIAG_EEPROM:
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*result = &ee->ee_base;
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*resultsize = sizeof(ee->ee_base);
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return AH_TRUE;
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}
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return AH_FALSE;
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}
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/* Do structure specific swaps if Eeprom format is non native to host */
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static void
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eepromSwap(struct ar5416eeprom_4k *ee)
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{
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uint32_t integer, i;
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uint16_t word;
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MODAL_EEP4K_HEADER *pModal;
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/* convert Base Eep header */
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word = __bswap16(ee->baseEepHeader.length);
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ee->baseEepHeader.length = word;
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word = __bswap16(ee->baseEepHeader.checksum);
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ee->baseEepHeader.checksum = word;
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word = __bswap16(ee->baseEepHeader.version);
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ee->baseEepHeader.version = word;
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word = __bswap16(ee->baseEepHeader.regDmn[0]);
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ee->baseEepHeader.regDmn[0] = word;
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word = __bswap16(ee->baseEepHeader.regDmn[1]);
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ee->baseEepHeader.regDmn[1] = word;
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word = __bswap16(ee->baseEepHeader.rfSilent);
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ee->baseEepHeader.rfSilent = word;
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word = __bswap16(ee->baseEepHeader.blueToothOptions);
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ee->baseEepHeader.blueToothOptions = word;
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word = __bswap16(ee->baseEepHeader.deviceCap);
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ee->baseEepHeader.deviceCap = word;
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/* convert Modal Eep header */
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pModal = &ee->modalHeader;
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/* XXX linux/ah_osdep.h only defines __bswap32 for BE */
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integer = __bswap32(pModal->antCtrlCommon);
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pModal->antCtrlCommon = integer;
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for (i = 0; i < AR5416_4K_MAX_CHAINS; i++) {
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integer = __bswap32(pModal->antCtrlChain[i]);
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pModal->antCtrlChain[i] = integer;
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}
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for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
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word = __bswap16(pModal->spurChans[i].spurChan);
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pModal->spurChans[i].spurChan = word;
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}
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}
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static uint16_t
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v4kEepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz)
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{
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HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
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HALASSERT(0 <= ix && ix < AR5416_EEPROM_MODAL_SPURS);
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HALASSERT(is2GHz);
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return ee->ee_base.modalHeader.spurChans[ix].spurChan;
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}
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/**************************************************************************
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* fbin2freq
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*
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* Get channel value from binary representation held in eeprom
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* RETURNS: the frequency in MHz
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*/
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static uint16_t
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fbin2freq(uint8_t fbin, HAL_BOOL is2GHz)
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{
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/*
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* Reserved value 0xFF provides an empty definition both as
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* an fbin and as a frequency - do not convert
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*/
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if (fbin == AR5416_BCHAN_UNUSED)
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return fbin;
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return (uint16_t)((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
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}
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/*
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* Copy EEPROM Conformance Testing Limits contents
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* into the allocated space
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*/
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/* USE CTLS from chain zero */
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#define CTL_CHAIN 0
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static void
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v4kEepromReadCTLInfo(struct ath_hal *ah, HAL_EEPROM_v4k *ee)
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{
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RD_EDGES_POWER *rep = ee->ee_rdEdgesPower;
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int i, j;
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HALASSERT(AR5416_NUM_CTLS <= sizeof(ee->ee_rdEdgesPower)/NUM_EDGES);
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for (i = 0; ee->ee_base.ctlIndex[i] != 0 && i < AR5416_4K_NUM_CTLS; i++) {
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for (j = 0; j < NUM_EDGES; j ++) {
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/* XXX Confirm this is the right thing to do when an invalid channel is stored */
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if (ee->ee_base.ctlData[i].ctlEdges[CTL_CHAIN][j].bChannel == AR5416_BCHAN_UNUSED) {
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rep[j].rdEdge = 0;
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rep[j].twice_rdEdgePower = 0;
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rep[j].flag = 0;
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} else {
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rep[j].rdEdge = fbin2freq(
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ee->ee_base.ctlData[i].ctlEdges[CTL_CHAIN][j].bChannel,
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(ee->ee_base.ctlIndex[i] & CTL_MODE_M) != CTL_11A);
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rep[j].twice_rdEdgePower = MS(ee->ee_base.ctlData[i].ctlEdges[CTL_CHAIN][j].tPowerFlag, CAL_CTL_EDGES_POWER);
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rep[j].flag = MS(ee->ee_base.ctlData[i].ctlEdges[CTL_CHAIN][j].tPowerFlag, CAL_CTL_EDGES_FLAG) != 0;
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}
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}
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rep += NUM_EDGES;
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}
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ee->ee_numCtls = i;
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HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,
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"%s Numctls = %u\n",__func__,i);
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}
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/*
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* Reclaim any EEPROM-related storage.
|
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*/
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static void
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v4kEepromDetach(struct ath_hal *ah)
|
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{
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HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
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ath_hal_free(ee);
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AH_PRIVATE(ah)->ah_eeprom = AH_NULL;
|
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}
|
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#define owl_get_eep_ver(_ee) \
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(((_ee)->ee_base.baseEepHeader.version >> 12) & 0xF)
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#define owl_get_eep_rev(_ee) \
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(((_ee)->ee_base.baseEepHeader.version) & 0xFFF)
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|
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HAL_STATUS
|
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ath_hal_v4kEepromAttach(struct ath_hal *ah)
|
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{
|
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#define NW(a) (sizeof(a) / sizeof(uint16_t))
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HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
|
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uint16_t *eep_data, magic;
|
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HAL_BOOL need_swap;
|
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u_int w, off, len;
|
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uint32_t sum;
|
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|
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HALASSERT(ee == AH_NULL);
|
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|
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if (!ath_hal_eepromRead(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
|
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HALDEBUG(ah, HAL_DEBUG_ANY,
|
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"%s Error reading Eeprom MAGIC\n", __func__);
|
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return HAL_EEREAD;
|
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}
|
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HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s Eeprom Magic = 0x%x\n",
|
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__func__, magic);
|
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if (magic != AR5416_EEPROM_MAGIC) {
|
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HALDEBUG(ah, HAL_DEBUG_ANY, "Bad magic number\n");
|
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return HAL_EEMAGIC;
|
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}
|
||||
|
||||
ee = ath_hal_malloc(sizeof(HAL_EEPROM_v4k));
|
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if (ee == AH_NULL) {
|
||||
/* XXX message */
|
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return HAL_ENOMEM;
|
||||
}
|
||||
|
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eep_data = (uint16_t *)&ee->ee_base;
|
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for (w = 0; w < NW(struct ar5416eeprom_4k); w++) {
|
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off = owl_eep_start_loc + w; /* NB: AP71 starts at 0 */
|
||||
if (!ath_hal_eepromRead(ah, off, &eep_data[w])) {
|
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HALDEBUG(ah, HAL_DEBUG_ANY,
|
||||
"%s eeprom read error at offset 0x%x\n",
|
||||
__func__, off);
|
||||
return HAL_EEREAD;
|
||||
}
|
||||
}
|
||||
/* Convert to eeprom native eeprom endian format */
|
||||
if (isBigEndian()) {
|
||||
for (w = 0; w < NW(struct ar5416eeprom_4k); w++)
|
||||
eep_data[w] = __bswap16(eep_data[w]);
|
||||
}
|
||||
|
||||
/*
|
||||
* At this point, we're in the native eeprom endian format
|
||||
* Now, determine the eeprom endian by looking at byte 26??
|
||||
*/
|
||||
need_swap = ((ee->ee_base.baseEepHeader.eepMisc & AR5416_EEPMISC_BIG_ENDIAN) != 0) ^ isBigEndian();
|
||||
if (need_swap) {
|
||||
HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,
|
||||
"Byte swap EEPROM contents.\n");
|
||||
len = __bswap16(ee->ee_base.baseEepHeader.length);
|
||||
} else {
|
||||
len = ee->ee_base.baseEepHeader.length;
|
||||
}
|
||||
len = AH_MIN(len, sizeof(struct ar5416eeprom_4k)) / sizeof(uint16_t);
|
||||
|
||||
/* Apply the checksum, done in native eeprom format */
|
||||
/* XXX - Need to check to make sure checksum calculation is done
|
||||
* in the correct endian format. Right now, it seems it would
|
||||
* cast the raw data to host format and do the calculation, which may
|
||||
* not be correct as the calculation may need to be done in the native
|
||||
* eeprom format
|
||||
*/
|
||||
sum = 0;
|
||||
for (w = 0; w < len; w++) {
|
||||
sum ^= eep_data[w];
|
||||
}
|
||||
/* Check CRC - Attach should fail on a bad checksum */
|
||||
if (sum != 0xffff) {
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY,
|
||||
"Bad EEPROM checksum 0x%x (Len=%u)\n", sum, len);
|
||||
return HAL_EEBADSUM;
|
||||
}
|
||||
|
||||
if (need_swap)
|
||||
eepromSwap(&ee->ee_base); /* byte swap multi-byte data */
|
||||
|
||||
/* swap words 0+2 so version is at the front */
|
||||
magic = eep_data[0];
|
||||
eep_data[0] = eep_data[2];
|
||||
eep_data[2] = magic;
|
||||
|
||||
HALDEBUG(ah, HAL_DEBUG_ATTACH | HAL_DEBUG_EEPROM,
|
||||
"%s Eeprom Version %u.%u\n", __func__,
|
||||
owl_get_eep_ver(ee), owl_get_eep_rev(ee));
|
||||
|
||||
/* NB: must be after all byte swapping */
|
||||
if (owl_get_eep_ver(ee) != AR5416_EEP_VER) {
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY,
|
||||
"Bad EEPROM version 0x%x\n", owl_get_eep_ver(ee));
|
||||
return HAL_EEBADSUM;
|
||||
}
|
||||
|
||||
v4kEepromReadCTLInfo(ah, ee); /* Get CTLs */
|
||||
|
||||
AH_PRIVATE(ah)->ah_eeprom = ee;
|
||||
AH_PRIVATE(ah)->ah_eeversion = ee->ee_base.baseEepHeader.version;
|
||||
AH_PRIVATE(ah)->ah_eepromDetach = v4kEepromDetach;
|
||||
AH_PRIVATE(ah)->ah_eepromGet = v4kEepromGet;
|
||||
AH_PRIVATE(ah)->ah_eepromSet = v4kEepromSet;
|
||||
AH_PRIVATE(ah)->ah_getSpurChan = v4kEepromGetSpurChan;
|
||||
AH_PRIVATE(ah)->ah_eepromDiag = v4kEepromDiag;
|
||||
return HAL_OK;
|
||||
#undef NW
|
||||
}
|
||||
@@ -0,0 +1,155 @@
|
||||
/*
|
||||
* Copyright (c) 2009 Rui Paulo <rpaulo@FreeBSD.org>
|
||||
* Copyright (c) 2008 Sam Leffler, Errno Consulting
|
||||
* Copyright (c) 2008 Atheros Communications, Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#ifndef _AH_EEPROM_V4K_H_
|
||||
#define _AH_EEPROM_V4K_H_
|
||||
|
||||
#include "ah_eeprom.h"
|
||||
#include "ah_eeprom_v14.h"
|
||||
|
||||
#undef owl_eep_start_loc
|
||||
#ifdef __LINUX_ARM_ARCH__ /* AP71 */
|
||||
#define owl_eep_start_loc 0
|
||||
#else
|
||||
#define owl_eep_start_loc 64
|
||||
#endif
|
||||
|
||||
// 16-bit offset location start of calibration struct
|
||||
#define AR5416_4K_EEP_START_LOC 64
|
||||
#define AR5416_4K_NUM_2G_CAL_PIERS 3
|
||||
#define AR5416_4K_NUM_2G_CCK_TARGET_POWERS 3
|
||||
#define AR5416_4K_NUM_2G_20_TARGET_POWERS 3
|
||||
#define AR5416_4K_NUM_2G_40_TARGET_POWERS 3
|
||||
#define AR5416_4K_NUM_CTLS 12
|
||||
#define AR5416_4K_NUM_BAND_EDGES 4
|
||||
#define AR5416_4K_NUM_PD_GAINS 2
|
||||
#define AR5416_4K_MAX_CHAINS 1
|
||||
|
||||
/*
|
||||
* NB: The format in EEPROM has words 0 and 2 swapped (i.e. version
|
||||
* and length are swapped). We reverse their position after reading
|
||||
* the data into host memory so the version field is at the same
|
||||
* offset as in previous EEPROM layouts. This makes utilities that
|
||||
* inspect the EEPROM contents work without looking at the PCI device
|
||||
* id which may or may not be reliable.
|
||||
*/
|
||||
typedef struct BaseEepHeader4k {
|
||||
uint16_t version; /* NB: length in EEPROM */
|
||||
uint16_t checksum;
|
||||
uint16_t length; /* NB: version in EEPROM */
|
||||
uint8_t opCapFlags;
|
||||
uint8_t eepMisc;
|
||||
uint16_t regDmn[2];
|
||||
uint8_t macAddr[6];
|
||||
uint8_t rxMask;
|
||||
uint8_t txMask;
|
||||
uint16_t rfSilent;
|
||||
uint16_t blueToothOptions;
|
||||
uint16_t deviceCap;
|
||||
uint32_t binBuildNumber;
|
||||
uint8_t deviceType;
|
||||
uint8_t txGainType; /* high power tx gain table support */
|
||||
} __packed BASE_EEP4K_HEADER; // 32 B
|
||||
|
||||
typedef struct ModalEepHeader4k {
|
||||
uint32_t antCtrlChain[AR5416_4K_MAX_CHAINS]; // 12
|
||||
uint32_t antCtrlCommon; // 4
|
||||
int8_t antennaGainCh[AR5416_4K_MAX_CHAINS]; // 1
|
||||
uint8_t switchSettling; // 1
|
||||
uint8_t txRxAttenCh[AR5416_4K_MAX_CHAINS]; // 1
|
||||
uint8_t rxTxMarginCh[AR5416_4K_MAX_CHAINS]; // 1
|
||||
uint8_t adcDesiredSize; // 1
|
||||
int8_t pgaDesiredSize; // 1
|
||||
uint8_t xlnaGainCh[AR5416_4K_MAX_CHAINS]; // 1
|
||||
uint8_t txEndToXpaOff; // 1
|
||||
uint8_t txEndToRxOn; // 1
|
||||
uint8_t txFrameToXpaOn; // 1
|
||||
uint8_t thresh62; // 1
|
||||
uint8_t noiseFloorThreshCh[AR5416_4K_MAX_CHAINS]; // 1
|
||||
uint8_t xpdGain; // 1
|
||||
uint8_t xpd; // 1
|
||||
int8_t iqCalICh[AR5416_4K_MAX_CHAINS]; // 1
|
||||
int8_t iqCalQCh[AR5416_4K_MAX_CHAINS]; // 1
|
||||
uint8_t pdGainOverlap; // 1
|
||||
uint8_t ob; // 1
|
||||
uint8_t db; // 1
|
||||
uint8_t xpaBiasLvl; // 1
|
||||
#if 0
|
||||
uint8_t pwrDecreaseFor2Chain; // 1
|
||||
uint8_t pwrDecreaseFor3Chain; // 1 -> 48 B
|
||||
#endif
|
||||
uint8_t txFrameToDataStart; // 1
|
||||
uint8_t txFrameToPaOn; // 1
|
||||
uint8_t ht40PowerIncForPdadc; // 1
|
||||
uint8_t bswAtten[AR5416_4K_MAX_CHAINS]; // 1
|
||||
uint8_t bswMargin[AR5416_4K_MAX_CHAINS]; // 1
|
||||
uint8_t swSettleHt40; // 1
|
||||
uint8_t xatten2Db[AR5416_4K_MAX_CHAINS]; // 1
|
||||
uint8_t xatten2Margin[AR5416_4K_MAX_CHAINS]; // 1
|
||||
uint8_t ob_ch1; // 1 -> ob and db become chain specific from AR9280
|
||||
uint8_t db_ch1; // 1
|
||||
uint8_t flagBits; // 1
|
||||
#define AR5416_EEP_FLAG_USEANT1 0x01 /* +1 configured antenna */
|
||||
#define AR5416_EEP_FLAG_FORCEXPAON 0x02 /* force XPA bit for 5G */
|
||||
#define AR5416_EEP_FLAG_LOCALBIAS 0x04 /* enable local bias */
|
||||
#define AR5416_EEP_FLAG_FEMBANDSELECT 0x08 /* FEM band select used */
|
||||
#define AR5416_EEP_FLAG_XLNABUFIN 0x10
|
||||
#define AR5416_EEP_FLAG_XLNAISEL 0x60
|
||||
#define AR5416_EEP_FLAG_XLNAISEL_S 5
|
||||
#define AR5416_EEP_FLAG_XLNABUFMODE 0x80
|
||||
uint8_t miscBits; // [0..1]: bb_tx_dac_scale_cck
|
||||
uint16_t xpaBiasLvlFreq[3]; // 6
|
||||
uint8_t futureModal[2]; // 2
|
||||
|
||||
SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B
|
||||
} __packed MODAL_EEP4K_HEADER; // == 68 B
|
||||
|
||||
typedef struct CalCtlData4k {
|
||||
CAL_CTL_EDGES ctlEdges[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_BAND_EDGES];
|
||||
} __packed CAL_CTL_DATA_4K;
|
||||
|
||||
typedef struct calDataPerFreq4k {
|
||||
uint8_t pwrPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
|
||||
uint8_t vpdPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
|
||||
} __packed CAL_DATA_PER_FREQ_4K;
|
||||
|
||||
struct ar5416eeprom_4k {
|
||||
BASE_EEP4K_HEADER baseEepHeader; // 32 B
|
||||
uint8_t custData[20]; // 20 B
|
||||
MODAL_EEP4K_HEADER modalHeader; // 68 B
|
||||
uint8_t calFreqPier2G[AR5416_4K_NUM_2G_CAL_PIERS];
|
||||
CAL_DATA_PER_FREQ_4K calPierData2G[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_2G_CAL_PIERS];
|
||||
CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_4K_NUM_2G_CCK_TARGET_POWERS];
|
||||
CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_4K_NUM_2G_20_TARGET_POWERS];
|
||||
CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_4K_NUM_2G_20_TARGET_POWERS];
|
||||
CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_4K_NUM_2G_40_TARGET_POWERS];
|
||||
uint8_t ctlIndex[AR5416_4K_NUM_CTLS];
|
||||
CAL_CTL_DATA_4K ctlData[AR5416_4K_NUM_CTLS];
|
||||
uint8_t padding;
|
||||
} __packed;
|
||||
|
||||
typedef struct {
|
||||
struct ar5416eeprom_4k ee_base;
|
||||
#define NUM_EDGES 8
|
||||
uint16_t ee_numCtls;
|
||||
RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*AR5416_4K_NUM_CTLS];
|
||||
/* XXX these are dynamically calculated for use by shared code */
|
||||
int8_t ee_antennaGainMax[2];
|
||||
} HAL_EEPROM_v4k;
|
||||
#endif /* _AH_EEPROM_V4K_H_ */
|
||||
@@ -170,6 +170,7 @@ enum {
|
||||
|
||||
WOR9_WORLD = 0x69, /* World9 (WO9 SKU) */
|
||||
WORA_WORLD = 0x6A, /* WorldA (WOA SKU) */
|
||||
WORB_WORLD = 0x6B, /* WorldB (WOB SKU) */
|
||||
|
||||
MKK3_MKKB = 0x80, /* Japan UNI-1 even + MKKB */
|
||||
MKK3_MKKA2 = 0x81, /* Japan UNI-1 even + MKKA2 */
|
||||
@@ -432,6 +433,7 @@ static REG_DMN_PAIR_MAPPING regDomainPairs[] = {
|
||||
{EU1_WORLD, EU1_WORLD, EU1_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
|
||||
{WOR9_WORLD, WOR9_WORLD, WOR9_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
|
||||
{WORA_WORLD, WORA_WORLD, WORA_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
|
||||
{WORB_WORLD, WORB_WORLD, WORB_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -573,7 +575,7 @@ static COUNTRY_CODE_TO_ENUM_RD allCountries[] = {
|
||||
{ CTRY_SWITZERLAND, ETSI1_WORLD },
|
||||
{ CTRY_SYRIA, NULL1_WORLD },
|
||||
{ CTRY_TAIWAN, APL3_FCCA },
|
||||
{ CTRY_THAILAND, NULL1_WORLD },
|
||||
{ CTRY_THAILAND, FCC3_WORLD },
|
||||
{ CTRY_TRINIDAD_Y_TOBAGO,ETSI4_WORLD },
|
||||
{ CTRY_TUNISIA, ETSI3_WORLD },
|
||||
{ CTRY_TURKEY, ETSI3_WORLD },
|
||||
@@ -1681,6 +1683,31 @@ static REG_DOMAIN regDomains[] = {
|
||||
WG1_2467_2467),
|
||||
.chan11g_turbo = BM1(T3_2437_2437)},
|
||||
|
||||
{.regDmnEnum = WORB_WORLD,
|
||||
.conformanceTestLimit = NO_CTL,
|
||||
.dfsMask = DFS_FCC3 | DFS_ETSI,
|
||||
.pscan = PSCAN_WWR,
|
||||
.flags = DISALLOW_ADHOC_11A,
|
||||
.chan11a = BM4(W1_5260_5320,
|
||||
W1_5180_5240,
|
||||
W1_5745_5825,
|
||||
W1_5500_5700),
|
||||
.chan11b = BM7(W1_2412_2412,
|
||||
W1_2437_2442,
|
||||
W1_2462_2462,
|
||||
W1_2472_2472,
|
||||
W1_2417_2432,
|
||||
W1_2447_2457,
|
||||
W1_2467_2467),
|
||||
.chan11g = BM7(WG1_2412_2412,
|
||||
WG1_2437_2442,
|
||||
WG1_2462_2462,
|
||||
WG1_2472_2472,
|
||||
WG1_2417_2432,
|
||||
WG1_2447_2457,
|
||||
WG1_2467_2467),
|
||||
.chan11g_turbo = BM1(T3_2437_2437)},
|
||||
|
||||
{.regDmnEnum = NULL1,
|
||||
.conformanceTestLimit = NO_CTL,
|
||||
}
|
||||
|
||||
+1
-1
@@ -87,7 +87,7 @@ ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,
|
||||
|
||||
if (!IEEE80211_IS_CHAN_5GHZ(chan)) {
|
||||
/* Only 11a mode */
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: channel not 5Ghz\n", __func__);
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: channel not 5GHz\n", __func__);
|
||||
FAIL(HAL_EINVAL);
|
||||
}
|
||||
/*
|
||||
|
||||
+1
-1
@@ -136,7 +136,7 @@ static void ar5211GetLowerUpperPcdacs(uint16_t pcdac,
|
||||
uint16_t channel, const PCDACS_EEPROM *pSrcStruct,
|
||||
uint16_t *pLowerPcdac, uint16_t *pUpperPcdac);
|
||||
|
||||
static void ar5211SetRfgain(struct ath_hal *, const GAIN_VALUES *);;
|
||||
static void ar5211SetRfgain(struct ath_hal *, const GAIN_VALUES *);
|
||||
static void ar5211RequestRfgain(struct ath_hal *);
|
||||
static HAL_BOOL ar5211InvalidGainReadback(struct ath_hal *, GAIN_VALUES *);
|
||||
static HAL_BOOL ar5211IsGainAdjustNeeded(struct ath_hal *, const GAIN_VALUES *);
|
||||
|
||||
+1
-1
@@ -76,7 +76,7 @@ ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
|
||||
isr = OS_REG_READ(ah, AR_ISR_RAC);
|
||||
if (isr == 0xffffffff) {
|
||||
*masked = 0;
|
||||
return AH_FALSE;;
|
||||
return AH_FALSE;
|
||||
}
|
||||
|
||||
*masked = isr & HAL_INT_COMMON;
|
||||
|
||||
+3
-3
@@ -14,7 +14,7 @@
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $Id: ar5212_power.c,v 1.4 2008/11/10 04:08:03 sam Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#include "opt_ah.h"
|
||||
|
||||
@@ -38,8 +38,8 @@ static HAL_BOOL
|
||||
ar5212SetPowerModeAwake(struct ath_hal *ah, int setChip)
|
||||
{
|
||||
#define AR_SCR_MASK \
|
||||
(AR_SCR_SLDUR|AR_SCR_SLE|AR_SCR_SLE|AR_SCR_SLDTP|AR_SCR_SLDWP|\
|
||||
AR_SCR_SLEPOL|AR_SCR_MIBIE)
|
||||
(AR_SCR_SLDUR|AR_SCR_SLE|AR_SCR_SLDTP|AR_SCR_SLDWP|\
|
||||
AR_SCR_SLEPOL|AR_SCR_MIBIE|AR_SCR_UNKNOWN)
|
||||
#define POWER_UP_TIME 2000
|
||||
uint32_t scr, val;
|
||||
int i;
|
||||
|
||||
@@ -700,6 +700,7 @@
|
||||
#define AR_SCR_SLDWP 0x00080000 /* sleep duration write policy */
|
||||
#define AR_SCR_SLEPOL 0x00100000 /* sleep policy mode */
|
||||
#define AR_SCR_MIBIE 0x00200000 /* sleep perf cntrs MIB intr ena */
|
||||
#define AR_SCR_UNKNOWN 0x00400000
|
||||
|
||||
#define AR_INTPEND_TRUE 0x00000001 /* interrupt pending */
|
||||
|
||||
|
||||
@@ -21,6 +21,7 @@
|
||||
|
||||
#include "ar5212/ar5212.h"
|
||||
#include "ar5416_cal.h"
|
||||
#include "ah_eeprom_v14.h" /* for CAL_TARGET_POWER_* */
|
||||
|
||||
#define AR5416_MAGIC 0x20065416
|
||||
|
||||
@@ -44,6 +45,7 @@ typedef struct {
|
||||
#define AR5416_CCA_MAX_GOOD_VALUE -85
|
||||
#define AR5416_CCA_MAX_HIGH_VALUE -62
|
||||
#define AR5416_CCA_MIN_BAD_VALUE -140
|
||||
#define AR9285_CCA_MAX_GOOD_VALUE -118
|
||||
|
||||
#define AR5416_SPUR_RSSI_THRESH 40
|
||||
|
||||
@@ -178,12 +180,27 @@ extern HAL_RFGAIN ar5416GetRfgain(struct ath_hal *ah);
|
||||
extern HAL_BOOL ar5416Disable(struct ath_hal *ah);
|
||||
extern HAL_BOOL ar5416ChipReset(struct ath_hal *ah,
|
||||
const struct ieee80211_channel *);
|
||||
extern HAL_BOOL ar5416SetBoardValues(struct ath_hal *,
|
||||
const struct ieee80211_channel *);
|
||||
extern HAL_BOOL ar5416SetResetReg(struct ath_hal *, uint32_t type);
|
||||
extern HAL_BOOL ar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit);
|
||||
extern HAL_BOOL ar5416SetTransmitPower(struct ath_hal *,
|
||||
const struct ieee80211_channel *, uint16_t *);
|
||||
extern HAL_BOOL ar5416GetChipPowerLimits(struct ath_hal *ah,
|
||||
struct ieee80211_channel *chan);
|
||||
extern void ar5416GetChannelCenters(struct ath_hal *,
|
||||
const struct ieee80211_channel *chan, CHAN_CENTERS *centers);
|
||||
extern void ar5416GetTargetPowers(struct ath_hal *ah,
|
||||
const struct ieee80211_channel *chan,
|
||||
CAL_TARGET_POWER_HT *powInfo,
|
||||
uint16_t numChannels, CAL_TARGET_POWER_HT *pNewPower,
|
||||
uint16_t numRates, HAL_BOOL isHt40Target);
|
||||
extern void ar5416GetTargetPowersLeg(struct ath_hal *ah,
|
||||
const struct ieee80211_channel *chan,
|
||||
CAL_TARGET_POWER_LEG *powInfo,
|
||||
uint16_t numChannels, CAL_TARGET_POWER_LEG *pNewPower,
|
||||
uint16_t numRates, HAL_BOOL isExtTarget);
|
||||
|
||||
|
||||
extern HAL_BOOL ar5416StopTxDma(struct ath_hal *ah, u_int q);
|
||||
extern HAL_BOOL ar5416SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
|
||||
|
||||
+3
-3
@@ -183,7 +183,7 @@ ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
|
||||
|
||||
if (level >= params->maxNoiseImmunityLevel) {
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY,
|
||||
"%s: level out of range (%u > %u)\n",
|
||||
"%s: immunity level out of range (%u > %u)\n",
|
||||
__func__, level, params->maxNoiseImmunityLevel);
|
||||
return AH_FALSE;
|
||||
}
|
||||
@@ -267,7 +267,7 @@ ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
|
||||
|
||||
if (level >= params->maxFirstepLevel) {
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY,
|
||||
"%s: level out of range (%u > %u)\n",
|
||||
"%s: firstep level out of range (%u > %u)\n",
|
||||
__func__, level, params->maxFirstepLevel);
|
||||
return AH_FALSE;
|
||||
}
|
||||
@@ -285,7 +285,7 @@ ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
|
||||
|
||||
if (level >= params->maxSpurImmunityLevel) {
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY,
|
||||
"%s: level out of range (%u > %u)\n",
|
||||
"%s: spur immunity level out of range (%u > %u)\n",
|
||||
__func__, level, params->maxSpurImmunityLevel);
|
||||
return AH_FALSE;
|
||||
}
|
||||
|
||||
+2
@@ -89,6 +89,8 @@ ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
|
||||
ah->ah_perCalibrationN = ar5416PerCalibrationN,
|
||||
ah->ah_resetCalValid = ar5416ResetCalValid,
|
||||
ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit;
|
||||
ah->ah_setTxPower = ar5416SetTransmitPower;
|
||||
ah->ah_setBoardValues = ar5416SetBoardValues;
|
||||
|
||||
/* Transmit functions */
|
||||
ah->ah_stopTxDma = ar5416StopTxDma;
|
||||
|
||||
+1
-1
@@ -14,7 +14,7 @@
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $Id: ar5416_beacon.c,v 1.8 2008/11/11 01:03:12 sam Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#include "opt_ah.h"
|
||||
|
||||
|
||||
+1
-1
@@ -14,7 +14,7 @@
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $Id: ar5416_cal_adcdc.c,v 1.2 2008/11/11 17:43:23 sam Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#include "opt_ah.h"
|
||||
|
||||
|
||||
+1
-1
@@ -14,7 +14,7 @@
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $Id: ar5416_cal_adcgain.c,v 1.2 2008/11/11 17:43:23 sam Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#include "opt_ah.h"
|
||||
|
||||
|
||||
+1
-1
@@ -14,7 +14,7 @@
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $Id: ar5416_cal_iq.c,v 1.2 2008/11/11 17:43:23 sam Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#include "opt_ah.h"
|
||||
|
||||
|
||||
+1
-1
@@ -14,7 +14,7 @@
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $Id: ar5416_eeprom.c,v 1.6 2008/11/10 04:08:04 sam Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#include "opt_ah.h"
|
||||
|
||||
|
||||
+3
-1
@@ -146,7 +146,9 @@ ar5416GpioGet(struct ath_hal *ah, uint32_t gpio)
|
||||
* Read output value for all gpio's, shift it,
|
||||
* and verify whether the specific bit is set.
|
||||
*/
|
||||
if (AR_SREV_MERLIN_10_OR_LATER(ah))
|
||||
if (AR_SREV_KITE_10_OR_LATER(ah))
|
||||
bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR9285_GPIO_IN_VAL);
|
||||
else if (AR_SREV_MERLIN_10_OR_LATER(ah))
|
||||
bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR928X_GPIO_IN_VAL);
|
||||
else
|
||||
bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL);
|
||||
|
||||
+1
-1
@@ -104,7 +104,7 @@ ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
|
||||
isr = OS_REG_READ(ah, AR_ISR_RAC);
|
||||
if (isr == 0xffffffff) {
|
||||
*masked = 0;
|
||||
return AH_FALSE;;
|
||||
return AH_FALSE;
|
||||
}
|
||||
|
||||
*masked = isr & HAL_INT_COMMON;
|
||||
|
||||
+1
-1
@@ -14,7 +14,7 @@
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $Id: ar5416_keycache.c,v 1.3 2008/11/10 04:08:04 sam Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#include "opt_ah.h"
|
||||
|
||||
|
||||
+2
-2
@@ -14,7 +14,7 @@
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $Id: ar5416_misc.c,v 1.12 2008/11/27 22:30:07 sam Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#include "opt_ah.h"
|
||||
|
||||
@@ -30,7 +30,7 @@
|
||||
#include "ar5416/ar5416phy.h"
|
||||
|
||||
/*
|
||||
* Return the wireless modes (a,b,g,t) supported by hardware.
|
||||
* Return the wireless modes (a,b,g,n,t) supported by hardware.
|
||||
*
|
||||
* This value is what is actually supported by the hardware
|
||||
* and is unaffected by regulatory/country code settings.
|
||||
|
||||
+1
-1
@@ -14,7 +14,7 @@
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $Id: ar5416_phy.c,v 1.4 2008/11/27 22:30:08 sam Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#include "opt_ah.h"
|
||||
|
||||
|
||||
+1
-1
@@ -14,7 +14,7 @@
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $Id: ar5416_power.c,v 1.6 2008/11/11 00:11:30 sam Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#include "opt_ah.h"
|
||||
|
||||
|
||||
+1
-1
@@ -14,7 +14,7 @@
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $Id: ar5416_recv.c,v 1.7 2008/11/11 20:46:06 sam Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#include "opt_ah.h"
|
||||
|
||||
|
||||
+6
-18
@@ -45,9 +45,6 @@ static void ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode);
|
||||
static void ar5416InitQoS(struct ath_hal *ah);
|
||||
static void ar5416InitUserSettings(struct ath_hal *ah);
|
||||
|
||||
static HAL_BOOL ar5416SetTransmitPower(struct ath_hal *ah,
|
||||
const struct ieee80211_channel *chan, uint16_t *rfXpdGain);
|
||||
|
||||
#if 0
|
||||
static HAL_BOOL ar5416ChannelChange(struct ath_hal *, const struct ieee80211_channel *);
|
||||
#endif
|
||||
@@ -56,7 +53,6 @@ static void ar5416SetDeltaSlope(struct ath_hal *, const struct ieee80211_channel
|
||||
static HAL_BOOL ar5416SetResetPowerOn(struct ath_hal *ah);
|
||||
static HAL_BOOL ar5416SetReset(struct ath_hal *ah, int type);
|
||||
static void ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan);
|
||||
static HAL_BOOL ar5416SetBoardValues(struct ath_hal *, const struct ieee80211_channel *);
|
||||
static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah,
|
||||
struct ar5416eeprom *pEepData,
|
||||
const struct ieee80211_channel *chan, int16_t *ratesArray,
|
||||
@@ -69,14 +65,6 @@ static HAL_BOOL ar5416SetPowerCalTable(struct ath_hal *ah,
|
||||
int16_t *pTxPowerIndexOffset);
|
||||
static uint16_t ar5416GetMaxEdgePower(uint16_t freq,
|
||||
CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz);
|
||||
static void ar5416GetTargetPowers(struct ath_hal *ah,
|
||||
const struct ieee80211_channel *chan, CAL_TARGET_POWER_HT *powInfo,
|
||||
uint16_t numChannels, CAL_TARGET_POWER_HT *pNewPower,
|
||||
uint16_t numRates, HAL_BOOL isHt40Target);
|
||||
static void ar5416GetTargetPowersLeg(struct ath_hal *ah,
|
||||
const struct ieee80211_channel *chan, CAL_TARGET_POWER_LEG *powInfo,
|
||||
uint16_t numChannels, CAL_TARGET_POWER_LEG *pNewPower,
|
||||
uint16_t numRates, HAL_BOOL isExtTarget);
|
||||
|
||||
static int16_t interpolate(uint16_t target, uint16_t srcLeft,
|
||||
uint16_t srcRight, int16_t targetLeft, int16_t targetRight);
|
||||
@@ -224,7 +212,7 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
|
||||
OS_REG_WRITE(ah, AR_SELFGEN_MASK, AH5416(ah)->ah_tx_chainmask);
|
||||
|
||||
/* Setup the transmit power values. */
|
||||
if (!ar5416SetTransmitPower(ah, chan, rfXpdGain)) {
|
||||
if (!ah->ah_setTxPower(ah, chan, rfXpdGain)) {
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY,
|
||||
"%s: error init'ing transmit power\n", __func__);
|
||||
FAIL(HAL_EIO);
|
||||
@@ -245,7 +233,7 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
|
||||
AH5416(ah)->ah_spurMitigate(ah, chan);
|
||||
|
||||
/* Setup board specific options for EEPROM version 3 */
|
||||
if (!ar5416SetBoardValues(ah, chan)) {
|
||||
if (!ah->ah_setBoardValues(ah, chan)) {
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY,
|
||||
"%s: error setting board options\n", __func__);
|
||||
FAIL(HAL_EIO);
|
||||
@@ -793,7 +781,7 @@ typedef enum Ar5416_Rates {
|
||||
* Set the transmit power in the baseband for the given
|
||||
* operating channel and mode.
|
||||
*/
|
||||
static HAL_BOOL
|
||||
HAL_BOOL
|
||||
ar5416SetTransmitPower(struct ath_hal *ah,
|
||||
const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
|
||||
{
|
||||
@@ -1185,7 +1173,7 @@ ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
|
||||
* Read EEPROM header info and program the device for correct operation
|
||||
* given the channel value.
|
||||
*/
|
||||
static HAL_BOOL
|
||||
HAL_BOOL
|
||||
ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
|
||||
{
|
||||
const HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
|
||||
@@ -1622,7 +1610,7 @@ ar5416GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2G
|
||||
* Return the rates of target power for the given target power table
|
||||
* channel, and number of channels
|
||||
*/
|
||||
static void
|
||||
void
|
||||
ar5416GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan,
|
||||
CAL_TARGET_POWER_HT *powInfo, uint16_t numChannels,
|
||||
CAL_TARGET_POWER_HT *pNewPower, uint16_t numRates,
|
||||
@@ -1681,7 +1669,7 @@ ar5416GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan,
|
||||
* Return the four rates of target power for the given target power table
|
||||
* channel, and number of channels
|
||||
*/
|
||||
static void
|
||||
void
|
||||
ar5416GetTargetPowersLeg(struct ath_hal *ah,
|
||||
const struct ieee80211_channel *chan,
|
||||
CAL_TARGET_POWER_LEG *powInfo, uint16_t numChannels,
|
||||
|
||||
+1
-1
@@ -14,7 +14,7 @@
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $Id: ar5416desc.h,v 1.7 2008/11/11 00:11:30 sam Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#ifndef _ATH_AR5416_DESC_H_
|
||||
#define _ATH_AR5416_DESC_H
|
||||
|
||||
+20
-1
@@ -14,7 +14,7 @@
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $Id: ar5416phy.h,v 1.10 2008/11/11 20:46:06 sam Exp $
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#ifndef _DEV_ATH_AR5416PHY_H_
|
||||
#define _DEV_ATH_AR5416PHY_H_
|
||||
@@ -48,6 +48,7 @@
|
||||
#define AR_PHY_FC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
|
||||
#define AR_PHY_FC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */
|
||||
#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
|
||||
#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
|
||||
|
||||
#define AR_PHY_TIMING2 0x9810 /* Timing Control 2 */
|
||||
#define AR_PHY_TIMING2_USE_FORCE 0x00001000
|
||||
@@ -78,6 +79,20 @@
|
||||
#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
|
||||
#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
|
||||
|
||||
#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
|
||||
#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
|
||||
#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
|
||||
#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
|
||||
#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
|
||||
#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
|
||||
#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
|
||||
#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
|
||||
|
||||
#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
|
||||
#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
|
||||
#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
|
||||
#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
|
||||
|
||||
#define AR_PHY_EXT_CCA 0x99bc
|
||||
#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
|
||||
#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
|
||||
@@ -207,6 +222,9 @@
|
||||
#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
|
||||
#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
|
||||
|
||||
#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
|
||||
#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
|
||||
|
||||
#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
|
||||
#define AR_PHY_MASK2_M_31_45 0xa3a4
|
||||
#define AR_PHY_MASK2_M_16_30 0xa3a8
|
||||
@@ -247,4 +265,5 @@
|
||||
|
||||
#define AR_PHY_CL_CAL_CTL 0xA358 /* carrier leak cal control */
|
||||
#define AR_PHY_CL_CAL_ENABLE 0x00000002
|
||||
#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
|
||||
#endif /* _DEV_ATH_AR5416PHY_H_ */
|
||||
|
||||
+101
-33
@@ -70,8 +70,20 @@
|
||||
#define AR_AN_RF5G1_CH1 0x783C
|
||||
#define AR_AN_TOP2 0x7894
|
||||
#define AR_AN_SYNTH9 0x7868
|
||||
#define AR9285_AN_RF2G3 0x7828
|
||||
#define AR9285_AN_RF2G1 0x7820
|
||||
#define AR9285_AN_RF2G2 0x7824
|
||||
#define AR9285_AN_RF2G3 0x7828
|
||||
#define AR9285_AN_RF2G4 0x782C
|
||||
#define AR9285_AN_RF2G6 0x7834
|
||||
#define AR9285_AN_RF2G7 0x7838
|
||||
#define AR9285_AN_RF2G8 0x783C
|
||||
#define AR9285_AN_RF2G9 0x7840
|
||||
#define AR9285_AN_RXTXBB1 0x7854
|
||||
#define AR9285_AN_TOP2 0x7868
|
||||
#define AR9285_AN_TOP3 0x786c
|
||||
#define AR9285_AN_TOP4 0x7870
|
||||
#define AR9285_AN_TOP4_DEFAULT 0x10142c00
|
||||
|
||||
#define AR_RESET_TSF 0x8020
|
||||
#define AR_RXFIFO_CFG 0x8114
|
||||
#define AR_PHY_ERR_1 0x812c
|
||||
@@ -359,42 +371,83 @@
|
||||
#define AR_AN_SYNTH9_REFDIVA_S 27
|
||||
|
||||
/* AR9285 Analog registers */
|
||||
#define AR9285_AN_RF2G3_OB_0 0x00E00000
|
||||
#define AR9285_AN_RF2G3_OB_0_S 21
|
||||
#define AR9285_AN_RF2G3_OB_1 0x001C0000
|
||||
#define AR9285_AN_RF2G3_OB_1_S 18
|
||||
#define AR9285_AN_RF2G3_OB_2 0x00038000
|
||||
#define AR9285_AN_RF2G3_OB_2_S 15
|
||||
#define AR9285_AN_RF2G3_OB_3 0x00007000
|
||||
#define AR9285_AN_RF2G3_OB_3_S 12
|
||||
#define AR9285_AN_RF2G3_OB_4 0x00000E00
|
||||
#define AR9285_AN_RF2G3_OB_4_S 9
|
||||
#define AR9285_AN_RF2G1_ENPACAL 0x00000800
|
||||
#define AR9285_AN_RF2G1_ENPACAL_S 11
|
||||
#define AR9285_AN_RF2G1_PDPADRV1 0x02000000
|
||||
#define AR9285_AN_RF2G1_PDPADRV1_S 25
|
||||
#define AR9285_AN_RF2G1_PDPADRV2 0x01000000
|
||||
#define AR9285_AN_RF2G1_PDPADRV2_S 24
|
||||
#define AR9285_AN_RF2G1_PDPAOUT 0x00800000
|
||||
#define AR9285_AN_RF2G1_PDPAOUT_S 23
|
||||
|
||||
#define AR9285_AN_RF2G3_DB1_0 0x000001C0
|
||||
#define AR9285_AN_RF2G3_DB1_0_S 6
|
||||
#define AR9285_AN_RF2G3_DB1_1 0x00000038
|
||||
#define AR9285_AN_RF2G3_DB1_1_S 3
|
||||
#define AR9285_AN_RF2G3_DB1_2 0x00000007
|
||||
#define AR9285_AN_RF2G3_DB1_2_S 0
|
||||
#define AR9285_AN_RF2G4 0x782C
|
||||
#define AR9285_AN_RF2G4_DB1_3 0xE0000000
|
||||
#define AR9285_AN_RF2G4_DB1_3_S 29
|
||||
#define AR9285_AN_RF2G4_DB1_4 0x1C000000
|
||||
#define AR9285_AN_RF2G4_DB1_4_S 26
|
||||
#define AR9285_AN_RF2G2_OFFCAL 0x00001000
|
||||
#define AR9285_AN_RF2G2_OFFCAL_S 12
|
||||
|
||||
#define AR9285_AN_RF2G4_DB2_0 0x03800000
|
||||
#define AR9285_AN_RF2G4_DB2_0_S 23
|
||||
#define AR9285_AN_RF2G4_DB2_1 0x00700000
|
||||
#define AR9285_AN_RF2G4_DB2_1_S 20
|
||||
#define AR9285_AN_RF2G4_DB2_2 0x000E0000
|
||||
#define AR9285_AN_RF2G4_DB2_2_S 17
|
||||
#define AR9285_AN_RF2G4_DB2_3 0x0001C000
|
||||
#define AR9285_AN_RF2G4_DB2_3_S 14
|
||||
#define AR9285_AN_RF2G4_DB2_4 0x00003800
|
||||
#define AR9285_AN_RF2G4_DB2_4_S 11
|
||||
#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
|
||||
#define AR9285_AN_RF2G3_PDVCCOMP_S 25
|
||||
#define AR9285_AN_RF2G3_OB_0 0x00E00000
|
||||
#define AR9285_AN_RF2G3_OB_0_S 21
|
||||
#define AR9285_AN_RF2G3_OB_1 0x001C0000
|
||||
#define AR9285_AN_RF2G3_OB_1_S 18
|
||||
#define AR9285_AN_RF2G3_OB_2 0x00038000
|
||||
#define AR9285_AN_RF2G3_OB_2_S 15
|
||||
#define AR9285_AN_RF2G3_OB_3 0x00007000
|
||||
#define AR9285_AN_RF2G3_OB_3_S 12
|
||||
#define AR9285_AN_RF2G3_OB_4 0x00000E00
|
||||
#define AR9285_AN_RF2G3_OB_4_S 9
|
||||
|
||||
#define AR9285_AN_RF2G3_DB1_0 0x000001C0
|
||||
#define AR9285_AN_RF2G3_DB1_0_S 6
|
||||
#define AR9285_AN_RF2G3_DB1_1 0x00000038
|
||||
#define AR9285_AN_RF2G3_DB1_1_S 3
|
||||
#define AR9285_AN_RF2G3_DB1_2 0x00000007
|
||||
#define AR9285_AN_RF2G3_DB1_2_S 0
|
||||
|
||||
#define AR9285_AN_RF2G4_DB1_3 0xE0000000
|
||||
#define AR9285_AN_RF2G4_DB1_3_S 29
|
||||
#define AR9285_AN_RF2G4_DB1_4 0x1C000000
|
||||
#define AR9285_AN_RF2G4_DB1_4_S 26
|
||||
|
||||
#define AR9285_AN_RF2G4_DB2_0 0x03800000
|
||||
#define AR9285_AN_RF2G4_DB2_0_S 23
|
||||
#define AR9285_AN_RF2G4_DB2_1 0x00700000
|
||||
#define AR9285_AN_RF2G4_DB2_1_S 20
|
||||
#define AR9285_AN_RF2G4_DB2_2 0x000E0000
|
||||
#define AR9285_AN_RF2G4_DB2_2_S 17
|
||||
#define AR9285_AN_RF2G4_DB2_3 0x0001C000
|
||||
#define AR9285_AN_RF2G4_DB2_3_S 14
|
||||
#define AR9285_AN_RF2G4_DB2_4 0x00003800
|
||||
#define AR9285_AN_RF2G4_DB2_4_S 11
|
||||
|
||||
#define AR9285_AN_RF2G6_CCOMP 0x00007800
|
||||
#define AR9285_AN_RF2G6_CCOMP_S 11
|
||||
#define AR9285_AN_RF2G6_OFFS 0x03f00000
|
||||
#define AR9285_AN_RF2G6_OFFS_S 20
|
||||
|
||||
#define AR9271_AN_RF2G6_OFFS 0x07f00000
|
||||
#define AR9271_AN_RF2G6_OFFS_S 20
|
||||
|
||||
#define AR9285_AN_RF2G7_PWDDB 0x00000002
|
||||
#define AR9285_AN_RF2G7_PWDDB_S 1
|
||||
#define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000
|
||||
#define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29
|
||||
|
||||
#define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000
|
||||
#define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14
|
||||
|
||||
#define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020
|
||||
#define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5
|
||||
#define AR9285_AN_RXTXBB1_PDV2I 0x00000080
|
||||
#define AR9285_AN_RXTXBB1_PDV2I_S 7
|
||||
#define AR9285_AN_RXTXBB1_PDDACIF 0x00000100
|
||||
#define AR9285_AN_RXTXBB1_PDDACIF_S 8
|
||||
#define AR9285_AN_RXTXBB1_SPARE9 0x00000001
|
||||
#define AR9285_AN_RXTXBB1_SPARE9_S 0
|
||||
|
||||
#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C
|
||||
#define AR9285_AN_TOP3_XPABIAS_LVL_S 2
|
||||
#define AR9285_AN_TOP3_PWDDAC 0x00800000
|
||||
#define AR9285_AN_TOP3_PWDDAC_S 23
|
||||
|
||||
/* Sleep control */
|
||||
#define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */
|
||||
@@ -472,6 +525,7 @@
|
||||
|
||||
#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF
|
||||
#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700
|
||||
#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380
|
||||
|
||||
/* Eeprom defines */
|
||||
#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
|
||||
@@ -522,6 +576,8 @@
|
||||
#define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */
|
||||
#define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */
|
||||
#define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */
|
||||
#define AR_XSREV_REVISION_KITE_11 1 /* Kite 1.1 */
|
||||
#define AR_XSREV_REVISION_KITE_12 2 /* Kite 1.2 */
|
||||
|
||||
#define AR_SREV_OWL_20_OR_LATER(_ah) \
|
||||
(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \
|
||||
@@ -544,7 +600,7 @@
|
||||
(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN)
|
||||
#define AR_SREV_MERLIN_20(_ah) \
|
||||
(AR_SREV_MERLIN(_ah) && \
|
||||
AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20)
|
||||
AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_MERLIN_20)
|
||||
#define AR_SREV_MERLIN_20_OR_LATER(_ah) \
|
||||
(AR_SREV_MERLIN_20(_ah) || \
|
||||
AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN)
|
||||
@@ -553,4 +609,16 @@
|
||||
(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE)
|
||||
#define AR_SREV_KITE_10_OR_LATER(_ah) \
|
||||
(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE)
|
||||
#define AR_SREV_KITE_11(_ah) \
|
||||
(AR_SREV_KITE(ah) && \
|
||||
AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_11)
|
||||
#define AR_SREV_KITE_11_OR_LATER(_ah) \
|
||||
(AR_SREV_KITE_11(_ah) || \
|
||||
AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_11)
|
||||
#define AR_SREV_KITE_12(_ah) \
|
||||
(AR_SREV_KITE(ah) && \
|
||||
AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_12)
|
||||
#define AR_SREV_KITE_12_OR_LATER(_ah) \
|
||||
(AR_SREV_KITE_12(_ah) || \
|
||||
AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_12)
|
||||
#endif /* _DEV_ATH_AR5416REG_H */
|
||||
|
||||
@@ -30,11 +30,16 @@ struct ath_hal_9280 {
|
||||
#define AH9280(_ah) ((struct ath_hal_9280 *)(_ah))
|
||||
|
||||
#define AR9280_DEFAULT_RXCHAINMASK 3
|
||||
#define AR9285_DEFAULT_RXCHAINMASK 1
|
||||
#define AR9280_DEFAULT_TXCHAINMASK 1
|
||||
#define AR9285_DEFAULT_TXCHAINMASK 1
|
||||
|
||||
HAL_BOOL ar9280RfAttach(struct ath_hal *, HAL_STATUS *);
|
||||
|
||||
struct ath_hal;
|
||||
|
||||
HAL_BOOL ar9280SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
|
||||
void ar9280SpurMitigate(struct ath_hal *,
|
||||
const struct ieee80211_channel *);
|
||||
|
||||
#endif /* _ATH_AR9280_H_ */
|
||||
|
||||
+1
-3
@@ -64,8 +64,6 @@ static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
|
||||
static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah);
|
||||
static void ar9280WriteIni(struct ath_hal *ah,
|
||||
const struct ieee80211_channel *chan);
|
||||
static void ar9280SpurMitigate(struct ath_hal *ah,
|
||||
const struct ieee80211_channel *chan);
|
||||
|
||||
static void
|
||||
ar9280AniSetup(struct ath_hal *ah)
|
||||
@@ -360,7 +358,7 @@ ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
|
||||
#define AR_SPUR_FEEQ_BOUND_HT40 19
|
||||
#define AR_SPUR_FEEQ_BOUND_HT20 10
|
||||
|
||||
static void
|
||||
void
|
||||
ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan)
|
||||
{
|
||||
static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
|
||||
|
||||
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
* Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
|
||||
* Copyright (c) 2008 Atheros Communications, Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#include "opt_ah.h"
|
||||
|
||||
#include "ah.h"
|
||||
#include "ah_internal.h"
|
||||
|
||||
#include "ah_eeprom_v14.h"
|
||||
|
||||
#include "ar5416/ar9280.h"
|
||||
#include "ar5416/ar9285.h"
|
||||
#include "ar5416/ar5416reg.h"
|
||||
#include "ar5416/ar5416phy.h"
|
||||
|
||||
static void
|
||||
ar9285GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])
|
||||
{
|
||||
int16_t nf;
|
||||
|
||||
nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
|
||||
if (nf & 0x100)
|
||||
nf = 0 - ((nf ^ 0x1ff) + 1);
|
||||
HALDEBUG(ah, HAL_DEBUG_NFCAL,
|
||||
"NF calibrated [ctl] [chain 0] is %d\n", nf);
|
||||
nfarray[0] = nf;
|
||||
|
||||
nfarray[1] = 0;
|
||||
|
||||
nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
|
||||
if (nf & 0x100)
|
||||
nf = 0 - ((nf ^ 0x1ff) + 1);
|
||||
HALDEBUG(ah, HAL_DEBUG_NFCAL,
|
||||
"NF calibrated [ext] [chain 0] is %d\n", nf);
|
||||
nfarray[3] = nf;
|
||||
|
||||
nfarray[4] = 0;
|
||||
}
|
||||
|
||||
HAL_BOOL
|
||||
ar9285RfAttach(struct ath_hal *ah, HAL_STATUS *status)
|
||||
{
|
||||
if (ar9280RfAttach(ah, status) == AH_FALSE)
|
||||
return AH_FALSE;
|
||||
|
||||
AH_PRIVATE(ah)->ah_getNoiseFloor = ar9285GetNoiseFloor;
|
||||
|
||||
return AH_TRUE;
|
||||
}
|
||||
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#ifndef _ATH_AR9285_H_
|
||||
#define _ATH_AR9285_H_
|
||||
|
||||
#include "ar5416/ar5416.h"
|
||||
|
||||
struct ath_hal_9285 {
|
||||
struct ath_hal_5416 ah_5416;
|
||||
|
||||
HAL_INI_ARRAY ah_ini_txgain;
|
||||
HAL_INI_ARRAY ah_ini_rxgain;
|
||||
};
|
||||
#define AH9285(_ah) ((struct ath_hal_9285 *)(_ah))
|
||||
|
||||
#define AR9285_DEFAULT_RXCHAINMASK 1
|
||||
#define AR9285_DEFAULT_TXCHAINMASK 1
|
||||
|
||||
|
||||
HAL_BOOL ar9285SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
|
||||
HAL_BOOL ar9285RfAttach(struct ath_hal *, HAL_STATUS *);
|
||||
|
||||
extern HAL_BOOL ar9285SetTransmitPower(struct ath_hal *,
|
||||
const struct ieee80211_channel *, uint16_t *);
|
||||
extern HAL_BOOL ar9285SetBoardValues(struct ath_hal *,
|
||||
const struct ieee80211_channel *);
|
||||
|
||||
#endif /* _ATH_AR9285_H_ */
|
||||
+699
@@ -0,0 +1,699 @@
|
||||
/*
|
||||
* Copyright (c) 2008-2009 Atheros Communications Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/* AR9285 Revsion 10 */
|
||||
static const u_int32_t ar9285Modes[][6] = {
|
||||
{ 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
|
||||
{ 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
|
||||
{ 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
|
||||
{ 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
|
||||
{ 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
|
||||
{ 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
|
||||
{ 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
|
||||
{ 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
|
||||
{ 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
|
||||
{ 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
|
||||
{ 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
|
||||
{ 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
|
||||
{ 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
|
||||
{ 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
|
||||
{ 0x00009844, 0x0372161e, 0x0372161e, 0x03720020, 0x03720020, 0x037216a0 },
|
||||
{ 0x00009848, 0x00001066, 0x00001066, 0x0000004e, 0x0000004e, 0x00001059 },
|
||||
{ 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
|
||||
{ 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
|
||||
{ 0x0000985c, 0x3139605e, 0x3139605e, 0x3136605e, 0x3136605e, 0x3139605e },
|
||||
{ 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
|
||||
{ 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
|
||||
{ 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
|
||||
{ 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
|
||||
{ 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
|
||||
{ 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
|
||||
{ 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
|
||||
{ 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1020, 0xdfbc1020, 0xdfbc1010 },
|
||||
{ 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x000099b8, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c },
|
||||
{ 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
|
||||
{ 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
|
||||
{ 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
|
||||
{ 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
|
||||
{ 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
|
||||
{ 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
|
||||
{ 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x00009a00, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
|
||||
{ 0x00009a04, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
|
||||
{ 0x00009a08, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
|
||||
{ 0x00009a0c, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
|
||||
{ 0x00009a10, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
|
||||
{ 0x00009a14, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
|
||||
{ 0x00009a18, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
|
||||
{ 0x00009a1c, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
|
||||
{ 0x00009a20, 0x00000000, 0x00000000, 0x00068114, 0x00068114, 0x00000000 },
|
||||
{ 0x00009a24, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
|
||||
{ 0x00009a28, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
|
||||
{ 0x00009a2c, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
|
||||
{ 0x00009a30, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
|
||||
{ 0x00009a34, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
|
||||
{ 0x00009a38, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
|
||||
{ 0x00009a3c, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
|
||||
{ 0x00009a40, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
|
||||
{ 0x00009a44, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
|
||||
{ 0x00009a48, 0x00000000, 0x00000000, 0x00068284, 0x00068284, 0x00000000 },
|
||||
{ 0x00009a4c, 0x00000000, 0x00000000, 0x00068288, 0x00068288, 0x00000000 },
|
||||
{ 0x00009a50, 0x00000000, 0x00000000, 0x00068220, 0x00068220, 0x00000000 },
|
||||
{ 0x00009a54, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
|
||||
{ 0x00009a58, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
|
||||
{ 0x00009a5c, 0x00000000, 0x00000000, 0x00068304, 0x00068304, 0x00000000 },
|
||||
{ 0x00009a60, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
|
||||
{ 0x00009a64, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
|
||||
{ 0x00009a68, 0x00000000, 0x00000000, 0x00068380, 0x00068380, 0x00000000 },
|
||||
{ 0x00009a6c, 0x00000000, 0x00000000, 0x00068384, 0x00068384, 0x00000000 },
|
||||
{ 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
|
||||
{ 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
|
||||
{ 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
|
||||
{ 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
|
||||
{ 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
|
||||
{ 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
|
||||
{ 0x00009a88, 0x00000000, 0x00000000, 0x00068b04, 0x00068b04, 0x00000000 },
|
||||
{ 0x00009a8c, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
|
||||
{ 0x00009a90, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
|
||||
{ 0x00009a94, 0x00000000, 0x00000000, 0x00068b0c, 0x00068b0c, 0x00000000 },
|
||||
{ 0x00009a98, 0x00000000, 0x00000000, 0x00068b80, 0x00068b80, 0x00000000 },
|
||||
{ 0x00009a9c, 0x00000000, 0x00000000, 0x00068b84, 0x00068b84, 0x00000000 },
|
||||
{ 0x00009aa0, 0x00000000, 0x00000000, 0x00068b88, 0x00068b88, 0x00000000 },
|
||||
{ 0x00009aa4, 0x00000000, 0x00000000, 0x00068b8c, 0x00068b8c, 0x00000000 },
|
||||
{ 0x00009aa8, 0x00000000, 0x00000000, 0x000b8b90, 0x000b8b90, 0x00000000 },
|
||||
{ 0x00009aac, 0x00000000, 0x00000000, 0x000b8f80, 0x000b8f80, 0x00000000 },
|
||||
{ 0x00009ab0, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
|
||||
{ 0x00009ab4, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
|
||||
{ 0x00009ab8, 0x00000000, 0x00000000, 0x000b8f8c, 0x000b8f8c, 0x00000000 },
|
||||
{ 0x00009abc, 0x00000000, 0x00000000, 0x000b8f90, 0x000b8f90, 0x00000000 },
|
||||
{ 0x00009ac0, 0x00000000, 0x00000000, 0x000bb30c, 0x000bb30c, 0x00000000 },
|
||||
{ 0x00009ac4, 0x00000000, 0x00000000, 0x000bb310, 0x000bb310, 0x00000000 },
|
||||
{ 0x00009ac8, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
|
||||
{ 0x00009acc, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
|
||||
{ 0x00009ad0, 0x00000000, 0x00000000, 0x000bb324, 0x000bb324, 0x00000000 },
|
||||
{ 0x00009ad4, 0x00000000, 0x00000000, 0x000bb704, 0x000bb704, 0x00000000 },
|
||||
{ 0x00009ad8, 0x00000000, 0x00000000, 0x000f96a4, 0x000f96a4, 0x00000000 },
|
||||
{ 0x00009adc, 0x00000000, 0x00000000, 0x000f96a8, 0x000f96a8, 0x00000000 },
|
||||
{ 0x00009ae0, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
|
||||
{ 0x00009ae4, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
|
||||
{ 0x00009ae8, 0x00000000, 0x00000000, 0x000f9720, 0x000f9720, 0x00000000 },
|
||||
{ 0x00009aec, 0x00000000, 0x00000000, 0x000f9724, 0x000f9724, 0x00000000 },
|
||||
{ 0x00009af0, 0x00000000, 0x00000000, 0x000f9728, 0x000f9728, 0x00000000 },
|
||||
{ 0x00009af4, 0x00000000, 0x00000000, 0x000f972c, 0x000f972c, 0x00000000 },
|
||||
{ 0x00009af8, 0x00000000, 0x00000000, 0x000f97a0, 0x000f97a0, 0x00000000 },
|
||||
{ 0x00009afc, 0x00000000, 0x00000000, 0x000f97a4, 0x000f97a4, 0x00000000 },
|
||||
{ 0x00009b00, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
|
||||
{ 0x00009b04, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
|
||||
{ 0x00009b08, 0x00000000, 0x00000000, 0x000fb7b4, 0x000fb7b4, 0x00000000 },
|
||||
{ 0x00009b0c, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
|
||||
{ 0x00009b10, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
|
||||
{ 0x00009b14, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
|
||||
{ 0x00009b18, 0x00000000, 0x00000000, 0x000fb7ad, 0x000fb7ad, 0x00000000 },
|
||||
{ 0x00009b1c, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
|
||||
{ 0x00009b20, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
|
||||
{ 0x00009b24, 0x00000000, 0x00000000, 0x000fb7b9, 0x000fb7b9, 0x00000000 },
|
||||
{ 0x00009b28, 0x00000000, 0x00000000, 0x000fb7c5, 0x000fb7c5, 0x00000000 },
|
||||
{ 0x00009b2c, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
|
||||
{ 0x00009b30, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
|
||||
{ 0x00009b34, 0x00000000, 0x00000000, 0x000fb7d5, 0x000fb7d5, 0x00000000 },
|
||||
{ 0x00009b38, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
|
||||
{ 0x00009b3c, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
|
||||
{ 0x00009b40, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
|
||||
{ 0x00009b44, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
|
||||
{ 0x00009b48, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
|
||||
{ 0x00009b4c, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
|
||||
{ 0x00009b50, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
|
||||
{ 0x00009b54, 0x00000000, 0x00000000, 0x000fb7c7, 0x000fb7c7, 0x00000000 },
|
||||
{ 0x00009b58, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
|
||||
{ 0x00009b5c, 0x00000000, 0x00000000, 0x000fb7cf, 0x000fb7cf, 0x00000000 },
|
||||
{ 0x00009b60, 0x00000000, 0x00000000, 0x000fb7d7, 0x000fb7d7, 0x00000000 },
|
||||
{ 0x00009b64, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009b68, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009b6c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009b70, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009b74, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009b78, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009b7c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009b80, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009b84, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009b88, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009b8c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009b90, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009b94, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009b98, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009b9c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009ba0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009ba4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009ba8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bac, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bb0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bb4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bb8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bbc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bc0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bc4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bc8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bcc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bd0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bd4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bd8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bdc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009be0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009be4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009be8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bec, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bf0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bf4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bf8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x00009bfc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
|
||||
{ 0x0000aa00, 0x00000000, 0x00000000, 0x0006801c, 0x0006801c, 0x00000000 },
|
||||
{ 0x0000aa04, 0x00000000, 0x00000000, 0x00068080, 0x00068080, 0x00000000 },
|
||||
{ 0x0000aa08, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
|
||||
{ 0x0000aa0c, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
|
||||
{ 0x0000aa10, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
|
||||
{ 0x0000aa14, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
|
||||
{ 0x0000aa18, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
|
||||
{ 0x0000aa1c, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
|
||||
{ 0x0000aa20, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
|
||||
{ 0x0000aa24, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
|
||||
{ 0x0000aa28, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
|
||||
{ 0x0000aa2c, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
|
||||
{ 0x0000aa30, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
|
||||
{ 0x0000aa34, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
|
||||
{ 0x0000aa38, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
|
||||
{ 0x0000aa3c, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
|
||||
{ 0x0000aa40, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
|
||||
{ 0x0000aa44, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
|
||||
{ 0x0000aa48, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
|
||||
{ 0x0000aa4c, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
|
||||
{ 0x0000aa50, 0x00000000, 0x00000000, 0x000681ac, 0x000681ac, 0x00000000 },
|
||||
{ 0x0000aa54, 0x00000000, 0x00000000, 0x0006821c, 0x0006821c, 0x00000000 },
|
||||
{ 0x0000aa58, 0x00000000, 0x00000000, 0x00068224, 0x00068224, 0x00000000 },
|
||||
{ 0x0000aa5c, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
|
||||
{ 0x0000aa60, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
|
||||
{ 0x0000aa64, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
|
||||
{ 0x0000aa68, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
|
||||
{ 0x0000aa6c, 0x00000000, 0x00000000, 0x00068310, 0x00068310, 0x00000000 },
|
||||
{ 0x0000aa70, 0x00000000, 0x00000000, 0x00068788, 0x00068788, 0x00000000 },
|
||||
{ 0x0000aa74, 0x00000000, 0x00000000, 0x0006878c, 0x0006878c, 0x00000000 },
|
||||
{ 0x0000aa78, 0x00000000, 0x00000000, 0x00068790, 0x00068790, 0x00000000 },
|
||||
{ 0x0000aa7c, 0x00000000, 0x00000000, 0x00068794, 0x00068794, 0x00000000 },
|
||||
{ 0x0000aa80, 0x00000000, 0x00000000, 0x00068798, 0x00068798, 0x00000000 },
|
||||
{ 0x0000aa84, 0x00000000, 0x00000000, 0x0006879c, 0x0006879c, 0x00000000 },
|
||||
{ 0x0000aa88, 0x00000000, 0x00000000, 0x00068b89, 0x00068b89, 0x00000000 },
|
||||
{ 0x0000aa8c, 0x00000000, 0x00000000, 0x00068b8d, 0x00068b8d, 0x00000000 },
|
||||
{ 0x0000aa90, 0x00000000, 0x00000000, 0x00068b91, 0x00068b91, 0x00000000 },
|
||||
{ 0x0000aa94, 0x00000000, 0x00000000, 0x00068b95, 0x00068b95, 0x00000000 },
|
||||
{ 0x0000aa98, 0x00000000, 0x00000000, 0x00068b99, 0x00068b99, 0x00000000 },
|
||||
{ 0x0000aa9c, 0x00000000, 0x00000000, 0x00068ba5, 0x00068ba5, 0x00000000 },
|
||||
{ 0x0000aaa0, 0x00000000, 0x00000000, 0x00068ba9, 0x00068ba9, 0x00000000 },
|
||||
{ 0x0000aaa4, 0x00000000, 0x00000000, 0x00068bad, 0x00068bad, 0x00000000 },
|
||||
{ 0x0000aaa8, 0x00000000, 0x00000000, 0x000b8b0c, 0x000b8b0c, 0x00000000 },
|
||||
{ 0x0000aaac, 0x00000000, 0x00000000, 0x000b8f10, 0x000b8f10, 0x00000000 },
|
||||
{ 0x0000aab0, 0x00000000, 0x00000000, 0x000b8f14, 0x000b8f14, 0x00000000 },
|
||||
{ 0x0000aab4, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
|
||||
{ 0x0000aab8, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
|
||||
{ 0x0000aabc, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
|
||||
{ 0x0000aac0, 0x00000000, 0x00000000, 0x000bb380, 0x000bb380, 0x00000000 },
|
||||
{ 0x0000aac4, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
|
||||
{ 0x0000aac8, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
|
||||
{ 0x0000aacc, 0x00000000, 0x00000000, 0x000bb38c, 0x000bb38c, 0x00000000 },
|
||||
{ 0x0000aad0, 0x00000000, 0x00000000, 0x000bb394, 0x000bb394, 0x00000000 },
|
||||
{ 0x0000aad4, 0x00000000, 0x00000000, 0x000bb798, 0x000bb798, 0x00000000 },
|
||||
{ 0x0000aad8, 0x00000000, 0x00000000, 0x000f970c, 0x000f970c, 0x00000000 },
|
||||
{ 0x0000aadc, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
|
||||
{ 0x0000aae0, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
|
||||
{ 0x0000aae4, 0x00000000, 0x00000000, 0x000f9718, 0x000f9718, 0x00000000 },
|
||||
{ 0x0000aae8, 0x00000000, 0x00000000, 0x000f9705, 0x000f9705, 0x00000000 },
|
||||
{ 0x0000aaec, 0x00000000, 0x00000000, 0x000f9709, 0x000f9709, 0x00000000 },
|
||||
{ 0x0000aaf0, 0x00000000, 0x00000000, 0x000f970d, 0x000f970d, 0x00000000 },
|
||||
{ 0x0000aaf4, 0x00000000, 0x00000000, 0x000f9711, 0x000f9711, 0x00000000 },
|
||||
{ 0x0000aaf8, 0x00000000, 0x00000000, 0x000f9715, 0x000f9715, 0x00000000 },
|
||||
{ 0x0000aafc, 0x00000000, 0x00000000, 0x000f9719, 0x000f9719, 0x00000000 },
|
||||
{ 0x0000ab00, 0x00000000, 0x00000000, 0x000fb7a4, 0x000fb7a4, 0x00000000 },
|
||||
{ 0x0000ab04, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
|
||||
{ 0x0000ab08, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
|
||||
{ 0x0000ab0c, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
|
||||
{ 0x0000ab10, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
|
||||
{ 0x0000ab14, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
|
||||
{ 0x0000ab18, 0x00000000, 0x00000000, 0x000fb7bc, 0x000fb7bc, 0x00000000 },
|
||||
{ 0x0000ab1c, 0x00000000, 0x00000000, 0x000fb7a1, 0x000fb7a1, 0x00000000 },
|
||||
{ 0x0000ab20, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
|
||||
{ 0x0000ab24, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
|
||||
{ 0x0000ab28, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
|
||||
{ 0x0000ab2c, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
|
||||
{ 0x0000ab30, 0x00000000, 0x00000000, 0x000fb7bd, 0x000fb7bd, 0x00000000 },
|
||||
{ 0x0000ab34, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
|
||||
{ 0x0000ab38, 0x00000000, 0x00000000, 0x000fb7cd, 0x000fb7cd, 0x00000000 },
|
||||
{ 0x0000ab3c, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
|
||||
{ 0x0000ab40, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
|
||||
{ 0x0000ab44, 0x00000000, 0x00000000, 0x000fb7c2, 0x000fb7c2, 0x00000000 },
|
||||
{ 0x0000ab48, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
|
||||
{ 0x0000ab4c, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
|
||||
{ 0x0000ab50, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
|
||||
{ 0x0000ab54, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
|
||||
{ 0x0000ab58, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
|
||||
{ 0x0000ab5c, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
|
||||
{ 0x0000ab60, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
|
||||
{ 0x0000ab64, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000ab68, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000ab6c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000ab70, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000ab74, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000ab78, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000ab7c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000ab80, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000ab84, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000ab88, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000ab8c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000ab90, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000ab94, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000ab98, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000ab9c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000aba0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000aba4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000aba8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abac, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abb0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abb4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abb8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abbc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abc0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abc4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abc8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abcc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abd0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abd4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abd8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abdc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abe0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abe4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abe8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abec, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abf0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abf4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abf8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000abfc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
|
||||
{ 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
|
||||
{ 0x0000a20c, 0x00000014, 0x00000014, 0x00000000, 0x00000000, 0x0001f000 },
|
||||
{ 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
|
||||
{ 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
|
||||
{ 0x0000a250, 0x001ff000, 0x001ff000, 0x001ca000, 0x001ca000, 0x001da000 },
|
||||
{ 0x0000a274, 0x0a81c652, 0x0a81c652, 0x0a820652, 0x0a820652, 0x0a82a652 },
|
||||
{ 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x0000a304, 0x00000000, 0x00000000, 0x00007201, 0x00007201, 0x00000000 },
|
||||
{ 0x0000a308, 0x00000000, 0x00000000, 0x00010408, 0x00010408, 0x00000000 },
|
||||
{ 0x0000a30c, 0x00000000, 0x00000000, 0x0001860a, 0x0001860a, 0x00000000 },
|
||||
{ 0x0000a310, 0x00000000, 0x00000000, 0x00020818, 0x00020818, 0x00000000 },
|
||||
{ 0x0000a314, 0x00000000, 0x00000000, 0x00024858, 0x00024858, 0x00000000 },
|
||||
{ 0x0000a318, 0x00000000, 0x00000000, 0x00026859, 0x00026859, 0x00000000 },
|
||||
{ 0x0000a31c, 0x00000000, 0x00000000, 0x0002985b, 0x0002985b, 0x00000000 },
|
||||
{ 0x0000a320, 0x00000000, 0x00000000, 0x0002c89a, 0x0002c89a, 0x00000000 },
|
||||
{ 0x0000a324, 0x00000000, 0x00000000, 0x0002e89b, 0x0002e89b, 0x00000000 },
|
||||
{ 0x0000a328, 0x00000000, 0x00000000, 0x0003089c, 0x0003089c, 0x00000000 },
|
||||
{ 0x0000a32c, 0x00000000, 0x00000000, 0x0003289d, 0x0003289d, 0x00000000 },
|
||||
{ 0x0000a330, 0x00000000, 0x00000000, 0x0003489e, 0x0003489e, 0x00000000 },
|
||||
{ 0x0000a334, 0x00000000, 0x00000000, 0x000388de, 0x000388de, 0x00000000 },
|
||||
{ 0x0000a338, 0x00000000, 0x00000000, 0x0003b91e, 0x0003b91e, 0x00000000 },
|
||||
{ 0x0000a33c, 0x00000000, 0x00000000, 0x0003d95e, 0x0003d95e, 0x00000000 },
|
||||
{ 0x0000a340, 0x00000000, 0x00000000, 0x000419df, 0x000419df, 0x00000000 },
|
||||
{ 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285Common[][2] = {
|
||||
{ 0x0000000c, 0x00000000 },
|
||||
{ 0x00000030, 0x00020045 },
|
||||
{ 0x00000034, 0x00000005 },
|
||||
{ 0x00000040, 0x00000000 },
|
||||
{ 0x00000044, 0x00000008 },
|
||||
{ 0x00000048, 0x00000008 },
|
||||
{ 0x0000004c, 0x00000010 },
|
||||
{ 0x00000050, 0x00000000 },
|
||||
{ 0x00000054, 0x0000001f },
|
||||
{ 0x00000800, 0x00000000 },
|
||||
{ 0x00000804, 0x00000000 },
|
||||
{ 0x00000808, 0x00000000 },
|
||||
{ 0x0000080c, 0x00000000 },
|
||||
{ 0x00000810, 0x00000000 },
|
||||
{ 0x00000814, 0x00000000 },
|
||||
{ 0x00000818, 0x00000000 },
|
||||
{ 0x0000081c, 0x00000000 },
|
||||
{ 0x00000820, 0x00000000 },
|
||||
{ 0x00000824, 0x00000000 },
|
||||
{ 0x00001040, 0x002ffc0f },
|
||||
{ 0x00001044, 0x002ffc0f },
|
||||
{ 0x00001048, 0x002ffc0f },
|
||||
{ 0x0000104c, 0x002ffc0f },
|
||||
{ 0x00001050, 0x002ffc0f },
|
||||
{ 0x00001054, 0x002ffc0f },
|
||||
{ 0x00001058, 0x002ffc0f },
|
||||
{ 0x0000105c, 0x002ffc0f },
|
||||
{ 0x00001060, 0x002ffc0f },
|
||||
{ 0x00001064, 0x002ffc0f },
|
||||
{ 0x00001230, 0x00000000 },
|
||||
{ 0x00001270, 0x00000000 },
|
||||
{ 0x00001038, 0x00000000 },
|
||||
{ 0x00001078, 0x00000000 },
|
||||
{ 0x000010b8, 0x00000000 },
|
||||
{ 0x000010f8, 0x00000000 },
|
||||
{ 0x00001138, 0x00000000 },
|
||||
{ 0x00001178, 0x00000000 },
|
||||
{ 0x000011b8, 0x00000000 },
|
||||
{ 0x000011f8, 0x00000000 },
|
||||
{ 0x00001238, 0x00000000 },
|
||||
{ 0x00001278, 0x00000000 },
|
||||
{ 0x000012b8, 0x00000000 },
|
||||
{ 0x000012f8, 0x00000000 },
|
||||
{ 0x00001338, 0x00000000 },
|
||||
{ 0x00001378, 0x00000000 },
|
||||
{ 0x000013b8, 0x00000000 },
|
||||
{ 0x000013f8, 0x00000000 },
|
||||
{ 0x00001438, 0x00000000 },
|
||||
{ 0x00001478, 0x00000000 },
|
||||
{ 0x000014b8, 0x00000000 },
|
||||
{ 0x000014f8, 0x00000000 },
|
||||
{ 0x00001538, 0x00000000 },
|
||||
{ 0x00001578, 0x00000000 },
|
||||
{ 0x000015b8, 0x00000000 },
|
||||
{ 0x000015f8, 0x00000000 },
|
||||
{ 0x00001638, 0x00000000 },
|
||||
{ 0x00001678, 0x00000000 },
|
||||
{ 0x000016b8, 0x00000000 },
|
||||
{ 0x000016f8, 0x00000000 },
|
||||
{ 0x00001738, 0x00000000 },
|
||||
{ 0x00001778, 0x00000000 },
|
||||
{ 0x000017b8, 0x00000000 },
|
||||
{ 0x000017f8, 0x00000000 },
|
||||
{ 0x0000103c, 0x00000000 },
|
||||
{ 0x0000107c, 0x00000000 },
|
||||
{ 0x000010bc, 0x00000000 },
|
||||
{ 0x000010fc, 0x00000000 },
|
||||
{ 0x0000113c, 0x00000000 },
|
||||
{ 0x0000117c, 0x00000000 },
|
||||
{ 0x000011bc, 0x00000000 },
|
||||
{ 0x000011fc, 0x00000000 },
|
||||
{ 0x0000123c, 0x00000000 },
|
||||
{ 0x0000127c, 0x00000000 },
|
||||
{ 0x000012bc, 0x00000000 },
|
||||
{ 0x000012fc, 0x00000000 },
|
||||
{ 0x0000133c, 0x00000000 },
|
||||
{ 0x0000137c, 0x00000000 },
|
||||
{ 0x000013bc, 0x00000000 },
|
||||
{ 0x000013fc, 0x00000000 },
|
||||
{ 0x0000143c, 0x00000000 },
|
||||
{ 0x0000147c, 0x00000000 },
|
||||
{ 0x00004030, 0x00000002 },
|
||||
{ 0x0000403c, 0x00000002 },
|
||||
{ 0x00004024, 0x0000001f },
|
||||
{ 0x00004060, 0x00000000 },
|
||||
{ 0x00004064, 0x00000000 },
|
||||
{ 0x00007010, 0x00000031 },
|
||||
{ 0x00007034, 0x00000002 },
|
||||
{ 0x00007038, 0x000004c2 },
|
||||
{ 0x00008004, 0x00000000 },
|
||||
{ 0x00008008, 0x00000000 },
|
||||
{ 0x0000800c, 0x00000000 },
|
||||
{ 0x00008018, 0x00000700 },
|
||||
{ 0x00008020, 0x00000000 },
|
||||
{ 0x00008038, 0x00000000 },
|
||||
{ 0x0000803c, 0x00000000 },
|
||||
{ 0x00008048, 0x00000000 },
|
||||
{ 0x00008054, 0x00000000 },
|
||||
{ 0x00008058, 0x00000000 },
|
||||
{ 0x0000805c, 0x000fc78f },
|
||||
{ 0x00008060, 0x0000000f },
|
||||
{ 0x00008064, 0x00000000 },
|
||||
{ 0x00008070, 0x00000000 },
|
||||
{ 0x000080c0, 0x2a80001a },
|
||||
{ 0x000080c4, 0x05dc01e0 },
|
||||
{ 0x000080c8, 0x1f402710 },
|
||||
{ 0x000080cc, 0x01f40000 },
|
||||
{ 0x000080d0, 0x00001e00 },
|
||||
{ 0x000080d4, 0x00000000 },
|
||||
{ 0x000080d8, 0x00400000 },
|
||||
{ 0x000080e0, 0xffffffff },
|
||||
{ 0x000080e4, 0x0000ffff },
|
||||
{ 0x000080e8, 0x003f3f3f },
|
||||
{ 0x000080ec, 0x00000000 },
|
||||
{ 0x000080f0, 0x00000000 },
|
||||
{ 0x000080f4, 0x00000000 },
|
||||
{ 0x000080f8, 0x00000000 },
|
||||
{ 0x000080fc, 0x00020000 },
|
||||
{ 0x00008100, 0x00020000 },
|
||||
{ 0x00008104, 0x00000001 },
|
||||
{ 0x00008108, 0x00000052 },
|
||||
{ 0x0000810c, 0x00000000 },
|
||||
{ 0x00008110, 0x00000168 },
|
||||
{ 0x00008118, 0x000100aa },
|
||||
{ 0x0000811c, 0x00003210 },
|
||||
{ 0x00008120, 0x08f04800 },
|
||||
{ 0x00008124, 0x00000000 },
|
||||
{ 0x00008128, 0x00000000 },
|
||||
{ 0x0000812c, 0x00000000 },
|
||||
{ 0x00008130, 0x00000000 },
|
||||
{ 0x00008134, 0x00000000 },
|
||||
{ 0x00008138, 0x00000000 },
|
||||
{ 0x0000813c, 0x00000000 },
|
||||
{ 0x00008144, 0x00000000 },
|
||||
{ 0x00008168, 0x00000000 },
|
||||
{ 0x0000816c, 0x00000000 },
|
||||
{ 0x00008170, 0x32143320 },
|
||||
{ 0x00008174, 0xfaa4fa50 },
|
||||
{ 0x00008178, 0x00000100 },
|
||||
{ 0x0000817c, 0x00000000 },
|
||||
{ 0x000081c0, 0x00000000 },
|
||||
{ 0x000081d0, 0x00003210 },
|
||||
{ 0x000081ec, 0x00000000 },
|
||||
{ 0x000081f0, 0x00000000 },
|
||||
{ 0x000081f4, 0x00000000 },
|
||||
{ 0x000081f8, 0x00000000 },
|
||||
{ 0x000081fc, 0x00000000 },
|
||||
{ 0x00008200, 0x00000000 },
|
||||
{ 0x00008204, 0x00000000 },
|
||||
{ 0x00008208, 0x00000000 },
|
||||
{ 0x0000820c, 0x00000000 },
|
||||
{ 0x00008210, 0x00000000 },
|
||||
{ 0x00008214, 0x00000000 },
|
||||
{ 0x00008218, 0x00000000 },
|
||||
{ 0x0000821c, 0x00000000 },
|
||||
{ 0x00008220, 0x00000000 },
|
||||
{ 0x00008224, 0x00000000 },
|
||||
{ 0x00008228, 0x00000000 },
|
||||
{ 0x0000822c, 0x00000000 },
|
||||
{ 0x00008230, 0x00000000 },
|
||||
{ 0x00008234, 0x00000000 },
|
||||
{ 0x00008238, 0x00000000 },
|
||||
{ 0x0000823c, 0x00000000 },
|
||||
{ 0x00008240, 0x00100000 },
|
||||
{ 0x00008244, 0x0010f400 },
|
||||
{ 0x00008248, 0x00000100 },
|
||||
{ 0x0000824c, 0x0001e800 },
|
||||
{ 0x00008250, 0x00000000 },
|
||||
{ 0x00008254, 0x00000000 },
|
||||
{ 0x00008258, 0x00000000 },
|
||||
{ 0x0000825c, 0x400000ff },
|
||||
{ 0x00008260, 0x00080922 },
|
||||
{ 0x00008264, 0xa8a00010 },
|
||||
{ 0x00008270, 0x00000000 },
|
||||
{ 0x00008274, 0x40000000 },
|
||||
{ 0x00008278, 0x003e4180 },
|
||||
{ 0x0000827c, 0x00000000 },
|
||||
{ 0x00008284, 0x0000002c },
|
||||
{ 0x00008288, 0x0000002c },
|
||||
{ 0x0000828c, 0x00000000 },
|
||||
{ 0x00008294, 0x00000000 },
|
||||
{ 0x00008298, 0x00000000 },
|
||||
{ 0x0000829c, 0x00000000 },
|
||||
{ 0x00008300, 0x00000040 },
|
||||
{ 0x00008314, 0x00000000 },
|
||||
{ 0x00008328, 0x00000000 },
|
||||
{ 0x0000832c, 0x00000001 },
|
||||
{ 0x00008330, 0x00000302 },
|
||||
{ 0x00008334, 0x00000e00 },
|
||||
{ 0x00008338, 0x00000000 },
|
||||
{ 0x0000833c, 0x00000000 },
|
||||
{ 0x00008340, 0x00010380 },
|
||||
{ 0x00008344, 0x00481043 },
|
||||
{ 0x00009808, 0x00000000 },
|
||||
{ 0x0000980c, 0xafe68e30 },
|
||||
{ 0x00009810, 0xfd14e000 },
|
||||
{ 0x00009814, 0x9c0a9f6b },
|
||||
{ 0x0000981c, 0x00000000 },
|
||||
{ 0x0000982c, 0x0000a000 },
|
||||
{ 0x00009830, 0x00000000 },
|
||||
{ 0x0000983c, 0x00200400 },
|
||||
{ 0x0000984c, 0x0040233c },
|
||||
{ 0x00009854, 0x00000044 },
|
||||
{ 0x00009900, 0x00000000 },
|
||||
{ 0x00009904, 0x00000000 },
|
||||
{ 0x00009908, 0x00000000 },
|
||||
{ 0x0000990c, 0x00000000 },
|
||||
{ 0x00009910, 0x01002310 },
|
||||
{ 0x0000991c, 0x10000fff },
|
||||
{ 0x00009920, 0x04900000 },
|
||||
{ 0x00009928, 0x00000001 },
|
||||
{ 0x0000992c, 0x00000004 },
|
||||
{ 0x00009934, 0x1e1f2022 },
|
||||
{ 0x00009938, 0x0a0b0c0d },
|
||||
{ 0x0000993c, 0x00000000 },
|
||||
{ 0x00009940, 0x14750604 },
|
||||
{ 0x00009948, 0x9280c00a },
|
||||
{ 0x0000994c, 0x00020028 },
|
||||
{ 0x00009954, 0x5f3ca3de },
|
||||
{ 0x00009958, 0x2108ecff },
|
||||
{ 0x00009968, 0x000003ce },
|
||||
{ 0x00009970, 0x1927b515 },
|
||||
{ 0x00009974, 0x00000000 },
|
||||
{ 0x00009978, 0x00000001 },
|
||||
{ 0x0000997c, 0x00000000 },
|
||||
{ 0x00009980, 0x00000000 },
|
||||
{ 0x00009984, 0x00000000 },
|
||||
{ 0x00009988, 0x00000000 },
|
||||
{ 0x0000998c, 0x00000000 },
|
||||
{ 0x00009990, 0x00000000 },
|
||||
{ 0x00009994, 0x00000000 },
|
||||
{ 0x00009998, 0x00000000 },
|
||||
{ 0x0000999c, 0x00000000 },
|
||||
{ 0x000099a0, 0x00000000 },
|
||||
{ 0x000099a4, 0x00000001 },
|
||||
{ 0x000099a8, 0x201fff00 },
|
||||
{ 0x000099ac, 0x2def0a00 },
|
||||
{ 0x000099b0, 0x03051000 },
|
||||
{ 0x000099b4, 0x00000820 },
|
||||
{ 0x000099dc, 0x00000000 },
|
||||
{ 0x000099e0, 0x00000000 },
|
||||
{ 0x000099e4, 0xaaaaaaaa },
|
||||
{ 0x000099e8, 0x3c466478 },
|
||||
{ 0x000099ec, 0x0cc80caa },
|
||||
{ 0x000099f0, 0x00000000 },
|
||||
{ 0x0000a208, 0x803e6788 },
|
||||
{ 0x0000a210, 0x4080a333 },
|
||||
{ 0x0000a214, 0x00206c10 },
|
||||
{ 0x0000a218, 0x009c4060 },
|
||||
{ 0x0000a220, 0x01834061 },
|
||||
{ 0x0000a224, 0x00000400 },
|
||||
{ 0x0000a228, 0x000003b5 },
|
||||
{ 0x0000a22c, 0x00000000 },
|
||||
{ 0x0000a234, 0x20202020 },
|
||||
{ 0x0000a238, 0x20202020 },
|
||||
{ 0x0000a244, 0x00000000 },
|
||||
{ 0x0000a248, 0xfffffffc },
|
||||
{ 0x0000a24c, 0x00000000 },
|
||||
{ 0x0000a254, 0x00000000 },
|
||||
{ 0x0000a258, 0x0ccb5380 },
|
||||
{ 0x0000a25c, 0x15151501 },
|
||||
{ 0x0000a260, 0xdfa90f01 },
|
||||
{ 0x0000a268, 0x00000000 },
|
||||
{ 0x0000a26c, 0x0ebae9e6 },
|
||||
{ 0x0000d270, 0x0d820820 },
|
||||
{ 0x0000a278, 0x39ce739c },
|
||||
{ 0x0000a27c, 0x050e039c },
|
||||
{ 0x0000d35c, 0x07ffffef },
|
||||
{ 0x0000d360, 0x0fffffe7 },
|
||||
{ 0x0000d364, 0x17ffffe5 },
|
||||
{ 0x0000d368, 0x1fffffe4 },
|
||||
{ 0x0000d36c, 0x37ffffe3 },
|
||||
{ 0x0000d370, 0x3fffffe3 },
|
||||
{ 0x0000d374, 0x57ffffe3 },
|
||||
{ 0x0000d378, 0x5fffffe2 },
|
||||
{ 0x0000d37c, 0x7fffffe2 },
|
||||
{ 0x0000d380, 0x7f3c7bba },
|
||||
{ 0x0000d384, 0xf3307ff0 },
|
||||
{ 0x0000a388, 0x0c000000 },
|
||||
{ 0x0000a38c, 0x20202020 },
|
||||
{ 0x0000a390, 0x20202020 },
|
||||
{ 0x0000a394, 0x39ce739c },
|
||||
{ 0x0000a398, 0x0000039c },
|
||||
{ 0x0000a39c, 0x00000001 },
|
||||
{ 0x0000a3a0, 0x00000000 },
|
||||
{ 0x0000a3a4, 0x00000000 },
|
||||
{ 0x0000a3a8, 0x00000000 },
|
||||
{ 0x0000a3ac, 0x00000000 },
|
||||
{ 0x0000a3b0, 0x00000000 },
|
||||
{ 0x0000a3b4, 0x00000000 },
|
||||
{ 0x0000a3b8, 0x00000000 },
|
||||
{ 0x0000a3bc, 0x00000000 },
|
||||
{ 0x0000a3c0, 0x00000000 },
|
||||
{ 0x0000a3c4, 0x00000000 },
|
||||
{ 0x0000a3cc, 0x20202020 },
|
||||
{ 0x0000a3d0, 0x20202020 },
|
||||
{ 0x0000a3d4, 0x20202020 },
|
||||
{ 0x0000a3dc, 0x39ce739c },
|
||||
{ 0x0000a3e0, 0x0000039c },
|
||||
{ 0x0000a3e4, 0x00000000 },
|
||||
{ 0x0000a3e8, 0x18c43433 },
|
||||
{ 0x0000a3ec, 0x00f70081 },
|
||||
{ 0x00007800, 0x00140000 },
|
||||
{ 0x00007804, 0x0e4548d8 },
|
||||
{ 0x00007808, 0x54214514 },
|
||||
{ 0x0000780c, 0x02025820 },
|
||||
{ 0x00007810, 0x71c0d388 },
|
||||
{ 0x00007814, 0x924934a8 },
|
||||
{ 0x0000781c, 0x00000000 },
|
||||
{ 0x00007820, 0x00000c04 },
|
||||
{ 0x00007824, 0x00d86fff },
|
||||
{ 0x00007828, 0x26d2491b },
|
||||
{ 0x0000782c, 0x6e36d97b },
|
||||
{ 0x00007830, 0xedb6d96c },
|
||||
{ 0x00007834, 0x71400086 },
|
||||
{ 0x00007838, 0xfac68800 },
|
||||
{ 0x0000783c, 0x0001fffe },
|
||||
{ 0x00007840, 0xffeb1a20 },
|
||||
{ 0x00007844, 0x000c0db6 },
|
||||
{ 0x00007848, 0x6db61b6f },
|
||||
{ 0x0000784c, 0x6d9b66db },
|
||||
{ 0x00007850, 0x6d8c6dba },
|
||||
{ 0x00007854, 0x00040000 },
|
||||
{ 0x00007858, 0xdb003012 },
|
||||
{ 0x0000785c, 0x04924914 },
|
||||
{ 0x00007860, 0x21084210 },
|
||||
{ 0x00007864, 0xf7d7ffde },
|
||||
{ 0x00007868, 0xc2034080 },
|
||||
{ 0x0000786c, 0x48609eb4 },
|
||||
{ 0x00007870, 0x10142c00 },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285PciePhy_clkreq_always_on_L1[][2] = {
|
||||
{0x00004040, 0x9248fd00 },
|
||||
{0x00004040, 0x24924924 },
|
||||
{0x00004040, 0xa8000019 },
|
||||
{0x00004040, 0x13160820 },
|
||||
{0x00004040, 0xe5980560 },
|
||||
{0x00004040, 0xc01dcffd },
|
||||
{0x00004040, 0x1aaabe41 },
|
||||
{0x00004040, 0xbe105554 },
|
||||
{0x00004040, 0x00043007 },
|
||||
{0x00004044, 0x00000000 },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285PciePhy_clkreq_off_L1[][2] = {
|
||||
{0x00004040, 0x9248fd00 },
|
||||
{0x00004040, 0x24924924 },
|
||||
{0x00004040, 0xa8000019 },
|
||||
{0x00004040, 0x13160820 },
|
||||
{0x00004040, 0xe5980560 },
|
||||
{0x00004040, 0xc01dcffc },
|
||||
{0x00004040, 0x1aaabe41 },
|
||||
{0x00004040, 0xbe105554 },
|
||||
{0x00004040, 0x00043007 },
|
||||
{0x00004044, 0x00000000 },
|
||||
};
|
||||
+395
@@ -0,0 +1,395 @@
|
||||
/*
|
||||
* Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
|
||||
* Copyright (c) 2008 Atheros Communications, Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#include "opt_ah.h"
|
||||
|
||||
#include "ah.h"
|
||||
#include "ah_internal.h"
|
||||
#include "ah_devid.h"
|
||||
|
||||
#include "ah_eeprom_v4k.h" /* XXX for tx/rx gain */
|
||||
|
||||
#include "ar5416/ar9280.h"
|
||||
#include "ar5416/ar9285.h"
|
||||
#include "ar5416/ar5416reg.h"
|
||||
#include "ar5416/ar5416phy.h"
|
||||
|
||||
#include "ar5416/ar9285.ini"
|
||||
#include "ar5416/ar9285v2.ini"
|
||||
#include "ar5416/ar9280v2.ini" /* XXX ini for tx/rx gain */
|
||||
|
||||
static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */
|
||||
.calName = "IQ", .calType = IQ_MISMATCH_CAL,
|
||||
.calNumSamples = MIN_CAL_SAMPLES,
|
||||
.calCountMax = PER_MAX_LOG_COUNT,
|
||||
.calCollect = ar5416IQCalCollect,
|
||||
.calPostProc = ar5416IQCalibration
|
||||
};
|
||||
static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */
|
||||
.calName = "ADC Gain", .calType = ADC_GAIN_CAL,
|
||||
.calNumSamples = MIN_CAL_SAMPLES,
|
||||
.calCountMax = PER_MIN_LOG_COUNT,
|
||||
.calCollect = ar5416AdcGainCalCollect,
|
||||
.calPostProc = ar5416AdcGainCalibration
|
||||
};
|
||||
static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */
|
||||
.calName = "ADC DC", .calType = ADC_DC_CAL,
|
||||
.calNumSamples = MIN_CAL_SAMPLES,
|
||||
.calCountMax = PER_MIN_LOG_COUNT,
|
||||
.calCollect = ar5416AdcDcCalCollect,
|
||||
.calPostProc = ar5416AdcDcCalibration
|
||||
};
|
||||
static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = {
|
||||
.calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
|
||||
.calNumSamples = MIN_CAL_SAMPLES,
|
||||
.calCountMax = INIT_LOG_COUNT,
|
||||
.calCollect = ar5416AdcDcCalCollect,
|
||||
.calPostProc = ar5416AdcDcCalibration
|
||||
};
|
||||
|
||||
static void ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
|
||||
static HAL_BOOL ar9285FillCapabilityInfo(struct ath_hal *ah);
|
||||
static void ar9285WriteIni(struct ath_hal *ah,
|
||||
const struct ieee80211_channel *chan);
|
||||
|
||||
static void
|
||||
ar9285AniSetup(struct ath_hal *ah)
|
||||
{
|
||||
/* NB: disable ANI for reliable RIFS rx */
|
||||
ar5212AniAttach(ah, AH_NULL, AH_NULL, AH_FALSE);
|
||||
}
|
||||
|
||||
/*
|
||||
* Attach for an AR9285 part.
|
||||
*/
|
||||
static struct ath_hal *
|
||||
ar9285Attach(uint16_t devid, HAL_SOFTC sc,
|
||||
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
|
||||
{
|
||||
struct ath_hal_9285 *ahp9285;
|
||||
struct ath_hal_5212 *ahp;
|
||||
struct ath_hal *ah;
|
||||
uint32_t val;
|
||||
HAL_STATUS ecode;
|
||||
HAL_BOOL rfStatus;
|
||||
|
||||
HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
|
||||
__func__, sc, (void*) st, (void*) sh);
|
||||
|
||||
/* NB: memory is returned zero'd */
|
||||
ahp9285 = ath_hal_malloc(sizeof (struct ath_hal_9285));
|
||||
if (ahp9285 == AH_NULL) {
|
||||
HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
|
||||
"%s: cannot allocate memory for state block\n", __func__);
|
||||
*status = HAL_ENOMEM;
|
||||
return AH_NULL;
|
||||
}
|
||||
ahp = AH5212(ahp9285);
|
||||
ah = &ahp->ah_priv.h;
|
||||
|
||||
ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
|
||||
|
||||
/* XXX override with 9285 specific state */
|
||||
/* override 5416 methods for our needs */
|
||||
ah->ah_setAntennaSwitch = ar9285SetAntennaSwitch;
|
||||
ah->ah_configPCIE = ar9285ConfigPCIE;
|
||||
ah->ah_setTxPower = ar9285SetTransmitPower;
|
||||
ah->ah_setBoardValues = ar9285SetBoardValues;
|
||||
|
||||
AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
|
||||
AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
|
||||
AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
|
||||
AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
|
||||
AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
|
||||
|
||||
AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
|
||||
AH5416(ah)->ah_writeIni = ar9285WriteIni;
|
||||
AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;
|
||||
AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK;
|
||||
|
||||
if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
|
||||
/* reset chip */
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
|
||||
__func__);
|
||||
ecode = HAL_EIO;
|
||||
goto bad;
|
||||
}
|
||||
|
||||
if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
|
||||
__func__);
|
||||
ecode = HAL_EIO;
|
||||
goto bad;
|
||||
}
|
||||
/* Read Revisions from Chips before taking out of reset */
|
||||
val = OS_REG_READ(ah, AR_SREV);
|
||||
HALDEBUG(ah, HAL_DEBUG_ATTACH,
|
||||
"%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
|
||||
__func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
|
||||
MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
|
||||
/* NB: include chip type to differentiate from pre-Sowl versions */
|
||||
AH_PRIVATE(ah)->ah_macVersion =
|
||||
(val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
|
||||
AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
|
||||
AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
|
||||
|
||||
/* setup common ini data; rf backends handle remainder */
|
||||
if (AR_SREV_KITE_12_OR_LATER(ah)) {
|
||||
HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6);
|
||||
HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2);
|
||||
HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
|
||||
ar9285PciePhy_clkreq_always_on_L1_v2, 2);
|
||||
} else {
|
||||
HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6);
|
||||
HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2);
|
||||
HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
|
||||
ar9285PciePhy_clkreq_always_on_L1, 2);
|
||||
}
|
||||
ar5416AttachPCIE(ah);
|
||||
|
||||
ecode = ath_hal_v4kEepromAttach(ah);
|
||||
if (ecode != HAL_OK)
|
||||
goto bad;
|
||||
|
||||
if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
|
||||
__func__);
|
||||
ecode = HAL_EIO;
|
||||
goto bad;
|
||||
}
|
||||
|
||||
AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
|
||||
|
||||
if (!ar5212ChipTest(ah)) {
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
|
||||
__func__);
|
||||
ecode = HAL_ESELFTEST;
|
||||
goto bad;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set correct Baseband to analog shift
|
||||
* setting to access analog chips.
|
||||
*/
|
||||
OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
|
||||
|
||||
/* Read Radio Chip Rev Extract */
|
||||
AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
|
||||
switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
|
||||
case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
|
||||
case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
|
||||
break;
|
||||
default:
|
||||
if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
|
||||
AH_PRIVATE(ah)->ah_analog5GhzRev =
|
||||
AR_RAD5133_SREV_MAJOR;
|
||||
break;
|
||||
}
|
||||
#ifdef AH_DEBUG
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY,
|
||||
"%s: 5G Radio Chip Rev 0x%02X is not supported by "
|
||||
"this driver\n", __func__,
|
||||
AH_PRIVATE(ah)->ah_analog5GhzRev);
|
||||
ecode = HAL_ENOTSUPP;
|
||||
goto bad;
|
||||
#endif
|
||||
}
|
||||
rfStatus = ar9285RfAttach(ah, &ecode);
|
||||
if (!rfStatus) {
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
|
||||
__func__, ecode);
|
||||
goto bad;
|
||||
}
|
||||
|
||||
HAL_INI_INIT(&ahp9285->ah_ini_rxgain, ar9280Modes_original_rxgain_v2,
|
||||
6);
|
||||
/* setup txgain table */
|
||||
switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
|
||||
case AR5416_EEP_TXGAIN_HIGH_POWER:
|
||||
HAL_INI_INIT(&ahp9285->ah_ini_txgain,
|
||||
ar9285Modes_high_power_tx_gain_v2, 6);
|
||||
break;
|
||||
case AR5416_EEP_TXGAIN_ORIG:
|
||||
HAL_INI_INIT(&ahp9285->ah_ini_txgain,
|
||||
ar9285Modes_original_tx_gain_v2, 6);
|
||||
break;
|
||||
default:
|
||||
HALASSERT(AH_FALSE);
|
||||
goto bad; /* XXX ? try to continue */
|
||||
}
|
||||
|
||||
/*
|
||||
* Got everything we need now to setup the capabilities.
|
||||
*/
|
||||
if (!ar9285FillCapabilityInfo(ah)) {
|
||||
ecode = HAL_EEREAD;
|
||||
goto bad;
|
||||
}
|
||||
|
||||
ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
|
||||
if (ecode != HAL_OK) {
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY,
|
||||
"%s: error getting mac address from EEPROM\n", __func__);
|
||||
goto bad;
|
||||
}
|
||||
/* XXX How about the serial number ? */
|
||||
/* Read Reg Domain */
|
||||
AH_PRIVATE(ah)->ah_currentRD =
|
||||
ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
|
||||
|
||||
/*
|
||||
* ah_miscMode is populated by ar5416FillCapabilityInfo()
|
||||
* starting from griffin. Set here to make sure that
|
||||
* AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
|
||||
* placed into hardware.
|
||||
*/
|
||||
if (ahp->ah_miscMode != 0)
|
||||
OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
|
||||
|
||||
ar9285AniSetup(ah); /* Anti Noise Immunity */
|
||||
ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
|
||||
|
||||
HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
|
||||
|
||||
return ah;
|
||||
bad:
|
||||
if (ah != AH_NULL)
|
||||
ah->ah_detach(ah);
|
||||
if (status)
|
||||
*status = ecode;
|
||||
return AH_NULL;
|
||||
}
|
||||
|
||||
static void
|
||||
ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
|
||||
{
|
||||
if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
|
||||
ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
|
||||
OS_DELAY(1000);
|
||||
OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
|
||||
OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
ar9285WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
|
||||
{
|
||||
u_int modesIndex, freqIndex;
|
||||
int regWrites = 0;
|
||||
|
||||
/* Setup the indices for the next set of register array writes */
|
||||
/* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
|
||||
freqIndex = 2;
|
||||
if (IEEE80211_IS_CHAN_HT40(chan))
|
||||
modesIndex = 3;
|
||||
else if (IEEE80211_IS_CHAN_108G(chan))
|
||||
modesIndex = 5;
|
||||
else
|
||||
modesIndex = 4;
|
||||
|
||||
/* Set correct Baseband to analog shift setting to access analog chips. */
|
||||
OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
|
||||
OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
|
||||
regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
|
||||
modesIndex, regWrites);
|
||||
if (AR_SREV_KITE_12_OR_LATER(ah)) {
|
||||
regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain,
|
||||
modesIndex, regWrites);
|
||||
}
|
||||
regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
|
||||
1, regWrites);
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Fill all software cached or static hardware state information.
|
||||
* Return failure if capabilities are to come from EEPROM and
|
||||
* cannot be read.
|
||||
*/
|
||||
static HAL_BOOL
|
||||
ar9285FillCapabilityInfo(struct ath_hal *ah)
|
||||
{
|
||||
HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
|
||||
|
||||
if (!ar5416FillCapabilityInfo(ah))
|
||||
return AH_FALSE;
|
||||
pCap->halNumGpioPins = 12;
|
||||
pCap->halWowSupport = AH_TRUE;
|
||||
pCap->halWowMatchPatternExact = AH_TRUE;
|
||||
#if 0
|
||||
pCap->halWowMatchPatternDword = AH_TRUE;
|
||||
#endif
|
||||
pCap->halCSTSupport = AH_TRUE;
|
||||
pCap->halRifsRxSupport = AH_TRUE;
|
||||
pCap->halRifsTxSupport = AH_TRUE;
|
||||
pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
|
||||
pCap->halExtChanDfsSupport = AH_TRUE;
|
||||
#if 0
|
||||
/* XXX bluetooth */
|
||||
pCap->halBtCoexSupport = AH_TRUE;
|
||||
#endif
|
||||
pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
|
||||
#if 0
|
||||
pCap->hal4kbSplitTransSupport = AH_FALSE;
|
||||
#endif
|
||||
pCap->halRxStbcSupport = 1;
|
||||
pCap->halTxStbcSupport = 1;
|
||||
|
||||
return AH_TRUE;
|
||||
}
|
||||
|
||||
HAL_BOOL
|
||||
ar9285SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
|
||||
{
|
||||
#define ANTENNA0_CHAINMASK 0x1
|
||||
#define ANTENNA1_CHAINMASK 0x2
|
||||
struct ath_hal_5416 *ahp = AH5416(ah);
|
||||
|
||||
/* Antenna selection is done by setting the tx/rx chainmasks approp. */
|
||||
switch (settings) {
|
||||
case HAL_ANT_FIXED_A:
|
||||
/* Enable first antenna only */
|
||||
ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK;
|
||||
ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK;
|
||||
break;
|
||||
case HAL_ANT_FIXED_B:
|
||||
/* Enable second antenna only, after checking capability */
|
||||
if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK)
|
||||
ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK;
|
||||
ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK;
|
||||
break;
|
||||
case HAL_ANT_VARIABLE:
|
||||
/* Restore original chainmask settings */
|
||||
/* XXX */
|
||||
ahp->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK;
|
||||
ahp->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK;
|
||||
break;
|
||||
}
|
||||
return AH_TRUE;
|
||||
#undef ANTENNA0_CHAINMASK
|
||||
#undef ANTENNA1_CHAINMASK
|
||||
}
|
||||
|
||||
static const char*
|
||||
ar9285Probe(uint16_t vendorid, uint16_t devid)
|
||||
{
|
||||
if (vendorid == ATHEROS_VENDOR_ID && devid == AR9285_DEVID_PCIE)
|
||||
return "Atheros 9285";
|
||||
return AH_NULL;
|
||||
}
|
||||
AH_CHIP(AR9285, ar9285Probe, ar9285Attach);
|
||||
+951
@@ -0,0 +1,951 @@
|
||||
/*
|
||||
* Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
|
||||
* Copyright (c) 2002-2008 Atheros Communications, Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/*
|
||||
* This is almost the same as ar5416_reset.c but uses the v4k EEPROM and
|
||||
* supports only 2Ghz operation.
|
||||
*/
|
||||
|
||||
#include "opt_ah.h"
|
||||
|
||||
#include "ah.h"
|
||||
#include "ah_internal.h"
|
||||
#include "ah_devid.h"
|
||||
|
||||
#include "ah_eeprom_v14.h"
|
||||
#include "ah_eeprom_v4k.h"
|
||||
|
||||
#include "ar5416/ar9285.h"
|
||||
#include "ar5416/ar5416.h"
|
||||
#include "ar5416/ar5416reg.h"
|
||||
#include "ar5416/ar5416phy.h"
|
||||
|
||||
/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */
|
||||
#define EEP_MINOR(_ah) \
|
||||
(AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)
|
||||
#define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2)
|
||||
#define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3)
|
||||
|
||||
/* Additional Time delay to wait after activiting the Base band */
|
||||
#define BASE_ACTIVATE_DELAY 100 /* 100 usec */
|
||||
#define PLL_SETTLE_DELAY 300 /* 300 usec */
|
||||
#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */
|
||||
|
||||
static HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah,
|
||||
struct ar5416eeprom_4k *pEepData,
|
||||
const struct ieee80211_channel *chan, int16_t *ratesArray,
|
||||
uint16_t cfgCtl, uint16_t AntennaReduction,
|
||||
uint16_t twiceMaxRegulatoryPower,
|
||||
uint16_t powerLimit);
|
||||
static HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah,
|
||||
struct ar5416eeprom_4k *pEepData,
|
||||
const struct ieee80211_channel *chan,
|
||||
int16_t *pTxPowerIndexOffset);
|
||||
static int16_t interpolate(uint16_t target, uint16_t srcLeft,
|
||||
uint16_t srcRight, int16_t targetLeft, int16_t targetRight);
|
||||
static HAL_BOOL ar9285FillVpdTable(uint8_t, uint8_t, uint8_t *, uint8_t *,
|
||||
uint16_t, uint8_t *);
|
||||
static void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah,
|
||||
const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ_4K *pRawDataSet,
|
||||
uint8_t * bChans, uint16_t availPiers,
|
||||
uint16_t tPdGainOverlap, int16_t *pMinCalPower,
|
||||
uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues,
|
||||
uint16_t numXpdGains);
|
||||
static HAL_BOOL getLowerUpperIndex(uint8_t target, uint8_t *pList,
|
||||
uint16_t listSize, uint16_t *indexL, uint16_t *indexR);
|
||||
static uint16_t ar9285GetMaxEdgePower(uint16_t, CAL_CTL_EDGES *);
|
||||
|
||||
/* XXX gag, this is sick */
|
||||
typedef enum Ar5416_Rates {
|
||||
rate6mb, rate9mb, rate12mb, rate18mb,
|
||||
rate24mb, rate36mb, rate48mb, rate54mb,
|
||||
rate1l, rate2l, rate2s, rate5_5l,
|
||||
rate5_5s, rate11l, rate11s, rateXr,
|
||||
rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
|
||||
rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
|
||||
rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
|
||||
rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
|
||||
rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
|
||||
Ar5416RateSize
|
||||
} AR5416_RATES;
|
||||
|
||||
HAL_BOOL
|
||||
ar9285SetTransmitPower(struct ath_hal *ah,
|
||||
const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
|
||||
{
|
||||
#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
|
||||
#define N(a) (sizeof (a) / sizeof (a[0]))
|
||||
|
||||
MODAL_EEP4K_HEADER *pModal;
|
||||
struct ath_hal_5212 *ahp = AH5212(ah);
|
||||
int16_t ratesArray[Ar5416RateSize];
|
||||
int16_t txPowerIndexOffset = 0;
|
||||
uint8_t ht40PowerIncForPdadc = 2;
|
||||
int i;
|
||||
|
||||
uint16_t cfgCtl;
|
||||
uint16_t powerLimit;
|
||||
uint16_t twiceAntennaReduction;
|
||||
uint16_t twiceMaxRegulatoryPower;
|
||||
int16_t maxPower;
|
||||
HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
|
||||
struct ar5416eeprom_4k *pEepData = &ee->ee_base;
|
||||
|
||||
HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
|
||||
|
||||
/* Setup info for the actual eeprom */
|
||||
OS_MEMZERO(ratesArray, sizeof(ratesArray));
|
||||
cfgCtl = ath_hal_getctl(ah, chan);
|
||||
powerLimit = chan->ic_maxregpower * 2;
|
||||
twiceAntennaReduction = chan->ic_maxantgain;
|
||||
twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);
|
||||
pModal = &pEepData->modalHeader;
|
||||
HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
|
||||
__func__,chan->ic_freq, cfgCtl );
|
||||
|
||||
if (IS_EEP_MINOR_V2(ah)) {
|
||||
ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
|
||||
}
|
||||
|
||||
if (!ar9285SetPowerPerRateTable(ah, pEepData, chan,
|
||||
&ratesArray[0],cfgCtl,
|
||||
twiceAntennaReduction,
|
||||
twiceMaxRegulatoryPower, powerLimit)) {
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY,
|
||||
"%s: unable to set tx power per rate table\n", __func__);
|
||||
return AH_FALSE;
|
||||
}
|
||||
|
||||
if (!ar9285SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) {
|
||||
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",
|
||||
__func__);
|
||||
return AH_FALSE;
|
||||
}
|
||||
|
||||
maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]);
|
||||
maxPower = AH_MAX(maxPower, ratesArray[rate1l]);
|
||||
|
||||
if (IEEE80211_IS_CHAN_HT40(chan)) {
|
||||
maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]);
|
||||
}
|
||||
|
||||
ahp->ah_tx6PowerInHalfDbm = maxPower;
|
||||
AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower;
|
||||
ahp->ah_txPowerIndexOffset = txPowerIndexOffset;
|
||||
|
||||
/*
|
||||
* txPowerIndexOffset is set by the SetPowerTable() call -
|
||||
* adjust the rate table (0 offset if rates EEPROM not loaded)
|
||||
*/
|
||||
for (i = 0; i < N(ratesArray); i++) {
|
||||
ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
|
||||
if (ratesArray[i] > AR5416_MAX_RATE_POWER)
|
||||
ratesArray[i] = AR5416_MAX_RATE_POWER;
|
||||
ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
|
||||
}
|
||||
|
||||
#ifdef AH_EEPROM_DUMP
|
||||
ar5416PrintPowerPerRate(ah, ratesArray);
|
||||
#endif
|
||||
|
||||
/* Write the OFDM power per rate set */
|
||||
OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
|
||||
POW_SM(ratesArray[rate18mb], 24)
|
||||
| POW_SM(ratesArray[rate12mb], 16)
|
||||
| POW_SM(ratesArray[rate9mb], 8)
|
||||
| POW_SM(ratesArray[rate6mb], 0)
|
||||
);
|
||||
OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
|
||||
POW_SM(ratesArray[rate54mb], 24)
|
||||
| POW_SM(ratesArray[rate48mb], 16)
|
||||
| POW_SM(ratesArray[rate36mb], 8)
|
||||
| POW_SM(ratesArray[rate24mb], 0)
|
||||
);
|
||||
|
||||
/* Write the CCK power per rate set */
|
||||
OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
|
||||
POW_SM(ratesArray[rate2s], 24)
|
||||
| POW_SM(ratesArray[rate2l], 16)
|
||||
| POW_SM(ratesArray[rateXr], 8) /* XR target power */
|
||||
| POW_SM(ratesArray[rate1l], 0)
|
||||
);
|
||||
OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
|
||||
POW_SM(ratesArray[rate11s], 24)
|
||||
| POW_SM(ratesArray[rate11l], 16)
|
||||
| POW_SM(ratesArray[rate5_5s], 8)
|
||||
| POW_SM(ratesArray[rate5_5l], 0)
|
||||
);
|
||||
HALDEBUG(ah, HAL_DEBUG_RESET,
|
||||
"%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n",
|
||||
__func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3),
|
||||
OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4));
|
||||
|
||||
/* Write the HT20 power per rate set */
|
||||
OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
|
||||
POW_SM(ratesArray[rateHt20_3], 24)
|
||||
| POW_SM(ratesArray[rateHt20_2], 16)
|
||||
| POW_SM(ratesArray[rateHt20_1], 8)
|
||||
| POW_SM(ratesArray[rateHt20_0], 0)
|
||||
);
|
||||
OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
|
||||
POW_SM(ratesArray[rateHt20_7], 24)
|
||||
| POW_SM(ratesArray[rateHt20_6], 16)
|
||||
| POW_SM(ratesArray[rateHt20_5], 8)
|
||||
| POW_SM(ratesArray[rateHt20_4], 0)
|
||||
);
|
||||
|
||||
if (IEEE80211_IS_CHAN_HT40(chan)) {
|
||||
/* Write the HT40 power per rate set */
|
||||
/* Correct PAR difference between HT40 and HT20/LEGACY */
|
||||
OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
|
||||
POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24)
|
||||
| POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16)
|
||||
| POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8)
|
||||
| POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0)
|
||||
);
|
||||
OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
|
||||
POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24)
|
||||
| POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16)
|
||||
| POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8)
|
||||
| POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0)
|
||||
);
|
||||
/* Write the Dup/Ext 40 power per rate set */
|
||||
OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
|
||||
POW_SM(ratesArray[rateExtOfdm], 24)
|
||||
| POW_SM(ratesArray[rateExtCck], 16)
|
||||
| POW_SM(ratesArray[rateDupOfdm], 8)
|
||||
| POW_SM(ratesArray[rateDupCck], 0)
|
||||
);
|
||||
}
|
||||
|
||||
return AH_TRUE;
|
||||
#undef POW_SM
|
||||
#undef N
|
||||
}
|
||||
|
||||
HAL_BOOL
|
||||
ar9285SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
|
||||
{
|
||||
const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
|
||||
const struct ar5416eeprom_4k *eep = &ee->ee_base;
|
||||
const MODAL_EEP4K_HEADER *pModal;
|
||||
int i, regChainOffset;
|
||||
uint8_t txRxAttenLocal; /* workaround for eeprom versions <= 14.2 */
|
||||
|
||||
HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
|
||||
pModal = &eep->modalHeader;
|
||||
|
||||
/* NB: workaround for eeprom versions <= 14.2 */
|
||||
txRxAttenLocal = 23;
|
||||
|
||||
OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
|
||||
for (i = 0; i < AR5416_4K_MAX_CHAINS; i++) {
|
||||
if (AR_SREV_MERLIN(ah)) {
|
||||
if (i >= 2) break;
|
||||
}
|
||||
if (AR_SREV_OWL_20_OR_LATER(ah) &&
|
||||
(AH5416(ah)->ah_rx_chainmask == 0x5 ||
|
||||
AH5416(ah)->ah_tx_chainmask == 0x5) && i != 0) {
|
||||
/* Regs are swapped from chain 2 to 1 for 5416 2_0 with
|
||||
* only chains 0 and 2 populated
|
||||
*/
|
||||
regChainOffset = (i == 1) ? 0x2000 : 0x1000;
|
||||
} else {
|
||||
regChainOffset = i * 0x1000;
|
||||
}
|
||||
|
||||
OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]);
|
||||
OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset,
|
||||
(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) &
|
||||
~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
|
||||
SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
|
||||
SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
|
||||
|
||||
/*
|
||||
* Large signal upgrade.
|
||||
* XXX update
|
||||
*/
|
||||
|
||||
if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
|
||||
OS_REG_WRITE(ah, AR_PHY_RXGAIN + regChainOffset,
|
||||
(OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & ~AR_PHY_RXGAIN_TXRX_ATTEN) |
|
||||
SM(IS_EEP_MINOR_V3(ah) ? pModal->txRxAttenCh[i] : txRxAttenLocal,
|
||||
AR_PHY_RXGAIN_TXRX_ATTEN));
|
||||
|
||||
OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
|
||||
(OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
|
||||
SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
|
||||
}
|
||||
}
|
||||
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize);
|
||||
OS_REG_WRITE(ah, AR_PHY_RF_CTL4,
|
||||
SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
|
||||
| SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
|
||||
| SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
|
||||
| SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
|
||||
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
|
||||
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
|
||||
pModal->thresh62);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
|
||||
pModal->thresh62);
|
||||
|
||||
/* Minor Version Specific application */
|
||||
if (IS_EEP_MINOR_V2(ah)) {
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, pModal->txFrameToPaOn);
|
||||
}
|
||||
|
||||
if (IS_EEP_MINOR_V3(ah)) {
|
||||
if (IEEE80211_IS_CHAN_HT40(chan)) {
|
||||
/* Overwrite switch settling with HT40 value */
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
|
||||
}
|
||||
|
||||
if ((AR_SREV_OWL_20_OR_LATER(ah)) &&
|
||||
( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5)){
|
||||
/* Reg Offsets are swapped for logical mapping */
|
||||
OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
|
||||
SM(pModal->bswMargin[2], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
|
||||
OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
|
||||
SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
|
||||
OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
|
||||
SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
|
||||
OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
|
||||
SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
|
||||
} else {
|
||||
OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
|
||||
SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
|
||||
OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
|
||||
SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
|
||||
OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
|
||||
SM(pModal->bswMargin[2],AR_PHY_GAIN_2GHZ_BSW_MARGIN));
|
||||
OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
|
||||
SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
|
||||
}
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_MARGIN, pModal->bswMargin[0]);
|
||||
OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_ATTEN, pModal->bswAtten[0]);
|
||||
}
|
||||
return AH_TRUE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Helper functions common for AP/CB/XB
|
||||
*/
|
||||
|
||||
static HAL_BOOL
|
||||
ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData,
|
||||
const struct ieee80211_channel *chan,
|
||||
int16_t *ratesArray, uint16_t cfgCtl,
|
||||
uint16_t AntennaReduction,
|
||||
uint16_t twiceMaxRegulatoryPower,
|
||||
uint16_t powerLimit)
|
||||
{
|
||||
#define N(a) (sizeof(a)/sizeof(a[0]))
|
||||
/* Local defines to distinguish between extension and control CTL's */
|
||||
#define EXT_ADDITIVE (0x8000)
|
||||
#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
|
||||
#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
|
||||
|
||||
uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
|
||||
int i;
|
||||
int16_t twiceLargestAntenna;
|
||||
CAL_CTL_DATA_4K *rep;
|
||||
CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}};
|
||||
CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}};
|
||||
CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}};
|
||||
int16_t scaledPower, minCtlPower;
|
||||
|
||||
#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
|
||||
static const uint16_t ctlModesFor11g[] = {
|
||||
CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
|
||||
};
|
||||
const uint16_t *pCtlMode;
|
||||
uint16_t numCtlModes, ctlMode, freq;
|
||||
CHAN_CENTERS centers;
|
||||
|
||||
ar5416GetChannelCenters(ah, chan, ¢ers);
|
||||
|
||||
/* Compute TxPower reduction due to Antenna Gain */
|
||||
|
||||
twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
|
||||
twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0);
|
||||
|
||||
/* XXX setup for 5212 use (really used?) */
|
||||
ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna);
|
||||
|
||||
/*
|
||||
* scaledPower is the minimum of the user input power level and
|
||||
* the regulatory allowed power level
|
||||
*/
|
||||
scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna);
|
||||
|
||||
/* Get target powers from EEPROM - our baseline for TX Power */
|
||||
/* Setup for CTL modes */
|
||||
numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */
|
||||
pCtlMode = ctlModesFor11g;
|
||||
|
||||
ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
|
||||
AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE);
|
||||
ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
|
||||
AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE);
|
||||
ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20,
|
||||
AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);
|
||||
|
||||
if (IEEE80211_IS_CHAN_HT40(chan)) {
|
||||
numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */
|
||||
|
||||
ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40,
|
||||
AR5416_4K_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE);
|
||||
/* Get target powers for extension channels */
|
||||
ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
|
||||
AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE);
|
||||
ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
|
||||
AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE);
|
||||
}
|
||||
|
||||
/*
|
||||
* For MIMO, need to apply regulatory caps individually across dynamically
|
||||
* running modes: CCK, OFDM, HT20, HT40
|
||||
*
|
||||
* The outer loop walks through each possible applicable runtime mode.
|
||||
* The inner loop walks through each ctlIndex entry in EEPROM.
|
||||
* The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
|
||||
*
|
||||
*/
|
||||
for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
|
||||
HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
|
||||
(pCtlMode[ctlMode] == CTL_2GHT40);
|
||||
if (isHt40CtlMode) {
|
||||
freq = centers.ctl_center;
|
||||
} else if (pCtlMode[ctlMode] & EXT_ADDITIVE) {
|
||||
freq = centers.ext_center;
|
||||
} else {
|
||||
freq = centers.ctl_center;
|
||||
}
|
||||
|
||||
/* walk through each CTL index stored in EEPROM */
|
||||
for (i = 0; (i < AR5416_4K_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
|
||||
uint16_t twiceMinEdgePower;
|
||||
|
||||
/* compare test group from regulatory channel list with test mode from pCtlMode list */
|
||||
if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) ||
|
||||
(((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) ==
|
||||
((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
|
||||
rep = &(pEepData->ctlData[i]);
|
||||
twiceMinEdgePower = ar9285GetMaxEdgePower(freq,
|
||||
rep->ctlEdges[
|
||||
owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1]);
|
||||
if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
|
||||
/* Find the minimum of all CTL edge powers that apply to this channel */
|
||||
twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower);
|
||||
} else {
|
||||
/* specific */
|
||||
twiceMaxEdgePower = twiceMinEdgePower;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower);
|
||||
/* Apply ctl mode to correct target power set */
|
||||
switch(pCtlMode[ctlMode]) {
|
||||
case CTL_11B:
|
||||
for (i = 0; i < N(targetPowerCck.tPow2x); i++) {
|
||||
targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower);
|
||||
}
|
||||
break;
|
||||
case CTL_11A:
|
||||
case CTL_11G:
|
||||
for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) {
|
||||
targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower);
|
||||
}
|
||||
break;
|
||||
case CTL_5GHT20:
|
||||
case CTL_2GHT20:
|
||||
for (i = 0; i < N(targetPowerHt20.tPow2x); i++) {
|
||||
targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower);
|
||||
}
|
||||
break;
|
||||
case CTL_11B_EXT:
|
||||
targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower);
|
||||
break;
|
||||
case CTL_11G_EXT:
|
||||
targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower);
|
||||
break;
|
||||
case CTL_5GHT40:
|
||||
case CTL_2GHT40:
|
||||
for (i = 0; i < N(targetPowerHt40.tPow2x); i++) {
|
||||
targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
return AH_FALSE;
|
||||
break;
|
||||
}
|
||||
} /* end ctl mode checking */
|
||||
|
||||
/* Set rates Array from collected data */
|
||||
ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0];
|
||||
ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
|
||||
ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
|
||||
ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
|
||||
ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
|
||||
|
||||
for (i = 0; i < N(targetPowerHt20.tPow2x); i++) {
|
||||
ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
|
||||
}
|
||||
|
||||
ratesArray[rate1l] = targetPowerCck.tPow2x[0];
|
||||
ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
|
||||
ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
|
||||
ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
|
||||
if (IEEE80211_IS_CHAN_HT40(chan)) {
|
||||
for (i = 0; i < N(targetPowerHt40.tPow2x); i++) {
|
||||
ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
|
||||
}
|
||||
ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
|
||||
ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
|
||||
ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
|
||||
if (IEEE80211_IS_CHAN_2GHZ(chan)) {
|
||||
ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
|
||||
}
|
||||
}
|
||||
return AH_TRUE;
|
||||
#undef EXT_ADDITIVE
|
||||
#undef CTL_11G_EXT
|
||||
#undef CTL_11B_EXT
|
||||
#undef SUB_NUM_CTL_MODES_AT_2G_40
|
||||
#undef N
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
* fbin2freq
|
||||
*
|
||||
* Get channel value from binary representation held in eeprom
|
||||
* RETURNS: the frequency in MHz
|
||||
*/
|
||||
static uint16_t
|
||||
fbin2freq(uint8_t fbin)
|
||||
{
|
||||
/*
|
||||
* Reserved value 0xFF provides an empty definition both as
|
||||
* an fbin and as a frequency - do not convert
|
||||
*/
|
||||
if (fbin == AR5416_BCHAN_UNUSED) {
|
||||
return fbin;
|
||||
}
|
||||
|
||||
return (uint16_t)(2300 + fbin);
|
||||
}
|
||||
|
||||
/*
|
||||
* XXX almost the same as ar5416GetMaxEdgePower.
|
||||
*/
|
||||
static uint16_t
|
||||
ar9285GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower)
|
||||
{
|
||||
uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
|
||||
int i;
|
||||
|
||||
/* Get the edge power */
|
||||
for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) {
|
||||
/*
|
||||
* If there's an exact channel match or an inband flag set
|
||||
* on the lower channel use the given rdEdgePower
|
||||
*/
|
||||
if (freq == fbin2freq(pRdEdgesPower[i].bChannel)) {
|
||||
twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER);
|
||||
break;
|
||||
} else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel))) {
|
||||
if (fbin2freq(pRdEdgesPower[i - 1].bChannel) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) {
|
||||
twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER);
|
||||
}
|
||||
/* Leave loop - no more affecting edges possible in this monotonic increasing list */
|
||||
break;
|
||||
}
|
||||
}
|
||||
HALASSERT(twiceMaxEdgePower > 0);
|
||||
return twiceMaxEdgePower;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static HAL_BOOL
|
||||
ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData,
|
||||
const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
|
||||
{
|
||||
CAL_DATA_PER_FREQ_4K *pRawDataset;
|
||||
uint8_t *pCalBChans = AH_NULL;
|
||||
uint16_t pdGainOverlap_t2;
|
||||
static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES];
|
||||
uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK];
|
||||
uint16_t numPiers, i, j;
|
||||
int16_t tMinCalPower;
|
||||
uint16_t numXpdGain, xpdMask;
|
||||
uint16_t xpdGainValues[AR5416_4K_NUM_PD_GAINS];
|
||||
uint32_t reg32, regOffset, regChainOffset;
|
||||
|
||||
OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues));
|
||||
|
||||
xpdMask = pEepData->modalHeader.xpdGain;
|
||||
|
||||
if (IS_EEP_MINOR_V2(ah)) {
|
||||
pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
|
||||
} else {
|
||||
pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
|
||||
}
|
||||
|
||||
pCalBChans = pEepData->calFreqPier2G;
|
||||
numPiers = AR5416_4K_NUM_2G_CAL_PIERS;
|
||||
numXpdGain = 0;
|
||||
/* Calculate the value of xpdgains from the xpdGain Mask */
|
||||
for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
|
||||
if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
|
||||
if (numXpdGain >= AR5416_4K_NUM_PD_GAINS) {
|
||||
HALASSERT(0);
|
||||
break;
|
||||
}
|
||||
xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i);
|
||||
numXpdGain++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Write the detector gain biases and their number */
|
||||
OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) &
|
||||
~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 | AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) |
|
||||
SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) |
|
||||
SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(xpdGainValues[2], AR_PHY_TPCRG1_PD_GAIN_3));
|
||||
|
||||
for (i = 0; i < AR5416_MAX_CHAINS; i++) {
|
||||
|
||||
if (AR_SREV_OWL_20_OR_LATER(ah) &&
|
||||
( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) {
|
||||
/* Regs are swapped from chain 2 to 1 for 5416 2_0 with
|
||||
* only chains 0 and 2 populated
|
||||
*/
|
||||
regChainOffset = (i == 1) ? 0x2000 : 0x1000;
|
||||
} else {
|
||||
regChainOffset = i * 0x1000;
|
||||
}
|
||||
|
||||
if (pEepData->baseEepHeader.txMask & (1 << i)) {
|
||||
pRawDataset = pEepData->calPierData2G[i];
|
||||
|
||||
ar9285GetGainBoundariesAndPdadcs(ah, chan, pRawDataset,
|
||||
pCalBChans, numPiers,
|
||||
pdGainOverlap_t2,
|
||||
&tMinCalPower, gainBoundaries,
|
||||
pdadcValues, numXpdGain);
|
||||
|
||||
if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
|
||||
/*
|
||||
* Note the pdadc table may not start at 0 dBm power, could be
|
||||
* negative or greater than 0. Need to offset the power
|
||||
* values by the amount of minPower for griffin
|
||||
*/
|
||||
|
||||
OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
|
||||
SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
|
||||
SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
|
||||
SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
|
||||
SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
|
||||
SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
|
||||
}
|
||||
|
||||
/* Write the power values into the baseband power table */
|
||||
regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
|
||||
|
||||
for (j = 0; j < 32; j++) {
|
||||
reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) |
|
||||
((pdadcValues[4*j + 1] & 0xFF) << 8) |
|
||||
((pdadcValues[4*j + 2] & 0xFF) << 16) |
|
||||
((pdadcValues[4*j + 3] & 0xFF) << 24) ;
|
||||
OS_REG_WRITE(ah, regOffset, reg32);
|
||||
|
||||
#ifdef PDADC_DUMP
|
||||
ath_hal_printf(ah, "PDADC: Chain %d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d |\n",
|
||||
i,
|
||||
4*j, pdadcValues[4*j],
|
||||
4*j+1, pdadcValues[4*j + 1],
|
||||
4*j+2, pdadcValues[4*j + 2],
|
||||
4*j+3, pdadcValues[4*j + 3]);
|
||||
#endif
|
||||
regOffset += 4;
|
||||
}
|
||||
}
|
||||
}
|
||||
*pTxPowerIndexOffset = 0;
|
||||
|
||||
return AH_TRUE;
|
||||
}
|
||||
|
||||
static void
|
||||
ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah,
|
||||
const struct ieee80211_channel *chan,
|
||||
CAL_DATA_PER_FREQ_4K *pRawDataSet,
|
||||
uint8_t * bChans, uint16_t availPiers,
|
||||
uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries,
|
||||
uint8_t * pPDADCValues, uint16_t numXpdGains)
|
||||
{
|
||||
|
||||
int i, j, k;
|
||||
int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */
|
||||
uint16_t idxL, idxR, numPiers; /* Pier indexes */
|
||||
|
||||
/* filled out Vpd table for all pdGains (chanL) */
|
||||
static uint8_t vpdTableL[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
|
||||
|
||||
/* filled out Vpd table for all pdGains (chanR) */
|
||||
static uint8_t vpdTableR[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
|
||||
|
||||
/* filled out Vpd table for all pdGains (interpolated) */
|
||||
static uint8_t vpdTableI[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
|
||||
|
||||
uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR;
|
||||
uint8_t minPwrT4[AR5416_4K_NUM_PD_GAINS];
|
||||
uint8_t maxPwrT4[AR5416_4K_NUM_PD_GAINS];
|
||||
int16_t vpdStep;
|
||||
int16_t tmpVal;
|
||||
uint16_t sizeCurrVpdTable, maxIndex, tgtIndex;
|
||||
HAL_BOOL match;
|
||||
int16_t minDelta = 0;
|
||||
CHAN_CENTERS centers;
|
||||
|
||||
ar5416GetChannelCenters(ah, chan, ¢ers);
|
||||
|
||||
/* Trim numPiers for the number of populated channel Piers */
|
||||
for (numPiers = 0; numPiers < availPiers; numPiers++) {
|
||||
if (bChans[numPiers] == AR5416_BCHAN_UNUSED) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Find pier indexes around the current channel */
|
||||
match = getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),
|
||||
bChans, numPiers, &idxL, &idxR);
|
||||
|
||||
if (match) {
|
||||
/* Directly fill both vpd tables from the matching index */
|
||||
for (i = 0; i < numXpdGains; i++) {
|
||||
minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
|
||||
maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
|
||||
ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i],
|
||||
pRawDataSet[idxL].pwrPdg[i],
|
||||
pRawDataSet[idxL].vpdPdg[i],
|
||||
AR5416_PD_GAIN_ICEPTS, vpdTableI[i]);
|
||||
}
|
||||
} else {
|
||||
for (i = 0; i < numXpdGains; i++) {
|
||||
pVpdL = pRawDataSet[idxL].vpdPdg[i];
|
||||
pPwrL = pRawDataSet[idxL].pwrPdg[i];
|
||||
pVpdR = pRawDataSet[idxR].vpdPdg[i];
|
||||
pPwrR = pRawDataSet[idxR].pwrPdg[i];
|
||||
|
||||
/* Start Vpd interpolation from the max of the minimum powers */
|
||||
minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]);
|
||||
|
||||
/* End Vpd interpolation from the min of the max powers */
|
||||
maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
|
||||
HALASSERT(maxPwrT4[i] > minPwrT4[i]);
|
||||
|
||||
/* Fill pier Vpds */
|
||||
ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL,
|
||||
AR5416_PD_GAIN_ICEPTS, vpdTableL[i]);
|
||||
ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR,
|
||||
AR5416_PD_GAIN_ICEPTS, vpdTableR[i]);
|
||||
|
||||
/* Interpolate the final vpd */
|
||||
for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
|
||||
vpdTableI[i][j] = (uint8_t)(interpolate((uint16_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),
|
||||
bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j]));
|
||||
}
|
||||
}
|
||||
}
|
||||
*pMinCalPower = (int16_t)(minPwrT4[0] / 2);
|
||||
|
||||
k = 0; /* index for the final table */
|
||||
for (i = 0; i < numXpdGains; i++) {
|
||||
if (i == (numXpdGains - 1)) {
|
||||
pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2);
|
||||
} else {
|
||||
pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4);
|
||||
}
|
||||
|
||||
pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
|
||||
|
||||
/* NB: only applies to owl 1.0 */
|
||||
if ((i == 0) && !AR_SREV_OWL_20_OR_LATER(ah) ) {
|
||||
/*
|
||||
* fix the gain delta, but get a delta that can be applied to min to
|
||||
* keep the upper power values accurate, don't think max needs to
|
||||
* be adjusted because should not be at that area of the table?
|
||||
*/
|
||||
minDelta = pPdGainBoundaries[0] - 23;
|
||||
pPdGainBoundaries[0] = 23;
|
||||
}
|
||||
else {
|
||||
minDelta = 0;
|
||||
}
|
||||
|
||||
/* Find starting index for this pdGain */
|
||||
if (i == 0) {
|
||||
ss = 0; /* for the first pdGain, start from index 0 */
|
||||
} else {
|
||||
/* need overlap entries extrapolated below. */
|
||||
ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta);
|
||||
}
|
||||
vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
|
||||
vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
|
||||
/*
|
||||
*-ve ss indicates need to extrapolate data below for this pdGain
|
||||
*/
|
||||
while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
|
||||
tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
|
||||
pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal);
|
||||
ss++;
|
||||
}
|
||||
|
||||
sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1);
|
||||
tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2));
|
||||
maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
|
||||
|
||||
while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
|
||||
pPDADCValues[k++] = vpdTableI[i][ss++];
|
||||
}
|
||||
|
||||
vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]);
|
||||
vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
|
||||
/*
|
||||
* for last gain, pdGainBoundary == Pmax_t2, so will
|
||||
* have to extrapolate
|
||||
*/
|
||||
if (tgtIndex > maxIndex) { /* need to extrapolate above */
|
||||
while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
|
||||
tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
|
||||
(ss - maxIndex +1) * vpdStep));
|
||||
pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal);
|
||||
ss++;
|
||||
}
|
||||
} /* extrapolated above */
|
||||
} /* for all pdGainUsed */
|
||||
|
||||
/* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */
|
||||
while (i < AR5416_PD_GAINS_IN_MASK) {
|
||||
pPdGainBoundaries[i] = pPdGainBoundaries[i-1];
|
||||
i++;
|
||||
}
|
||||
|
||||
while (k < AR5416_NUM_PDADC_VALUES) {
|
||||
pPDADCValues[k] = pPDADCValues[k-1];
|
||||
k++;
|
||||
}
|
||||
return;
|
||||
}
|
||||
/*
|
||||
* XXX same as ar5416FillVpdTable
|
||||
*/
|
||||
static HAL_BOOL
|
||||
ar9285FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, uint8_t *pPwrList,
|
||||
uint8_t *pVpdList, uint16_t numIntercepts, uint8_t *pRetVpdList)
|
||||
{
|
||||
uint16_t i, k;
|
||||
uint8_t currPwr = pwrMin;
|
||||
uint16_t idxL, idxR;
|
||||
|
||||
HALASSERT(pwrMax > pwrMin);
|
||||
for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
|
||||
getLowerUpperIndex(currPwr, pPwrList, numIntercepts,
|
||||
&(idxL), &(idxR));
|
||||
if (idxR < 1)
|
||||
idxR = 1; /* extrapolate below */
|
||||
if (idxL == numIntercepts - 1)
|
||||
idxL = (uint16_t)(numIntercepts - 2); /* extrapolate above */
|
||||
if (pPwrList[idxL] == pPwrList[idxR])
|
||||
k = pVpdList[idxL];
|
||||
else
|
||||
k = (uint16_t)( ((currPwr - pPwrList[idxL]) * pVpdList[idxR] + (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
|
||||
(pPwrList[idxR] - pPwrList[idxL]) );
|
||||
HALASSERT(k < 256);
|
||||
pRetVpdList[i] = (uint8_t)k;
|
||||
currPwr += 2; /* half dB steps */
|
||||
}
|
||||
|
||||
return AH_TRUE;
|
||||
}
|
||||
static int16_t
|
||||
interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
|
||||
int16_t targetLeft, int16_t targetRight)
|
||||
{
|
||||
int16_t rv;
|
||||
|
||||
if (srcRight == srcLeft) {
|
||||
rv = targetLeft;
|
||||
} else {
|
||||
rv = (int16_t)( ((target - srcLeft) * targetRight +
|
||||
(srcRight - target) * targetLeft) / (srcRight - srcLeft) );
|
||||
}
|
||||
return rv;
|
||||
}
|
||||
|
||||
HAL_BOOL
|
||||
getLowerUpperIndex(uint8_t target, uint8_t *pList, uint16_t listSize,
|
||||
uint16_t *indexL, uint16_t *indexR)
|
||||
{
|
||||
uint16_t i;
|
||||
|
||||
/*
|
||||
* Check first and last elements for beyond ordered array cases.
|
||||
*/
|
||||
if (target <= pList[0]) {
|
||||
*indexL = *indexR = 0;
|
||||
return AH_TRUE;
|
||||
}
|
||||
if (target >= pList[listSize-1]) {
|
||||
*indexL = *indexR = (uint16_t)(listSize - 1);
|
||||
return AH_TRUE;
|
||||
}
|
||||
|
||||
/* look for value being near or between 2 values in list */
|
||||
for (i = 0; i < listSize - 1; i++) {
|
||||
/*
|
||||
* If value is close to the current value of the list
|
||||
* then target is not between values, it is one of the values
|
||||
*/
|
||||
if (pList[i] == target) {
|
||||
*indexL = *indexR = i;
|
||||
return AH_TRUE;
|
||||
}
|
||||
/*
|
||||
* Look for value being between current value and next value
|
||||
* if so return these 2 values
|
||||
*/
|
||||
if (target < pList[i + 1]) {
|
||||
*indexL = i;
|
||||
*indexR = (uint16_t)(i + 1);
|
||||
return AH_FALSE;
|
||||
}
|
||||
}
|
||||
HALASSERT(0);
|
||||
*indexL = *indexR = 0;
|
||||
return AH_FALSE;
|
||||
}
|
||||
+746
@@ -0,0 +1,746 @@
|
||||
/*
|
||||
* Copyright (c) 2008-2009 Atheros Communications Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/* AR9285 v1_2 PCI Register Writes. Created: 04/13/09 */
|
||||
static const u_int32_t ar9285Modes_v2[][6] = {
|
||||
/* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
|
||||
{ 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
|
||||
{ 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
|
||||
{ 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
|
||||
{ 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
|
||||
{ 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
|
||||
{ 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
|
||||
{ 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
|
||||
{ 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
|
||||
{ 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
|
||||
{ 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
|
||||
{ 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
|
||||
{ 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
|
||||
{ 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
|
||||
{ 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
|
||||
{ 0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620, 0x037216a0 },
|
||||
{ 0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
|
||||
{ 0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
|
||||
{ 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
|
||||
{ 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
|
||||
{ 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
|
||||
{ 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
|
||||
{ 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
|
||||
{ 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
|
||||
{ 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
|
||||
{ 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
|
||||
{ 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
|
||||
{ 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
|
||||
{ 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010 },
|
||||
{ 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c },
|
||||
{ 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
|
||||
{ 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
|
||||
{ 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
|
||||
{ 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
|
||||
{ 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
|
||||
{ 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
|
||||
{ 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
|
||||
{ 0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
|
||||
{ 0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
|
||||
{ 0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
|
||||
{ 0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
|
||||
{ 0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
|
||||
{ 0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
|
||||
{ 0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
|
||||
{ 0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
|
||||
{ 0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
|
||||
{ 0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
|
||||
{ 0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
|
||||
{ 0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
|
||||
{ 0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
|
||||
{ 0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
|
||||
{ 0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
|
||||
{ 0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
|
||||
{ 0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
|
||||
{ 0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
|
||||
{ 0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
|
||||
{ 0x00009a50, 0x00000000, 0x00000000, 0x00058220, 0x00058220, 0x00000000 },
|
||||
{ 0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
|
||||
{ 0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
|
||||
{ 0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
|
||||
{ 0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
|
||||
{ 0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
|
||||
{ 0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
|
||||
{ 0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
|
||||
{ 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
|
||||
{ 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
|
||||
{ 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
|
||||
{ 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
|
||||
{ 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
|
||||
{ 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
|
||||
{ 0x00009a88, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
|
||||
{ 0x00009a8c, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
|
||||
{ 0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
|
||||
{ 0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
|
||||
{ 0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
|
||||
{ 0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
|
||||
{ 0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
|
||||
{ 0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
|
||||
{ 0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
|
||||
{ 0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
|
||||
{ 0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
|
||||
{ 0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
|
||||
{ 0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
|
||||
{ 0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
|
||||
{ 0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
|
||||
{ 0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
|
||||
{ 0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
|
||||
{ 0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
|
||||
{ 0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
|
||||
{ 0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
|
||||
{ 0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
|
||||
{ 0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
|
||||
{ 0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
|
||||
{ 0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
|
||||
{ 0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
|
||||
{ 0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
|
||||
{ 0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
|
||||
{ 0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
|
||||
{ 0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
|
||||
{ 0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
|
||||
{ 0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
|
||||
{ 0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
|
||||
{ 0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
|
||||
{ 0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
|
||||
{ 0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
|
||||
{ 0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
|
||||
{ 0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
|
||||
{ 0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
|
||||
{ 0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
|
||||
{ 0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
|
||||
{ 0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
|
||||
{ 0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
|
||||
{ 0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
|
||||
{ 0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
|
||||
{ 0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
|
||||
{ 0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
|
||||
{ 0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
|
||||
{ 0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
|
||||
{ 0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
|
||||
{ 0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
|
||||
{ 0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
|
||||
{ 0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
|
||||
{ 0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
|
||||
{ 0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
|
||||
{ 0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
|
||||
{ 0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
|
||||
{ 0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
|
||||
{ 0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
|
||||
{ 0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
|
||||
{ 0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
|
||||
{ 0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
|
||||
{ 0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
|
||||
{ 0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
|
||||
{ 0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
|
||||
{ 0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
|
||||
{ 0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
|
||||
{ 0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
|
||||
{ 0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
|
||||
{ 0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
|
||||
{ 0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
|
||||
{ 0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
|
||||
{ 0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
|
||||
{ 0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
|
||||
{ 0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
|
||||
{ 0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
|
||||
{ 0x0000aa50, 0x00000000, 0x00000000, 0x00058220, 0x00058220, 0x00000000 },
|
||||
{ 0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
|
||||
{ 0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
|
||||
{ 0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
|
||||
{ 0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
|
||||
{ 0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
|
||||
{ 0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
|
||||
{ 0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
|
||||
{ 0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
|
||||
{ 0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
|
||||
{ 0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
|
||||
{ 0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
|
||||
{ 0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
|
||||
{ 0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
|
||||
{ 0x0000aa88, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
|
||||
{ 0x0000aa8c, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
|
||||
{ 0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
|
||||
{ 0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
|
||||
{ 0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
|
||||
{ 0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
|
||||
{ 0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
|
||||
{ 0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
|
||||
{ 0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
|
||||
{ 0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
|
||||
{ 0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
|
||||
{ 0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
|
||||
{ 0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
|
||||
{ 0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
|
||||
{ 0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
|
||||
{ 0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
|
||||
{ 0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
|
||||
{ 0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
|
||||
{ 0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
|
||||
{ 0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
|
||||
{ 0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
|
||||
{ 0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
|
||||
{ 0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
|
||||
{ 0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
|
||||
{ 0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
|
||||
{ 0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
|
||||
{ 0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
|
||||
{ 0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
|
||||
{ 0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
|
||||
{ 0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
|
||||
{ 0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
|
||||
{ 0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
|
||||
{ 0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
|
||||
{ 0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
|
||||
{ 0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
|
||||
{ 0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
|
||||
{ 0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
|
||||
{ 0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
|
||||
{ 0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
|
||||
{ 0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
|
||||
{ 0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
|
||||
{ 0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
|
||||
{ 0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
|
||||
{ 0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
|
||||
{ 0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
|
||||
{ 0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
|
||||
{ 0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
|
||||
{ 0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
|
||||
{ 0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
|
||||
{ 0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
|
||||
{ 0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
|
||||
{ 0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
|
||||
{ 0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
|
||||
{ 0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
|
||||
{ 0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
|
||||
{ 0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
|
||||
{ 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
|
||||
{ 0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
|
||||
{ 0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
|
||||
{ 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
|
||||
{ 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
|
||||
{ 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
|
||||
{ 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285Common_v2[][2] = {
|
||||
{ 0x0000000c, 0x00000000 },
|
||||
{ 0x00000030, 0x00020045 },
|
||||
{ 0x00000034, 0x00000005 },
|
||||
{ 0x00000040, 0x00000000 },
|
||||
{ 0x00000044, 0x00000008 },
|
||||
{ 0x00000048, 0x00000008 },
|
||||
{ 0x0000004c, 0x00000010 },
|
||||
{ 0x00000050, 0x00000000 },
|
||||
{ 0x00000054, 0x0000001f },
|
||||
{ 0x00000800, 0x00000000 },
|
||||
{ 0x00000804, 0x00000000 },
|
||||
{ 0x00000808, 0x00000000 },
|
||||
{ 0x0000080c, 0x00000000 },
|
||||
{ 0x00000810, 0x00000000 },
|
||||
{ 0x00000814, 0x00000000 },
|
||||
{ 0x00000818, 0x00000000 },
|
||||
{ 0x0000081c, 0x00000000 },
|
||||
{ 0x00000820, 0x00000000 },
|
||||
{ 0x00000824, 0x00000000 },
|
||||
{ 0x00001040, 0x002ffc0f },
|
||||
{ 0x00001044, 0x002ffc0f },
|
||||
{ 0x00001048, 0x002ffc0f },
|
||||
{ 0x0000104c, 0x002ffc0f },
|
||||
{ 0x00001050, 0x002ffc0f },
|
||||
{ 0x00001054, 0x002ffc0f },
|
||||
{ 0x00001058, 0x002ffc0f },
|
||||
{ 0x0000105c, 0x002ffc0f },
|
||||
{ 0x00001060, 0x002ffc0f },
|
||||
{ 0x00001064, 0x002ffc0f },
|
||||
{ 0x00001230, 0x00000000 },
|
||||
{ 0x00001270, 0x00000000 },
|
||||
{ 0x00001038, 0x00000000 },
|
||||
{ 0x00001078, 0x00000000 },
|
||||
{ 0x000010b8, 0x00000000 },
|
||||
{ 0x000010f8, 0x00000000 },
|
||||
{ 0x00001138, 0x00000000 },
|
||||
{ 0x00001178, 0x00000000 },
|
||||
{ 0x000011b8, 0x00000000 },
|
||||
{ 0x000011f8, 0x00000000 },
|
||||
{ 0x00001238, 0x00000000 },
|
||||
{ 0x00001278, 0x00000000 },
|
||||
{ 0x000012b8, 0x00000000 },
|
||||
{ 0x000012f8, 0x00000000 },
|
||||
{ 0x00001338, 0x00000000 },
|
||||
{ 0x00001378, 0x00000000 },
|
||||
{ 0x000013b8, 0x00000000 },
|
||||
{ 0x000013f8, 0x00000000 },
|
||||
{ 0x00001438, 0x00000000 },
|
||||
{ 0x00001478, 0x00000000 },
|
||||
{ 0x000014b8, 0x00000000 },
|
||||
{ 0x000014f8, 0x00000000 },
|
||||
{ 0x00001538, 0x00000000 },
|
||||
{ 0x00001578, 0x00000000 },
|
||||
{ 0x000015b8, 0x00000000 },
|
||||
{ 0x000015f8, 0x00000000 },
|
||||
{ 0x00001638, 0x00000000 },
|
||||
{ 0x00001678, 0x00000000 },
|
||||
{ 0x000016b8, 0x00000000 },
|
||||
{ 0x000016f8, 0x00000000 },
|
||||
{ 0x00001738, 0x00000000 },
|
||||
{ 0x00001778, 0x00000000 },
|
||||
{ 0x000017b8, 0x00000000 },
|
||||
{ 0x000017f8, 0x00000000 },
|
||||
{ 0x0000103c, 0x00000000 },
|
||||
{ 0x0000107c, 0x00000000 },
|
||||
{ 0x000010bc, 0x00000000 },
|
||||
{ 0x000010fc, 0x00000000 },
|
||||
{ 0x0000113c, 0x00000000 },
|
||||
{ 0x0000117c, 0x00000000 },
|
||||
{ 0x000011bc, 0x00000000 },
|
||||
{ 0x000011fc, 0x00000000 },
|
||||
{ 0x0000123c, 0x00000000 },
|
||||
{ 0x0000127c, 0x00000000 },
|
||||
{ 0x000012bc, 0x00000000 },
|
||||
{ 0x000012fc, 0x00000000 },
|
||||
{ 0x0000133c, 0x00000000 },
|
||||
{ 0x0000137c, 0x00000000 },
|
||||
{ 0x000013bc, 0x00000000 },
|
||||
{ 0x000013fc, 0x00000000 },
|
||||
{ 0x0000143c, 0x00000000 },
|
||||
{ 0x0000147c, 0x00000000 },
|
||||
{ 0x00004030, 0x00000002 },
|
||||
{ 0x0000403c, 0x00000002 },
|
||||
{ 0x00004024, 0x0000001f },
|
||||
{ 0x00004060, 0x00000000 },
|
||||
{ 0x00004064, 0x00000000 },
|
||||
{ 0x00007010, 0x00000031 },
|
||||
{ 0x00007034, 0x00000002 },
|
||||
{ 0x00007038, 0x000004c2 },
|
||||
{ 0x00008004, 0x00000000 },
|
||||
{ 0x00008008, 0x00000000 },
|
||||
{ 0x0000800c, 0x00000000 },
|
||||
{ 0x00008018, 0x00000700 },
|
||||
{ 0x00008020, 0x00000000 },
|
||||
{ 0x00008038, 0x00000000 },
|
||||
{ 0x0000803c, 0x00000000 },
|
||||
{ 0x00008048, 0x00000000 },
|
||||
{ 0x00008054, 0x00000000 },
|
||||
{ 0x00008058, 0x00000000 },
|
||||
{ 0x0000805c, 0x000fc78f },
|
||||
{ 0x00008060, 0x0000000f },
|
||||
{ 0x00008064, 0x00000000 },
|
||||
{ 0x00008070, 0x00000000 },
|
||||
{ 0x000080c0, 0x2a80001a },
|
||||
{ 0x000080c4, 0x05dc01e0 },
|
||||
{ 0x000080c8, 0x1f402710 },
|
||||
{ 0x000080cc, 0x01f40000 },
|
||||
{ 0x000080d0, 0x00001e00 },
|
||||
{ 0x000080d4, 0x00000000 },
|
||||
{ 0x000080d8, 0x00400000 },
|
||||
{ 0x000080e0, 0xffffffff },
|
||||
{ 0x000080e4, 0x0000ffff },
|
||||
{ 0x000080e8, 0x003f3f3f },
|
||||
{ 0x000080ec, 0x00000000 },
|
||||
{ 0x000080f0, 0x00000000 },
|
||||
{ 0x000080f4, 0x00000000 },
|
||||
{ 0x000080f8, 0x00000000 },
|
||||
{ 0x000080fc, 0x00020000 },
|
||||
{ 0x00008100, 0x00020000 },
|
||||
{ 0x00008104, 0x00000001 },
|
||||
{ 0x00008108, 0x00000052 },
|
||||
{ 0x0000810c, 0x00000000 },
|
||||
{ 0x00008110, 0x00000168 },
|
||||
{ 0x00008118, 0x000100aa },
|
||||
{ 0x0000811c, 0x00003210 },
|
||||
{ 0x00008120, 0x08f04810 },
|
||||
{ 0x00008124, 0x00000000 },
|
||||
{ 0x00008128, 0x00000000 },
|
||||
{ 0x0000812c, 0x00000000 },
|
||||
{ 0x00008130, 0x00000000 },
|
||||
{ 0x00008134, 0x00000000 },
|
||||
{ 0x00008138, 0x00000000 },
|
||||
{ 0x0000813c, 0x00000000 },
|
||||
{ 0x00008144, 0xffffffff },
|
||||
{ 0x00008168, 0x00000000 },
|
||||
{ 0x0000816c, 0x00000000 },
|
||||
{ 0x00008170, 0x32143320 },
|
||||
{ 0x00008174, 0xfaa4fa50 },
|
||||
{ 0x00008178, 0x00000100 },
|
||||
{ 0x0000817c, 0x00000000 },
|
||||
{ 0x000081c0, 0x00000000 },
|
||||
{ 0x000081d0, 0x0000320a },
|
||||
{ 0x000081ec, 0x00000000 },
|
||||
{ 0x000081f0, 0x00000000 },
|
||||
{ 0x000081f4, 0x00000000 },
|
||||
{ 0x000081f8, 0x00000000 },
|
||||
{ 0x000081fc, 0x00000000 },
|
||||
{ 0x00008200, 0x00000000 },
|
||||
{ 0x00008204, 0x00000000 },
|
||||
{ 0x00008208, 0x00000000 },
|
||||
{ 0x0000820c, 0x00000000 },
|
||||
{ 0x00008210, 0x00000000 },
|
||||
{ 0x00008214, 0x00000000 },
|
||||
{ 0x00008218, 0x00000000 },
|
||||
{ 0x0000821c, 0x00000000 },
|
||||
{ 0x00008220, 0x00000000 },
|
||||
{ 0x00008224, 0x00000000 },
|
||||
{ 0x00008228, 0x00000000 },
|
||||
{ 0x0000822c, 0x00000000 },
|
||||
{ 0x00008230, 0x00000000 },
|
||||
{ 0x00008234, 0x00000000 },
|
||||
{ 0x00008238, 0x00000000 },
|
||||
{ 0x0000823c, 0x00000000 },
|
||||
{ 0x00008240, 0x00100000 },
|
||||
{ 0x00008244, 0x0010f400 },
|
||||
{ 0x00008248, 0x00000100 },
|
||||
{ 0x0000824c, 0x0001e800 },
|
||||
{ 0x00008250, 0x00000000 },
|
||||
{ 0x00008254, 0x00000000 },
|
||||
{ 0x00008258, 0x00000000 },
|
||||
{ 0x0000825c, 0x400000ff },
|
||||
{ 0x00008260, 0x00080922 },
|
||||
{ 0x00008264, 0x88a00010 },
|
||||
{ 0x00008270, 0x00000000 },
|
||||
{ 0x00008274, 0x40000000 },
|
||||
{ 0x00008278, 0x003e4180 },
|
||||
{ 0x0000827c, 0x00000000 },
|
||||
{ 0x00008284, 0x0000002c },
|
||||
{ 0x00008288, 0x0000002c },
|
||||
{ 0x0000828c, 0x00000000 },
|
||||
{ 0x00008294, 0x00000000 },
|
||||
{ 0x00008298, 0x00000000 },
|
||||
{ 0x0000829c, 0x00000000 },
|
||||
{ 0x00008300, 0x00000040 },
|
||||
{ 0x00008314, 0x00000000 },
|
||||
{ 0x00008328, 0x00000000 },
|
||||
{ 0x0000832c, 0x00000001 },
|
||||
{ 0x00008330, 0x00000302 },
|
||||
{ 0x00008334, 0x00000e00 },
|
||||
{ 0x00008338, 0x00ff0000 },
|
||||
{ 0x0000833c, 0x00000000 },
|
||||
{ 0x00008340, 0x00010380 },
|
||||
{ 0x00008344, 0x00481043 },
|
||||
{ 0x00009808, 0x00000000 },
|
||||
{ 0x0000980c, 0xafe68e30 },
|
||||
{ 0x00009810, 0xfd14e000 },
|
||||
{ 0x00009814, 0x9c0a9f6b },
|
||||
{ 0x0000981c, 0x00000000 },
|
||||
{ 0x0000982c, 0x0000a000 },
|
||||
{ 0x00009830, 0x00000000 },
|
||||
{ 0x0000983c, 0x00200400 },
|
||||
{ 0x0000984c, 0x0040233c },
|
||||
{ 0x00009854, 0x00000044 },
|
||||
{ 0x00009900, 0x00000000 },
|
||||
{ 0x00009904, 0x00000000 },
|
||||
{ 0x00009908, 0x00000000 },
|
||||
{ 0x0000990c, 0x00000000 },
|
||||
{ 0x00009910, 0x01002310 },
|
||||
{ 0x0000991c, 0x10000fff },
|
||||
{ 0x00009920, 0x04900000 },
|
||||
{ 0x00009928, 0x00000001 },
|
||||
{ 0x0000992c, 0x00000004 },
|
||||
{ 0x00009934, 0x1e1f2022 },
|
||||
{ 0x00009938, 0x0a0b0c0d },
|
||||
{ 0x0000993c, 0x00000000 },
|
||||
{ 0x00009940, 0x14750604 },
|
||||
{ 0x00009948, 0x9280c00a },
|
||||
{ 0x0000994c, 0x00020028 },
|
||||
{ 0x00009954, 0x5f3ca3de },
|
||||
{ 0x00009958, 0x2108ecff },
|
||||
{ 0x00009968, 0x000003ce },
|
||||
{ 0x00009970, 0x192bb514 },
|
||||
{ 0x00009974, 0x00000000 },
|
||||
{ 0x00009978, 0x00000001 },
|
||||
{ 0x0000997c, 0x00000000 },
|
||||
{ 0x00009980, 0x00000000 },
|
||||
{ 0x00009984, 0x00000000 },
|
||||
{ 0x00009988, 0x00000000 },
|
||||
{ 0x0000998c, 0x00000000 },
|
||||
{ 0x00009990, 0x00000000 },
|
||||
{ 0x00009994, 0x00000000 },
|
||||
{ 0x00009998, 0x00000000 },
|
||||
{ 0x0000999c, 0x00000000 },
|
||||
{ 0x000099a0, 0x00000000 },
|
||||
{ 0x000099a4, 0x00000001 },
|
||||
{ 0x000099a8, 0x201fff00 },
|
||||
{ 0x000099ac, 0x2def0400 },
|
||||
{ 0x000099b0, 0x03051000 },
|
||||
{ 0x000099b4, 0x00000820 },
|
||||
{ 0x000099dc, 0x00000000 },
|
||||
{ 0x000099e0, 0x00000000 },
|
||||
{ 0x000099e4, 0xaaaaaaaa },
|
||||
{ 0x000099e8, 0x3c466478 },
|
||||
{ 0x000099ec, 0x0cc80caa },
|
||||
{ 0x000099f0, 0x00000000 },
|
||||
{ 0x0000a208, 0x803e68c8 },
|
||||
{ 0x0000a210, 0x4080a333 },
|
||||
{ 0x0000a214, 0x00206c10 },
|
||||
{ 0x0000a218, 0x009c4060 },
|
||||
{ 0x0000a220, 0x01834061 },
|
||||
{ 0x0000a224, 0x00000400 },
|
||||
{ 0x0000a228, 0x000003b5 },
|
||||
{ 0x0000a22c, 0x00000000 },
|
||||
{ 0x0000a234, 0x20202020 },
|
||||
{ 0x0000a238, 0x20202020 },
|
||||
{ 0x0000a244, 0x00000000 },
|
||||
{ 0x0000a248, 0xfffffffc },
|
||||
{ 0x0000a24c, 0x00000000 },
|
||||
{ 0x0000a254, 0x00000000 },
|
||||
{ 0x0000a258, 0x0ccb5380 },
|
||||
{ 0x0000a25c, 0x15151501 },
|
||||
{ 0x0000a260, 0xdfa90f01 },
|
||||
{ 0x0000a268, 0x00000000 },
|
||||
{ 0x0000a26c, 0x0ebae9e6 },
|
||||
{ 0x0000d270, 0x0d820820 },
|
||||
{ 0x0000d35c, 0x07ffffef },
|
||||
{ 0x0000d360, 0x0fffffe7 },
|
||||
{ 0x0000d364, 0x17ffffe5 },
|
||||
{ 0x0000d368, 0x1fffffe4 },
|
||||
{ 0x0000d36c, 0x37ffffe3 },
|
||||
{ 0x0000d370, 0x3fffffe3 },
|
||||
{ 0x0000d374, 0x57ffffe3 },
|
||||
{ 0x0000d378, 0x5fffffe2 },
|
||||
{ 0x0000d37c, 0x7fffffe2 },
|
||||
{ 0x0000d380, 0x7f3c7bba },
|
||||
{ 0x0000d384, 0xf3307ff0 },
|
||||
{ 0x0000a388, 0x0c000000 },
|
||||
{ 0x0000a38c, 0x20202020 },
|
||||
{ 0x0000a390, 0x20202020 },
|
||||
{ 0x0000a39c, 0x00000001 },
|
||||
{ 0x0000a3a0, 0x00000000 },
|
||||
{ 0x0000a3a4, 0x00000000 },
|
||||
{ 0x0000a3a8, 0x00000000 },
|
||||
{ 0x0000a3ac, 0x00000000 },
|
||||
{ 0x0000a3b0, 0x00000000 },
|
||||
{ 0x0000a3b4, 0x00000000 },
|
||||
{ 0x0000a3b8, 0x00000000 },
|
||||
{ 0x0000a3bc, 0x00000000 },
|
||||
{ 0x0000a3c0, 0x00000000 },
|
||||
{ 0x0000a3c4, 0x00000000 },
|
||||
{ 0x0000a3cc, 0x20202020 },
|
||||
{ 0x0000a3d0, 0x20202020 },
|
||||
{ 0x0000a3d4, 0x20202020 },
|
||||
{ 0x0000a3e4, 0x00000000 },
|
||||
{ 0x0000a3e8, 0x18c43433 },
|
||||
{ 0x0000a3ec, 0x00f70081 },
|
||||
{ 0x00007800, 0x00140000 },
|
||||
{ 0x00007804, 0x0e4548d8 },
|
||||
{ 0x00007808, 0x54214514 },
|
||||
{ 0x0000780c, 0x02025830 },
|
||||
{ 0x00007810, 0x71c0d388 },
|
||||
{ 0x00007814, 0x924934a8 },
|
||||
{ 0x0000781c, 0x00000000 },
|
||||
{ 0x00007824, 0x00d86fff },
|
||||
{ 0x00007828, 0x26d2491b },
|
||||
{ 0x0000782c, 0x6e36d97b },
|
||||
{ 0x00007830, 0xedb6d96e },
|
||||
{ 0x00007834, 0x71400087 },
|
||||
{ 0x0000783c, 0x0001fffe },
|
||||
{ 0x00007840, 0xffeb1a20 },
|
||||
{ 0x00007844, 0x000c0db6 },
|
||||
{ 0x00007848, 0x6db61b6f },
|
||||
{ 0x0000784c, 0x6d9b66db },
|
||||
{ 0x00007850, 0x6d8c6dba },
|
||||
{ 0x00007854, 0x00040000 },
|
||||
{ 0x00007858, 0xdb003012 },
|
||||
{ 0x0000785c, 0x04924914 },
|
||||
{ 0x00007860, 0x21084210 },
|
||||
{ 0x00007864, 0xf7d7ffde },
|
||||
{ 0x00007868, 0xc2034080 },
|
||||
{ 0x00007870, 0x10142c00 },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285Modes_high_power_tx_gain_v2[][6] = {
|
||||
/* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
|
||||
{ 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 },
|
||||
{ 0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000 },
|
||||
{ 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 },
|
||||
{ 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 },
|
||||
{ 0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600, 0x00000000 },
|
||||
{ 0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800, 0x00000000 },
|
||||
{ 0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802, 0x00000000 },
|
||||
{ 0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805, 0x00000000 },
|
||||
{ 0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80, 0x00000000 },
|
||||
{ 0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00, 0x00000000 },
|
||||
{ 0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 },
|
||||
{ 0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80, 0x00000000 },
|
||||
{ 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 },
|
||||
{ 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
|
||||
{ 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
|
||||
{ 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x00007838, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803 },
|
||||
{ 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe },
|
||||
{ 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
|
||||
{ 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652, 0x0a22a652 },
|
||||
{ 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
|
||||
{ 0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7 },
|
||||
{ 0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
|
||||
{ 0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
|
||||
{ 0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
|
||||
{ 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285Modes_original_tx_gain_v2[][6] = {
|
||||
/* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
|
||||
{ 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
|
||||
{ 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
|
||||
{ 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
|
||||
{ 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
|
||||
{ 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 },
|
||||
{ 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 },
|
||||
{ 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 },
|
||||
{ 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 },
|
||||
{ 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 },
|
||||
{ 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 },
|
||||
{ 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 },
|
||||
{ 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 },
|
||||
{ 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 },
|
||||
{ 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 },
|
||||
{ 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
|
||||
{ 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
|
||||
{ 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
|
||||
{ 0x00007838, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801 },
|
||||
{ 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
|
||||
{ 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
|
||||
{ 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
|
||||
{ 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
|
||||
{ 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c },
|
||||
{ 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
|
||||
{ 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
|
||||
{ 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
|
||||
{ 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_v2[][2] = {
|
||||
{0x00004040, 0x9248fd00 },
|
||||
{0x00004040, 0x24924924 },
|
||||
{0x00004040, 0xa8000019 },
|
||||
{0x00004040, 0x13160820 },
|
||||
{0x00004040, 0xe5980560 },
|
||||
{0x00004040, 0xc01dcffd },
|
||||
{0x00004040, 0x1aaabe41 },
|
||||
{0x00004040, 0xbe105554 },
|
||||
{0x00004040, 0x00043007 },
|
||||
{0x00004044, 0x00000000 },
|
||||
};
|
||||
|
||||
static const u_int32_t ar9285PciePhy_clkreq_off_L1_v2[][2] = {
|
||||
{0x00004040, 0x9248fd00 },
|
||||
{0x00004040, 0x24924924 },
|
||||
{0x00004040, 0xa8000019 },
|
||||
{0x00004040, 0x13160820 },
|
||||
{0x00004040, 0xe5980560 },
|
||||
{0x00004040, 0xc01dcffc },
|
||||
{0x00004040, 0x1aaabe41 },
|
||||
{0x00004040, 0xbe105554 },
|
||||
{0x00004040, 0x00043007 },
|
||||
{0x00004044, 0x00000000 },
|
||||
};
|
||||
@@ -469,7 +469,7 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
|
||||
/*
|
||||
* Allocate hardware transmit queues: one queue for
|
||||
* beacon frames and one data queue for each QoS
|
||||
* priority. Note that the hal handles reseting
|
||||
* priority. Note that the hal handles resetting
|
||||
* these queues at the needed time.
|
||||
*
|
||||
* XXX PS-Poll
|
||||
@@ -562,7 +562,6 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
|
||||
ifp->if_softc = sc;
|
||||
ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
|
||||
ifp->if_start = ath_start;
|
||||
ifp->if_watchdog = NULL;
|
||||
ifp->if_ioctl = ath_ioctl;
|
||||
ifp->if_init = ath_init;
|
||||
IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
|
||||
@@ -623,6 +622,13 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
|
||||
sc->sc_wmetkipmic = 1;
|
||||
}
|
||||
sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
|
||||
/*
|
||||
* Check for multicast key search support.
|
||||
*/
|
||||
if (ath_hal_hasmcastkeysearch(sc->sc_ah) &&
|
||||
!ath_hal_getmcastkeysearch(sc->sc_ah)) {
|
||||
ath_hal_setmcastkeysearch(sc->sc_ah, 1);
|
||||
}
|
||||
sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
|
||||
/*
|
||||
* Mark key cache slots associated with global keys
|
||||
@@ -1193,7 +1199,7 @@ ath_suspend(struct ath_softc *sc)
|
||||
/*
|
||||
* NB: don't worry about putting the chip in low power
|
||||
* mode; pci will power off our socket on suspend and
|
||||
* cardbus detaches the device.
|
||||
* CardBus detaches the device.
|
||||
*/
|
||||
}
|
||||
|
||||
@@ -1460,7 +1466,7 @@ ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs)
|
||||
uint32_t rsize;
|
||||
void *sp;
|
||||
|
||||
if (!ath_hal_getdiagstate(ah, 32, &mask, sizeof(&mask), &sp, &rsize))
|
||||
if (!ath_hal_getdiagstate(ah, 32, &mask, sizeof(mask), &sp, &rsize))
|
||||
return 0;
|
||||
KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize));
|
||||
*hangs = *(uint32_t *)sp;
|
||||
@@ -1477,7 +1483,7 @@ ath_bmiss_proc(void *arg, int pending)
|
||||
DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
|
||||
|
||||
if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) {
|
||||
if_printf(ifp, "bb hang detected (0x%x), reseting\n", hangs);
|
||||
if_printf(ifp, "bb hang detected (0x%x), resetting\n", hangs);
|
||||
ath_reset(ifp);
|
||||
} else
|
||||
ieee80211_beacon_miss(ifp->if_l2com);
|
||||
@@ -2047,7 +2053,7 @@ ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k,
|
||||
if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) {
|
||||
/*
|
||||
* Group keys on hardware that supports multicast frame
|
||||
* key search use a mac that is the sender's address with
|
||||
* key search use a MAC that is the sender's address with
|
||||
* the high bit set instead of the app-specified address.
|
||||
*/
|
||||
IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr);
|
||||
@@ -2227,8 +2233,10 @@ ath_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k,
|
||||
* it permits us to support multiple users for adhoc and/or
|
||||
* multi-station operation.
|
||||
*/
|
||||
if (k->wk_keyix != IEEE80211_KEYIX_NONE || /* global key */
|
||||
((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey)) {
|
||||
if (k->wk_keyix != IEEE80211_KEYIX_NONE) {
|
||||
/*
|
||||
* Only global keys should have key index assigned.
|
||||
*/
|
||||
if (!(&vap->iv_nw_keys[0] <= k &&
|
||||
k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) {
|
||||
/* should not happen */
|
||||
@@ -2236,12 +2244,21 @@ ath_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k,
|
||||
"%s: bogus group key\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
if (vap->iv_opmode != IEEE80211_M_HOSTAP ||
|
||||
!(k->wk_flags & IEEE80211_KEY_GROUP) ||
|
||||
!sc->sc_mcastkey) {
|
||||
/*
|
||||
* XXX we pre-allocate the global keys so
|
||||
* have no way to check if they've already
|
||||
* been allocated.
|
||||
*/
|
||||
*keyix = *rxkeyix = k - vap->iv_nw_keys;
|
||||
return 1;
|
||||
}
|
||||
/*
|
||||
* XXX we pre-allocate the global keys so
|
||||
* have no way to check if they've already been allocated.
|
||||
* Group key and device supports multicast key search.
|
||||
*/
|
||||
*keyix = *rxkeyix = k - vap->iv_nw_keys;
|
||||
return 1;
|
||||
k->wk_keyix = IEEE80211_KEYIX_NONE;
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -5333,7 +5350,7 @@ ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
|
||||
|
||||
/*
|
||||
* Set/change channels. If the channel is really being changed,
|
||||
* it's done by reseting the chip. To accomplish this we must
|
||||
* it's done by resetting the chip. To accomplish this we must
|
||||
* first cleanup any pending DMA, then restart stuff after a la
|
||||
* ath_init.
|
||||
*/
|
||||
@@ -5360,7 +5377,7 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
|
||||
ath_stoprecv(sc); /* turn off frame recv */
|
||||
if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) {
|
||||
if_printf(ifp, "%s: unable to reset "
|
||||
"channel %u (%u Mhz, flags 0x%x), hal status %u\n",
|
||||
"channel %u (%u MHz, flags 0x%x), hal status %u\n",
|
||||
__func__, ieee80211_chan2ieee(ic, chan),
|
||||
chan->ic_freq, chan->ic_flags, status);
|
||||
return EIO;
|
||||
@@ -6039,7 +6056,7 @@ ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
|
||||
sc->sc_protrix = ath_tx_findrix(sc, 2*2);
|
||||
else
|
||||
sc->sc_protrix = ath_tx_findrix(sc, 2*1);
|
||||
/* NB: caller is responsible for reseting rate control state */
|
||||
/* NB: caller is responsible for resetting rate control state */
|
||||
#undef N
|
||||
}
|
||||
|
||||
@@ -6953,6 +6970,8 @@ ath_announce(struct ath_softc *sc)
|
||||
if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
|
||||
if (ath_txbuf != ATH_TXBUF)
|
||||
if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
|
||||
if (sc->sc_mcastkey && bootverbose)
|
||||
if_printf(ifp, "using multicast key search\n");
|
||||
}
|
||||
|
||||
#ifdef IEEE80211_SUPPORT_TDMA
|
||||
|
||||
@@ -584,14 +584,12 @@ void ath_intr(void *);
|
||||
ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
|
||||
#define ath_hal_hasbursting(_ah) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
|
||||
#ifdef notyet
|
||||
#define ath_hal_setmcastkeysearch(_ah, _v) \
|
||||
ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL)
|
||||
#define ath_hal_hasmcastkeysearch(_ah) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
|
||||
#define ath_hal_getmcastkeysearch(_ah) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
|
||||
#else
|
||||
#define ath_hal_getmcastkeysearch(_ah) 0
|
||||
#endif
|
||||
#define ath_hal_hasfastframes(_ah) \
|
||||
(ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK)
|
||||
#define ath_hal_hasbssidmask(_ah) \
|
||||
|
||||
Reference in New Issue
Block a user