intel_extreme: Fix DP / HDMI gpu register location mixup on die

headers/private/graphics/intel_extreme/intel_extreme.h

@@ -522,6 +522,11 @@ struct intel_free_graphics_memory {
 #define INTEL_DISPLAY_PORT_C			(0x4200 | REGS_SOUTH_TRANSCODER_PORT)
 #define INTEL_DISPLAY_PORT_D			(0x4300 | REGS_SOUTH_TRANSCODER_PORT)
 
+// Unless you're a damn Valley/CherryView unicorn :-(
+#define VLV_DISPLAY_PORT_B				(VLV_DISPLAY_BASE + 0x64100)
+#define VLV_DISPLAY_PORT_C				(VLV_DISPLAY_BASE + 0x64200)
+#define CHV_DISPLAY_PORT_D				(VLV_DISPLAY_BASE + 0x64300)
+
 // planes
 #define INTEL_PIPE_ENABLED				(1UL << 31)
 #define INTEL_PIPE_CONTROL				0x0008

src/add-ons/accelerants/intel_extreme/Ports.cpp

@@ -770,14 +770,35 @@ DisplayPort::IsConnected()
 addr_t
 DisplayPort::_PortRegister()
 {
+	// There are 6000 lines of intel linux code probing DP registers
+	// to properly detect DP vs eDP to then in-turn properly figure out
+	// what is DP and what is HDMI. It only takes 3 lines to
+	// ignore DisplayPort on ValleyView / CherryView
+
+	if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_VLV)
+		|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_CHV))
+		return 0;
+
+	// Intel, are humans even involved anymore?
+	// This is a lot more complex than this code makes it look. (see defines)
+	// INTEL_DISPLAY_PORT_X moves around a lot based on PCH
+	// except on ValleyView and CherryView.
 	switch (PortIndex()) {
 		case INTEL_PORT_A:
 			return INTEL_DISPLAY_PORT_A;
 		case INTEL_PORT_B:
+			if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_VLV))
+				return VLV_DISPLAY_PORT_B;
 			return INTEL_DISPLAY_PORT_B;
 		case INTEL_PORT_C:
+			if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_VLV))
+				return VLV_DISPLAY_PORT_C;
 			return INTEL_DISPLAY_PORT_C;
 		case INTEL_PORT_D:
+			if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_CHV))
+				return CHV_DISPLAY_PORT_D;
+			else if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_VLV))
+				return 0;
 			return INTEL_DISPLAY_PORT_D;
 		default:
 			return 0;