Allocating additional memory should now work on the i965 as well (but bad things
will happen on earlier i9xx chips for now...). Not yet tested. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22589 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@@ -158,7 +158,10 @@ struct intel_free_graphics_memory {
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#define INTEL_PAGE_TABLE_CONTROL 0x02020
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#define INTEL_PAGE_TABLE_CONTROL 0x02020
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#define INTEL_PAGE_TABLE_ERROR 0x02024
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#define INTEL_PAGE_TABLE_ERROR 0x02024
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#define INTEL_HARDWARE_STATUS_PAGE 0x02080
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#define INTEL_HARDWARE_STATUS_PAGE 0x02080
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#define INTEL_GTT_BASE 0x10000 // (- 0x2ffff)
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#define i830_GTT_BASE 0x10000 // (- 0x2ffff)
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#define i830_GTT_SIZE 0x20000
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#define i965_GTT_BASE 0x80000 // (- 0xfffff)
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#define i965_GTT_SIZE 0x80000
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#define GTT_ENTRY_VALID 0x01
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#define GTT_ENTRY_VALID 0x01
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#define GTT_ENTRY_LOCAL_MEMORY 0x02
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#define GTT_ENTRY_LOCAL_MEMORY 0x02
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@@ -191,7 +191,7 @@ determine_stolen_memory_size(intel_info &info)
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static void
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static void
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set_gtt_entry(intel_info &info, uint32 offset, uint8 *physicalAddress)
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set_gtt_entry(intel_info &info, uint32 offset, uint8 *physicalAddress)
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{
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{
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write32(info.registers + INTEL_GTT_BASE + (offset >> 10),
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write32(info.gtt_base + (offset >> 10),
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(uint32)physicalAddress | GTT_ENTRY_VALID);
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(uint32)physicalAddress | GTT_ENTRY_VALID);
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}
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}
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@@ -391,6 +391,21 @@ intel_extreme_init(intel_info &info)
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if (info.memory_manager == NULL)
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if (info.memory_manager == NULL)
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return B_NO_MEMORY;
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return B_NO_MEMORY;
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if ((info.device_type & INTEL_TYPE_9xx) != 0) {
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if ((info.device_type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_965) {
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info.gtt_base = info.registers + i965_GTT_BASE;
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info.gtt_size = i965_GTT_SIZE;
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} else {
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// TODO: map it in???
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info.gtt_base = (uint8*)info.pci->u.h0.base_register_sizes[3];
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info.gtt_size = i830_GTT_SIZE;
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// TODO: for now...
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}
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} else {
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info.gtt_base = info.registers + i830_GTT_BASE;
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info.gtt_size = i830_GTT_SIZE;
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}
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// reserve ring buffer memory (currently, this memory is placed in
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// reserve ring buffer memory (currently, this memory is placed in
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// the graphics memory), but this could bring us problems with
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// the graphics memory), but this could bring us problems with
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// write combining...
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// write combining...
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@@ -29,6 +29,8 @@ struct intel_info {
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struct overlay_registers *overlay_registers;
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struct overlay_registers *overlay_registers;
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// update buffer, shares an area with shared_info
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// update buffer, shares an area with shared_info
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uint8 *gtt_base;
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size_t gtt_size;
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uint8 *graphics_memory;
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uint8 *graphics_memory;
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area_id graphics_memory_area;
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area_id graphics_memory_area;
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area_id additional_memory_area;
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area_id additional_memory_area;
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