intel_extreme: remove unhandled generation defines
- 7xx (1st gen) has no driver in Haiku or is handled by the intel_810 driver - PowerVR has no driver in Haiku So there is no point in having those in the intel_extreme driver. While I'm at it, fix the video timing/resolution constraints for sanitize_video_mode.
This commit is contained in:
@@ -25,14 +25,14 @@
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#define INTEL_GROUP_MASK 0x00fffff0
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#define INTEL_GROUP_MASK 0x00fffff0
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#define INTEL_MODEL_MASK 0x00ffffff
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#define INTEL_MODEL_MASK 0x00ffffff
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#define INTEL_TYPE_MASK 0x0000000f
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#define INTEL_TYPE_MASK 0x0000000f
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// families
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// families
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#define INTEL_FAMILY_7xx 0x00010000 // First Gen
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#define INTEL_FAMILY_8xx 0x00020000 // Second Gen
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#define INTEL_FAMILY_8xx 0x00020000 // Second Gen
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#define INTEL_FAMILY_9xx 0x00040000 // Third Gen +
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#define INTEL_FAMILY_9xx 0x00040000 // Third Gen +
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#define INTEL_FAMILY_SER5 0x00080000 // Intel5 Series
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#define INTEL_FAMILY_SER5 0x00080000 // Intel5 Series
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#define INTEL_FAMILY_POVR 0x00100000 // PowerVR (uugh)
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#define INTEL_FAMILY_SOC0 0x00200000 // Atom SOC
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#define INTEL_FAMILY_SOC0 0x00200000 // Atom SOC
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#define INTEL_FAMILY_LAKE 0x00400000 // Intel Lakes
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#define INTEL_FAMILY_LAKE 0x00400000 // Intel Lakes
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// groups
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// groups
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#define INTEL_GROUP_83x (INTEL_FAMILY_8xx | 0x0010)
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#define INTEL_GROUP_83x (INTEL_FAMILY_8xx | 0x0010)
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#define INTEL_GROUP_85x (INTEL_FAMILY_8xx | 0x0020)
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#define INTEL_GROUP_85x (INTEL_FAMILY_8xx | 0x0020)
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@@ -46,8 +46,6 @@
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#define INTEL_GROUP_SNB (INTEL_FAMILY_SER5 | 0x0020) // SandyBridge
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#define INTEL_GROUP_SNB (INTEL_FAMILY_SER5 | 0x0020) // SandyBridge
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#define INTEL_GROUP_IVB (INTEL_FAMILY_SER5 | 0x0040) // IvyBridge
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#define INTEL_GROUP_IVB (INTEL_FAMILY_SER5 | 0x0040) // IvyBridge
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#define INTEL_GROUP_HAS (INTEL_FAMILY_SER5 | 0x0080) // Haswell
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#define INTEL_GROUP_HAS (INTEL_FAMILY_SER5 | 0x0080) // Haswell
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#define INTEL_GROUP_SLT (INTEL_FAMILY_POVR | 0x0010) // Saltwell
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#define INTEL_GROUP_FSM (INTEL_FAMILY_POVR | 0x0020) // Fu.Silvermont
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#define INTEL_GROUP_VLV (INTEL_FAMILY_SOC0 | 0x0010) // ValleyView
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#define INTEL_GROUP_VLV (INTEL_FAMILY_SOC0 | 0x0010) // ValleyView
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#define INTEL_GROUP_CHV (INTEL_FAMILY_SOC0 | 0x0020) // CherryView
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#define INTEL_GROUP_CHV (INTEL_FAMILY_SOC0 | 0x0020) // CherryView
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#define INTEL_GROUP_BDW (INTEL_FAMILY_SOC0 | 0x0040) // Broadwell
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#define INTEL_GROUP_BDW (INTEL_FAMILY_SOC0 | 0x0040) // Broadwell
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@@ -191,8 +189,6 @@ struct DeviceType {
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int Generation() const
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int Generation() const
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{
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{
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if (InFamily(INTEL_FAMILY_7xx))
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return 1;
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if (InFamily(INTEL_FAMILY_8xx))
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if (InFamily(INTEL_FAMILY_8xx))
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return 2;
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return 2;
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if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x)
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if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x)
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@@ -211,7 +207,7 @@ struct DeviceType {
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if (InFamily(INTEL_FAMILY_LAKE))
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if (InFamily(INTEL_FAMILY_LAKE))
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return 9;
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return 9;
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// Generation 0 means somethins is wrong :-)
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// Generation 0 means something is wrong :-)
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return 0;
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return 0;
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}
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}
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};
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};
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@@ -597,12 +597,10 @@ intel_get_accelerant_device_info(accelerant_device_info* info)
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DeviceType* type = &gInfo->shared_info->device_type;
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DeviceType* type = &gInfo->shared_info->device_type;
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if (type->InFamily(INTEL_FAMILY_7xx) || type->InFamily(INTEL_FAMILY_8xx))
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if (type->InFamily(INTEL_FAMILY_8xx))
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strcpy(info->name, "Intel Extreme");
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strcpy(info->name, "Intel Extreme");
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else if (type->InFamily(INTEL_FAMILY_9xx))
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else if (type->InFamily(INTEL_FAMILY_9xx))
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strcpy(info->name, "Intel GMA");
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strcpy(info->name, "Intel GMA");
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else if (type->InFamily(INTEL_FAMILY_POVR))
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strcpy(info->name, "Intel PowerVR");
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else if (type->InFamily(INTEL_FAMILY_SOC0))
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else if (type->InFamily(INTEL_FAMILY_SOC0))
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strcpy(info->name, "Intel Atom");
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strcpy(info->name, "Intel Atom");
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else if (type->InFamily(INTEL_FAMILY_SER5))
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else if (type->InFamily(INTEL_FAMILY_SER5))
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@@ -122,7 +122,6 @@ get_accelerant_hook(uint32 feature, void* data)
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|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)
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|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)
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|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_ILK)
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|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_ILK)
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|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SER5)
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|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SER5)
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|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_POVR)
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|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SOC0))
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|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SOC0))
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return NULL;
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return NULL;
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@@ -81,29 +81,25 @@ get_color_space_format(const display_mode &mode, uint32 &colorMode,
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static bool
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static bool
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sanitize_display_mode(display_mode& mode)
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sanitize_display_mode(display_mode& mode)
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{
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{
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// Some cards only support even pixel counts, while others require an odd
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// one.
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uint16 pixelCount = 1;
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uint16 pixelCount = 1;
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// Older cards require pixel count to be even
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if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_Gxx)
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if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_Gxx)
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|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x)
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|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x)
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|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_94x)
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|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_94x)
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|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_91x)
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|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_91x)
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|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_8xx)
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|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_8xx)) {
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|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_7xx)) {
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pixelCount = 2;
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pixelCount = 2;
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}
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}
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// TODO: verify constraints - these are more or less taken from the
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// radeon driver!
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display_constraints constraints = {
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display_constraints constraints = {
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// resolution
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// resolution
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320, 8192, 200, 4096,
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320, 4096, 200, 4096,
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// pixel clock
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// pixel clock
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gInfo->shared_info->pll_info.min_frequency,
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gInfo->shared_info->pll_info.min_frequency,
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gInfo->shared_info->pll_info.max_frequency,
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gInfo->shared_info->pll_info.max_frequency,
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// horizontal
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// horizontal
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{pixelCount, 0, 8160, 32, 8192, 0, 8192},
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{pixelCount, 0, 8160, 32, 8192, 0, 8192},
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{1, 1, 4092, 2, 63, 1, 4096}
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{1, 1, 8190, 2, 8192, 1, 8192}
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};
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};
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return sanitize_display_mode(mode, constraints,
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return sanitize_display_mode(mode, constraints,
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@@ -276,9 +276,8 @@ determine_gtt_stolen(intel_info &info)
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}
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}
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} else if (info.type->InGroup(INTEL_GROUP_85x)
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} else if (info.type->InGroup(INTEL_GROUP_85x)
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|| info.type->InFamily(INTEL_FAMILY_9xx)
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|| info.type->InFamily(INTEL_FAMILY_9xx)
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|| info.type->InFamily(INTEL_FAMILY_SER5)
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|| info.type->InFamily(INTEL_FAMILY_SER5)
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|| info.type->InFamily(INTEL_FAMILY_SOC0)
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|| info.type->InFamily(INTEL_FAMILY_SOC0)) {
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|| info.type->InFamily(INTEL_FAMILY_POVR)) {
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switch (memoryConfig & STOLEN_MEMORY_MASK) {
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switch (memoryConfig & STOLEN_MEMORY_MASK) {
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case i855_STOLEN_MEMORY_4M:
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case i855_STOLEN_MEMORY_4M:
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memorySize *= 4;
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memorySize *= 4;
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