intel_extreme: remove unhandled generation defines

- 7xx (1st gen) has no driver in Haiku or is handled by the intel_810 driver
- PowerVR has no driver in Haiku

So there is no point in having those in the intel_extreme driver.

While I'm at it, fix the video timing/resolution constraints for
sanitize_video_mode.
This commit is contained in:
Adrien Destugues
2020-01-27 13:58:52 +01:00
parent 5cd8219db6
commit ec4e9ea8bc
5 changed files with 10 additions and 22 deletions
@@ -25,14 +25,14 @@
#define INTEL_GROUP_MASK 0x00fffff0 #define INTEL_GROUP_MASK 0x00fffff0
#define INTEL_MODEL_MASK 0x00ffffff #define INTEL_MODEL_MASK 0x00ffffff
#define INTEL_TYPE_MASK 0x0000000f #define INTEL_TYPE_MASK 0x0000000f
// families // families
#define INTEL_FAMILY_7xx 0x00010000 // First Gen
#define INTEL_FAMILY_8xx 0x00020000 // Second Gen #define INTEL_FAMILY_8xx 0x00020000 // Second Gen
#define INTEL_FAMILY_9xx 0x00040000 // Third Gen + #define INTEL_FAMILY_9xx 0x00040000 // Third Gen +
#define INTEL_FAMILY_SER5 0x00080000 // Intel5 Series #define INTEL_FAMILY_SER5 0x00080000 // Intel5 Series
#define INTEL_FAMILY_POVR 0x00100000 // PowerVR (uugh)
#define INTEL_FAMILY_SOC0 0x00200000 // Atom SOC #define INTEL_FAMILY_SOC0 0x00200000 // Atom SOC
#define INTEL_FAMILY_LAKE 0x00400000 // Intel Lakes #define INTEL_FAMILY_LAKE 0x00400000 // Intel Lakes
// groups // groups
#define INTEL_GROUP_83x (INTEL_FAMILY_8xx | 0x0010) #define INTEL_GROUP_83x (INTEL_FAMILY_8xx | 0x0010)
#define INTEL_GROUP_85x (INTEL_FAMILY_8xx | 0x0020) #define INTEL_GROUP_85x (INTEL_FAMILY_8xx | 0x0020)
@@ -46,8 +46,6 @@
#define INTEL_GROUP_SNB (INTEL_FAMILY_SER5 | 0x0020) // SandyBridge #define INTEL_GROUP_SNB (INTEL_FAMILY_SER5 | 0x0020) // SandyBridge
#define INTEL_GROUP_IVB (INTEL_FAMILY_SER5 | 0x0040) // IvyBridge #define INTEL_GROUP_IVB (INTEL_FAMILY_SER5 | 0x0040) // IvyBridge
#define INTEL_GROUP_HAS (INTEL_FAMILY_SER5 | 0x0080) // Haswell #define INTEL_GROUP_HAS (INTEL_FAMILY_SER5 | 0x0080) // Haswell
#define INTEL_GROUP_SLT (INTEL_FAMILY_POVR | 0x0010) // Saltwell
#define INTEL_GROUP_FSM (INTEL_FAMILY_POVR | 0x0020) // Fu.Silvermont
#define INTEL_GROUP_VLV (INTEL_FAMILY_SOC0 | 0x0010) // ValleyView #define INTEL_GROUP_VLV (INTEL_FAMILY_SOC0 | 0x0010) // ValleyView
#define INTEL_GROUP_CHV (INTEL_FAMILY_SOC0 | 0x0020) // CherryView #define INTEL_GROUP_CHV (INTEL_FAMILY_SOC0 | 0x0020) // CherryView
#define INTEL_GROUP_BDW (INTEL_FAMILY_SOC0 | 0x0040) // Broadwell #define INTEL_GROUP_BDW (INTEL_FAMILY_SOC0 | 0x0040) // Broadwell
@@ -191,8 +189,6 @@ struct DeviceType {
int Generation() const int Generation() const
{ {
if (InFamily(INTEL_FAMILY_7xx))
return 1;
if (InFamily(INTEL_FAMILY_8xx)) if (InFamily(INTEL_FAMILY_8xx))
return 2; return 2;
if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x) if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x)
@@ -211,7 +207,7 @@ struct DeviceType {
if (InFamily(INTEL_FAMILY_LAKE)) if (InFamily(INTEL_FAMILY_LAKE))
return 9; return 9;
// Generation 0 means somethins is wrong :-) // Generation 0 means something is wrong :-)
return 0; return 0;
} }
}; };
@@ -597,12 +597,10 @@ intel_get_accelerant_device_info(accelerant_device_info* info)
DeviceType* type = &gInfo->shared_info->device_type; DeviceType* type = &gInfo->shared_info->device_type;
if (type->InFamily(INTEL_FAMILY_7xx) || type->InFamily(INTEL_FAMILY_8xx)) if (type->InFamily(INTEL_FAMILY_8xx))
strcpy(info->name, "Intel Extreme"); strcpy(info->name, "Intel Extreme");
else if (type->InFamily(INTEL_FAMILY_9xx)) else if (type->InFamily(INTEL_FAMILY_9xx))
strcpy(info->name, "Intel GMA"); strcpy(info->name, "Intel GMA");
else if (type->InFamily(INTEL_FAMILY_POVR))
strcpy(info->name, "Intel PowerVR");
else if (type->InFamily(INTEL_FAMILY_SOC0)) else if (type->InFamily(INTEL_FAMILY_SOC0))
strcpy(info->name, "Intel Atom"); strcpy(info->name, "Intel Atom");
else if (type->InFamily(INTEL_FAMILY_SER5)) else if (type->InFamily(INTEL_FAMILY_SER5))
@@ -122,7 +122,6 @@ get_accelerant_hook(uint32 feature, void* data)
|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN) || gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)
|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_ILK) || gInfo->shared_info->device_type.InGroup(INTEL_GROUP_ILK)
|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SER5) || gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SER5)
|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_POVR)
|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SOC0)) || gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SOC0))
return NULL; return NULL;
@@ -81,29 +81,25 @@ get_color_space_format(const display_mode &mode, uint32 &colorMode,
static bool static bool
sanitize_display_mode(display_mode& mode) sanitize_display_mode(display_mode& mode)
{ {
// Some cards only support even pixel counts, while others require an odd
// one.
uint16 pixelCount = 1; uint16 pixelCount = 1;
// Older cards require pixel count to be even
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_Gxx) if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_Gxx)
|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x) || gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x)
|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_94x) || gInfo->shared_info->device_type.InGroup(INTEL_GROUP_94x)
|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_91x) || gInfo->shared_info->device_type.InGroup(INTEL_GROUP_91x)
|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_8xx) || gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_8xx)) {
|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_7xx)) {
pixelCount = 2; pixelCount = 2;
} }
// TODO: verify constraints - these are more or less taken from the
// radeon driver!
display_constraints constraints = { display_constraints constraints = {
// resolution // resolution
320, 8192, 200, 4096, 320, 4096, 200, 4096,
// pixel clock // pixel clock
gInfo->shared_info->pll_info.min_frequency, gInfo->shared_info->pll_info.min_frequency,
gInfo->shared_info->pll_info.max_frequency, gInfo->shared_info->pll_info.max_frequency,
// horizontal // horizontal
{pixelCount, 0, 8160, 32, 8192, 0, 8192}, {pixelCount, 0, 8160, 32, 8192, 0, 8192},
{1, 1, 4092, 2, 63, 1, 4096} {1, 1, 8190, 2, 8192, 1, 8192}
}; };
return sanitize_display_mode(mode, constraints, return sanitize_display_mode(mode, constraints,
@@ -276,9 +276,8 @@ determine_gtt_stolen(intel_info &info)
} }
} else if (info.type->InGroup(INTEL_GROUP_85x) } else if (info.type->InGroup(INTEL_GROUP_85x)
|| info.type->InFamily(INTEL_FAMILY_9xx) || info.type->InFamily(INTEL_FAMILY_9xx)
|| info.type->InFamily(INTEL_FAMILY_SER5) || info.type->InFamily(INTEL_FAMILY_SER5)
|| info.type->InFamily(INTEL_FAMILY_SOC0) || info.type->InFamily(INTEL_FAMILY_SOC0)) {
|| info.type->InFamily(INTEL_FAMILY_POVR)) {
switch (memoryConfig & STOLEN_MEMORY_MASK) { switch (memoryConfig & STOLEN_MEMORY_MASK) {
case i855_STOLEN_MEMORY_4M: case i855_STOLEN_MEMORY_4M:
memorySize *= 4; memorySize *= 4;