Attansic L2 Fast Ethernet driver for Haiku. Port of FreeBSD driver from:

http://www.SpringDaemons.com/stas/if_ae-1214569185.tar.bz2
(This is the wired NIC on the Asus EEE PC!)
NOTE: It is not in the image because it currently still crashes, will look into that soon.



git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@27290 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Ithamar R. Adema
2008-09-02 22:19:45 +00:00
parent 1b65b57dd5
commit ed64c85f06
11 changed files with 2796 additions and 0 deletions
@@ -20,6 +20,7 @@ SubInclude HAIKU_TOP src add-ons kernel drivers network marvell_yukon ;
SubInclude HAIKU_TOP src add-ons kernel drivers network nforce ;
SubInclude HAIKU_TOP src add-ons kernel drivers network pcnet ;
SubInclude HAIKU_TOP src add-ons kernel drivers network syskonnect ;
SubInclude HAIKU_TOP src add-ons kernel drivers network attansic_l2 ;
SubIncludeGPL HAIKU_TOP src add-ons kernel drivers network bcm440x ;
SubIncludeGPL HAIKU_TOP src add-ons kernel drivers network bcm570x ;
@@ -0,0 +1,3 @@
SubDir HAIKU_TOP src add-ons kernel drivers network attansic_l2 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network attansic_l2 dev ;
@@ -0,0 +1,5 @@
SubDir HAIKU_TOP src add-ons kernel drivers network attansic_l2 dev ;
SubInclude HAIKU_TOP src add-ons kernel drivers network attansic_l2 dev mii ;
SubInclude HAIKU_TOP src add-ons kernel drivers network attansic_l2 dev ae ;
@@ -0,0 +1,14 @@
SubDir HAIKU_TOP src add-ons kernel drivers network attansic_l2 dev ae ;
UsePrivateHeaders kernel net ;
UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ;
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
KernelAddon attansic_l2 :
if_ae.c
glue.c
: libfreebsd_network.a attansic_l2_mii.a
;
@@ -0,0 +1,29 @@
/*
* Copyright 2007, Hugo Santos. All Rights Reserved.
* Copyright 2007, Axel Dörfler, [email protected]. All Rights Reserved.
* Distributed under the terms of the MIT License.
*/
#include <sys/bus.h>
HAIKU_FBSD_DRIVER_GLUE(attansic_l2, ae, pci)
extern driver_t *DRIVER_MODULE_NAME(ukphy, miibus);
driver_t *
__haiku_select_miibus_driver(device_t dev)
{
driver_t *drivers[] = {
DRIVER_MODULE_NAME(ukphy, miibus),
NULL
};
return __haiku_probe_miibus(dev, drivers);
}
NO_HAIKU_CHECK_DISABLE_INTERRUPTS();
NO_HAIKU_REENABLE_INTERRUPTS();
HAIKU_DRIVER_REQUIREMENTS(FBSD_TASKQUEUES | FBSD_FAST_TASKQUEUE | FBSD_SWI_TASKQUEUE);
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,339 @@
/*-
* Copyright (c) 2008 Stanislav Sedov <[email protected]>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* Master configuration register
*/
#define AE_MASTER_REG 0x1400
#define AE_MASTER_SOFT_RESET 0x1 /* Reset adapter. */
#define AE_MASTER_MTIMER_EN 0x2 /* Unknown. */
#define AE_MASTER_IMT_EN 0x4 /* Interrupt moderation timer enable. */
#define AE_MASTER_MANUAL_INT 0x8 /* Software manual interrupt. */
#define AE_MASTER_REVNUM_SHIFT 16 /* Chip revision number. */
#define AE_MASTER_REVNUM_MASK 0xff
#define AE_MASTER_DEVID_SHIFT 24 /* PCI device id. */
#define AE_MASTER_DEVID_MASK 0xff
/*
* Interrupt status register
*/
#define AE_ISR_REG 0x1600
#define AE_ISR_TIMER 0x00000001 /* Counter expired. */
#define AE_ISR_MANUAL 0x00000002 /* Manual interrupt occuried. */
#define AE_ISR_RXF_OVERFLOW 0x00000004 /* RxF overflow occuried. */
#define AE_ISR_TXF_UNDERRUN 0x00000008 /* TxF underrun occuried. */
#define AE_ISR_TXS_OVERFLOW 0x00000010 /* TxS overflow occuried. */
#define AE_ISR_RXS_OVERFLOW 0x00000020 /* Internal RxS ring overflow. */
#define AE_ISR_LINK_CHG 0x00000040 /* Link state changed. */
#define AE_ISR_TXD_UNDERRUN 0x00000080 /* TxD underrun occuried. */
#define AE_ISR_RXD_OVERFLOW 0x00000100 /* RxD overflow occuried. */
#define AE_ISR_DMAR_TIMEOUT 0x00000200 /* DMA read timeout. */
#define AE_ISR_DMAW_TIMEOUT 0x00000400 /* DMA write timeout. */
#define AE_ISR_PHY 0x00000800 /* PHY interrupt. */
#define AE_ISR_TXS_UPDATED 0x00010000 /* Tx status updated. */
#define AE_ISR_RXD_UPDATED 0x00020000 /* Rx status updated. */
#define AE_ISR_TX_EARLY 0x00040000 /* TxMAC started transmit. */
#define AE_ISR_FIFO_UNDERRUN 0x01000000 /* FIFO underrun. */
#define AE_ISR_FRAME_ERROR 0x02000000 /* Frame receive error. */
#define AE_ISR_FRAME_SUCCESS 0x04000000 /* Frame receive success. */
#define AE_ISR_CRC_ERROR 0x08000000 /* CRC error occuried. */
#define AE_ISR_PHY_LINKDOWN 0x10000000 /* PHY link down. */
#define AE_ISR_DISABLE 0x80000000 /* Disable interrupts. */
#define AE_ISR_TX_EVENT (AE_ISR_TXF_UNDERRUN | AE_ISR_TXS_OVERFLOW | \
AE_ISR_TXD_UNDERRUN | AE_ISR_TXS_UPDATED | \
AE_ISR_TX_EARLY)
#define AE_ISR_RX_EVENT (AE_ISR_RXF_OVERFLOW | AE_ISR_RXS_OVERFLOW | \
AE_ISR_RXD_OVERFLOW | AE_ISR_RXD_UPDATED)
/* Interrupt mask register. */
#define AE_IMR_REG 0x1604
#define AE_IMR_DEFAULT (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT | \
AE_ISR_PHY | AE_ISR_PHY_LINKDOWN | \
AE_ISR_TXS_UPDATED | AE_ISR_RXD_UPDATED | \
AE_ISR_MANUAL)
/*
* Ethernet address register.
*/
#define AE_EADDR0_REG 0x1488 /* 5 - 2 bytes */
#define AE_EADDR1_REG 0x148c /* 1 - 0 bytes */
/*
* Desriptor rings registers.
* L2 supports 64-bit addressing but all rings base addresses
* should have the same high 32 bits of address.
*/
#define AE_DESC_ADDR_HI_REG 0x1540 /* High 32 bits of ring base address. */
#define AE_RXD_ADDR_LO_REG 0x1554 /* Low 32 bits of RxD ring address. */
#define AE_TXD_ADDR_LO_REG 0x1544 /* Low 32 bits of TxD ring address. */
#define AE_TXS_ADDR_LO_REG 0x154c /* Low 32 bits of TxS ring address. */
#define AE_RXD_COUNT_REG 0x1558 /* Number of RxD descriptors in ring.
Should be 120-byte aligned (i.e.
the 'data' field of RxD should
have 128-byte alignment). */
#define AE_TXD_BUFSIZE_REG 0x1548 /* Size of TxD ring in 4-byte units.
Should be 4-byte aligned. */
#define AE_TXS_COUNT_REG 0x1550 /* Number of TxS descriptors in ring.
4 byte alignment. */
#define AE_RXD_COUNT_MIN 16
#define AE_RXD_COUNT_MAX 512
#define AE_RXD_COUNT_DEFAULT 64
#define AE_TXD_BUFSIZE_MIN 4096
#define AE_TXD_BUFSIZE_MAX 65536
#define AE_TXD_BUFSIZE_DEFAULT 8192
#define AE_TXS_COUNT_MIN 8 /* Not sure. */
#define AE_TXS_COUNT_MAX 160
#define AE_TXS_COUNT_DEFAULT 64 /* AE_TXD_BUFSIZE_DEFAULT / 128 */
/*
* Inter-frame gap configuration register.
*/
#define AE_IFG_REG 0x1484
#define AE_IFG_TXIPG_DEFAULT 0x60 /* 96-bit IFG time. */
#define AE_IFG_TXIPG_SHIFT 0
#define AE_IFG_TXIPG_MASK 0x7f
#define AE_IFG_RXIPG_DEFAULT 0x50 /* 80-bit IFG time. */
#define AE_IFG_RXIPG_SHIFT 8
#define AE_IFG_RXIPG_MASK 0xff00
#define AE_IFG_IPGR1_DEFAULT 0x40 /* Carrier-sense window. */
#define AE_IFG_IPGR1_SHIFT 16
#define AE_IFG_IPGR1_MASK 0x7f0000
#define AE_IFG_IPGR2_DEFAULT 0x60 /* IFG window. */
#define AE_IFG_IPGR2_SHIFT 24
#define AE_IFG_IPGR2_MASK 0x7f000000
/*
* Half-duplex mode configuration register.
*/
#define AE_HDPX_REG 0x1498
/* Collision window. */
#define AE_HDPX_LCOL_SHIFT 0
#define AE_HDPX_LCOL_MASK 0x000003ff
#define AE_HDPX_LCOL_DEFAULT 0x37
/* Max retransmission time, after that the packet will be discarded. */
#define AE_HDPX_RETRY_SHIFT 12
#define AE_HDPX_RETRY_MASK 0x0000f000
#define AE_HDPX_RETRY_DEFAULT 0x0f
/* Alternative binary exponential back-off time. */
#define AE_HDPX_ABEBT_SHIFT 20
#define AE_HDPX_ABEBT_MASK 0x00f00000
#define AE_HDPX_ABEBT_DEFAULT 0x0a
/* IFG to start JAM for collision based flow control (8-bit time units).*/
#define AE_HDPX_JAMIPG_SHIFT 24
#define AE_HDPX_JAMIPG_MASK 0x0f000000
#define AE_HDPX_JAMIPG_DEFAULT 0x07
/* Allow the transmission of a packet which has been excessively deferred. */
#define AE_HDPX_EXC_EN 0x00010000
/* No back-off on collision, immediately start the retransmission. */
#define AE_HDPX_NO_BACK_C 0x00020000
/* No back-off on backpressure, immediately start the transmission. */
#define AE_HDPX_NO_BACK_P 0x00040000
/* Alternative binary exponential back-off enable. */
#define AE_HDPX_ABEBE 0x00080000
/*
* Interrupt moderation timer configuration register.
*/
#define AE_IMT_REG 0x1408 /* Timer value in 2 us units. */
#define AE_IMT_MAX 65000
#define AE_IMT_MIN 50
#define AE_IMT_DEFAULT 100 /* 200 microseconds. */
/*
* Interrupt clearing timer configuration register.
*/
#define AE_ICT_REG 0x140e /* Maximum time allowed to clear
interrupt. In 2 us units. */
#define AE_ICT_DEFAULT 50000 /* 100ms */
/*
* MTU configuration register.
*/
#define AE_MTU_REG 0x149c /* MTU size in bytes. */
/*
* Cut-through configuration register.
*/
#define AE_CUT_THRESH_REG 0x1590 /* Cut-through threshold in unknown units. */
#define AE_CUT_THRESH_DEFAULT 0x177
/*
* Flow-control configuration registers.
*/
#define AE_FLOW_THRESH_HI_REG 0x15a8 /* High watermark of RxD
overflow threshold. */
#define AE_FLOW_THRESH_LO_REG 0x15aa /* Lower watermark of RxD
overflow threshold */
/*
* Mailbox configuration registers.
*/
#define AE_MB_TXD_IDX_REG 0x15f0 /* TxD read index. */
#define AE_MB_RXD_IDX_REG 0x15f4 /* RxD write index. */
/*
* DMA configuration registers.
*/
#define AE_DMAREAD_REG 0x1580 /* Read DMA configuration register. */
#define AE_DMAREAD_EN 1
#define AE_DMAWRITE_REG 0x15a0 /* Write DMA configuration register. */
#define AE_DMAWRITE_EN 1
/*
* MAC configuration register.
*/
#define AE_MAC_REG 0x1480
#define AE_MAC_TX_EN 0x00000001 /* Enable transmit. */
#define AE_MAC_RX_EN 0x00000002 /* Enable receive. */
#define AE_MAC_TX_FLOW_EN 0x00000004 /* Enable Tx flow control. */
#define AE_MAC_RX_FLOW_EN 0x00000008 /* Enable Rx flow control. */
#define AE_MAC_LOOPBACK 0x00000010 /* Loopback at MII. */
#define AE_MAC_FULL_DUPLEX 0x00000020 /* Enable full-duplex. */
#define AE_MAC_TX_CRC_EN 0x00000040 /* Enable CRC generation. */
#define AE_MAC_TX_AUTOPAD 0x00000080 /* Pad short frames. */
#define AE_MAC_PREAMBLE_MASK 0x00003c00 /* Preamble length. */
#define AE_MAC_PREAMBLE_SHIFT 10
#define AE_MAC_PREAMBLE_DEFAULT 0x07 /* By standard. */
#define AE_MAC_RMVLAN_EN 0x00004000 /* Remove VLAN tags in
incoming packets. */
#define AE_MAC_PROMISC_EN 0x00008000 /* Enable promiscue mode. */
#define AE_MAC_TX_MAXBACKOFF 0x00100000 /* Unknown. */
#define AE_MAC_MCAST_EN 0x02000000 /* Pass all multicast frames. */
#define AE_MAC_BCAST_EN 0x04000000 /* Pass all broadcast frames. */
#define AE_MAC_CLK_PHY 0x08000000 /* If 1 uses loopback clock
PHY, if 0 - system clock. */
#define AE_HALFBUF_MASK 0xf0000000 /* Half-duplex retry buffer. */
#define AE_HALFBUF_SHIFT 28
#define AE_HALFBUF_DEFAULT 2 /* XXX: From Linux. */
/*
* MDIO control register.
*/
#define AE_MDIO_REG 0x1414
#define AE_MDIO_DATA_MASK 0xffff
#define AE_MDIO_DATA_SHIFT 0
#define AE_MDIO_REGADDR_MASK 0x1f0000
#define AE_MDIO_REGADDR_SHIFT 16
#define AE_MDIO_READ 0x00200000 /* Read operation. */
#define AE_MDIO_SUP_PREAMBLE 0x00400000 /* Suppress preamble. */
#define AE_MDIO_START 0x00800000 /* Initiate MDIO transfer. */
#define AE_MDIO_CLK_SHIFT 24 /* Clock selection. */
#define AE_MDIO_CLK_MASK 0x07000000 /* Clock selection. */
#define AE_MDIO_CLK_25_4 0 /* Dividers? */
#define AE_MDIO_CLK_25_6 2
#define AE_MDIO_CLK_25_8 3
#define AE_MDIO_CLK_25_10 4
#define AE_MDIO_CLK_25_14 5
#define AE_MDIO_CLK_25_20 6
#define AE_MDIO_CLK_25_28 7
#define AE_MDIO_BUSY 0x08000000 /* MDIO is busy. */
/*
* Idle status register.
*/
#define AE_IDLE_REG 0x1410
/*
* Idle status bits.
* If bit is set then the corresponding module is in non-idle state.
*/
#define AE_IDLE_RXMAC 1
#define AE_IDLE_TXMAC 2
#define AE_IDLE_DMAREAD 8
#define AE_IDLE_DMAWRITE 4
/*
* Multicast hash tables registers.
*/
#define AE_REG_MHT0 0x1490
#define AE_REG_MHT1 0x1494
/*
* PCIE configuration registers. Descriptions unknown.
*/
#define AE_LTSSM_TESTMODE_REG 0x12fc
#define AE_LTSSM_TESTMODE_DEFAULT 0x6500
#define AE_DLL_TX_REG 0x1104
#define AE_DLL_TX_SEL_NOR_CLK 0x0400
#define AE_DLL_TX_DEFAULT 0x0568
/*
* PHY enable register.
*/
#define AE_PHY_ENABLE_REG 0x140c
#define AE_PHY_ENABLE 1
/*
* VPD registers.
*/
#define AE_VPD_CAP_REG 0x6c /* Command register. */
#define AE_VPD_CAP_ID_MASK 0xff
#define AE_VPD_CAP_ID_SHIFT 0
#define AE_VPD_CAP_NEXT_MASK 0xff00
#define AE_VPD_CAP_NEXT_SHIFT 8
#define AE_VPD_CAP_ADDR_MASK 0x7fff0000
#define AE_VPD_CAP_ADDR_SHIFT 16
#define AE_VPD_CAP_DONE 0x80000000
#define AE_VPD_DATA_REG 0x70 /* Data register. */
#define AE_VPD_NREGS 64 /* Maximum number of VPD regs. */
#define AE_VPD_SIG_MASK 0xff
#define AE_VPD_SIG 0x5a /* VPD block signature. */
#define AE_VPD_REG_SHIFT 16 /* Register id offset. */
/*
* SPI registers.
*/
#define AE_SPICTL_REG 0x200
#define AE_SPICTL_VPD_EN 0x2000 /* Enable VPD. */
/*
* Tx descriptors flags.
*/
#define AE_TXF_SUCCESS 0x0001
/*
* Rx descriptors flags.
*/
#define AE_RXF_SUCCESS 0x0001
@@ -0,0 +1,144 @@
/*-
* Copyright (c) 2008 Stanislav Sedov <[email protected]>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef IF_AEVAR_H
#define IF_AEVAR_H
/*
* Supported chips identifiers.
*/
#define VENDORID_ATTANSIC 0x1969
#define DEVICEID_ATTANSIC_L2 0x2048
/* How much to wait for reset to complete (10 microsecond units). */
#define AE_RESET_TIMEOUT 100
/* How much to wait for device to enter idle state (100 microsecond units). */
#define AE_IDLE_TIMEOUT 100
/* How much to wait for MDIO to do the work (2 microsecond units). */
#define AE_MDIO_TIMEOUT 10
/* How much to wait for VPD reading operation to complete (2 ms units). */
#define AE_VPD_TIMEOUT 10
/* How much to wait for send operation to complete (HZ units). */
#define AE_TX_TIMEOUT 5
/* Default PHY address. */
#define AE_PHYADDR_DEFAULT 0
/* Tx packet descriptor header format. */
typedef struct ae_txd {
uint16_t len;
uint16_t vlan;
} __packed ae_txd_t;
/* Tx status descriptor format. */
typedef struct ae_txs {
uint16_t len;
uint16_t flags:15;
uint16_t update:1;
} __packed ae_txs_t;
/* Rx packet descriptor format. */
typedef struct ae_rxd {
uint16_t len;
uint16_t flags:15;
uint16_t update:1;
uint16_t vlan;
uint16_t __pad;
uint8_t data[1528];
} __packed ae_rxd_t;
/* Software state structure. */
typedef struct ae_softc {
struct ifnet *ifp;
device_t dev;
device_t miibus;
struct resource *mem[1];
struct resource_spec *spec_mem;
struct resource *irq[1];
struct resource_spec *spec_irq;
void *intrhand;
struct mtx mtx;
int phyaddr;
uint8_t eaddr[ETHER_ADDR_LEN];
uint8_t flags;
int if_flags;
struct callout tick_ch;
/* Tasks. */
struct task int_task;
struct task tx_task;
struct task link_task;
struct taskqueue *tq;
/* DMA tags. */
bus_dma_tag_t dma_parent_tag;
bus_dma_tag_t dma_rxd_tag;
bus_dma_tag_t dma_txd_tag;
bus_dma_tag_t dma_txs_tag;
bus_dmamap_t dma_rxd_map;
bus_dmamap_t dma_txd_map;
bus_dmamap_t dma_txs_map;
bus_addr_t dma_rxd_busaddr;
bus_addr_t dma_txd_busaddr;
bus_addr_t dma_txs_busaddr;
char *rxd_base_dma; /* Start of allocated area. */
ae_rxd_t *rxd_base; /* Start of RxD ring. */
char *txd_base; /* Start of TxD ring. */
ae_txs_t *txs_base; /* Start of TxS ring. */
/* Ring pointers. */
unsigned int rxd_cur;
unsigned int txd_cur;
unsigned int txs_cur;
unsigned int txs_ack;
unsigned int txd_ack;
int tx_inproc; /* Active Tx frames in ring. */
int wd_timer;
} ae_softc_t;
#define AE_LOCK(_sc) mtx_lock(&(_sc)->mtx)
#define AE_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
#define AE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
#define BUS_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF)
#define BUS_ADDR_HI(x) ((uint64_t) (x) >> 32)
#define AE_FLAG_LINK 0x01 /* Has link. */
#define AE_FLAG_DETACH 0x02 /* Is detaching. */
#define AE_FLAG_TXAVAIL 0x04 /* Txes available. */
#endif /* IF_AEVAR_H */
@@ -0,0 +1,15 @@
SubDir HAIKU_TOP src add-ons kernel drivers network attansic_l2 dev mii ;
UsePrivateHeaders kernel net ;
UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ;
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ;
KernelStaticLibrary attansic_l2_mii.a
:
ukphy.c
ukphy_subr.c
;
@@ -0,0 +1,220 @@
/* $NetBSD: ukphy.c,v 1.2 1999/04/23 04:24:32 thorpej Exp $ */
/*-
* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center, and by Frank van der Linden.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*-
* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Manuel Bouyer.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy.c,v 1.20 2007/01/20 00:52:29 marius Exp $");
/*
* driver for generic unknown PHYs
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#include <sys/errno.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <net/if.h>
#include <net/if_media.h>
#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
#include "miibus_if.h"
static int ukphy_probe(device_t);
static int ukphy_attach(device_t);
static device_method_t ukphy_methods[] = {
/* device interface */
DEVMETHOD(device_probe, ukphy_probe),
DEVMETHOD(device_attach, ukphy_attach),
DEVMETHOD(device_detach, mii_phy_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
{ 0, 0 }
};
static devclass_t ukphy_devclass;
static driver_t ukphy_driver = {
"ukphy",
ukphy_methods,
sizeof(struct mii_softc)
};
DRIVER_MODULE(ukphy, miibus, ukphy_driver, ukphy_devclass, 0, 0);
static int ukphy_service(struct mii_softc *, struct mii_data *, int);
static int
ukphy_probe(device_t dev)
{
/*
* We know something is here, so always match at a low priority.
*/
device_set_desc(dev, "Generic IEEE 802.3u media interface");
return (BUS_PROBE_GENERIC);
}
static int
ukphy_attach(device_t dev)
{
struct mii_softc *sc;
struct mii_attach_args *ma;
struct mii_data *mii;
sc = device_get_softc(dev);
ma = device_get_ivars(dev);
sc->mii_dev = device_get_parent(dev);
mii = device_get_softc(sc->mii_dev);
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
if (bootverbose)
device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
MII_OUI(ma->mii_id1, ma->mii_id2),
MII_MODEL(ma->mii_id2), MII_REV(ma->mii_id2));
sc->mii_inst = mii->mii_instance;
sc->mii_phy = ma->mii_phyno;
sc->mii_service = ukphy_service;
sc->mii_pdata = mii;
mii->mii_instance++;
mii_phy_reset(sc);
sc->mii_capabilities =
PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
if (sc->mii_capabilities & BMSR_EXTSTAT)
sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
device_printf(dev, " ");
mii_phy_add_media(sc);
printf("\n");
MIIBUS_MEDIAINIT(sc->mii_dev);
mii_phy_setmedia(sc);
return (0);
}
static int
ukphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
{
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
int reg;
switch (cmd) {
case MII_POLLSTAT:
/*
* If we're not polling our PHY instance, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
return (0);
break;
case MII_MEDIACHG:
/*
* If the media indicates a different PHY instance,
* isolate ourselves.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
reg = PHY_READ(sc, MII_BMCR);
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
return (0);
}
/*
* If the interface is not up, don't do anything.
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
break;
mii_phy_setmedia(sc);
break;
case MII_TICK:
/*
* If we're not currently selected, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
return (0);
if (mii_phy_tick(sc) == EJUSTRETURN)
return (0);
break;
}
/* Update the media status. */
ukphy_status(sc);
/* Callback if something changed. */
mii_phy_update(sc, cmd);
return (0);
}
@@ -0,0 +1,129 @@
/* $NetBSD: ukphy_subr.c,v 1.2 1998/11/05 04:08:02 thorpej Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center, and by Frank van der Linden.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy_subr.c,v 1.8.8.1 2006/07/19 04:40:26 yongari Exp $");
/*
* Subroutines shared by the ukphy driver and other PHY drivers.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/socket.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <net/if.h>
#include <net/if_media.h>
#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
#include "miibus_if.h"
/*
* Media status subroutine. If a PHY driver does media detection simply
* by decoding the NWay autonegotiation, use this routine.
*/
void
ukphy_status(struct mii_softc *phy)
{
struct mii_data *mii = phy->mii_pdata;
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
int bmsr, bmcr, anlpar, gtcr, gtsr;
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR);
if (bmsr & BMSR_LINK)
mii->mii_media_status |= IFM_ACTIVE;
bmcr = PHY_READ(phy, MII_BMCR);
if (bmcr & BMCR_ISO) {
mii->mii_media_active |= IFM_NONE;
mii->mii_media_status = 0;
return;
}
if (bmcr & BMCR_LOOP)
mii->mii_media_active |= IFM_LOOP;
if (bmcr & BMCR_AUTOEN) {
/*
* NWay autonegotiation takes the highest-order common
* bit of the ANAR and ANLPAR (i.e. best media advertised
* both by us and our link partner).
*/
if ((bmsr & BMSR_ACOMP) == 0) {
/* Erg, still trying, I guess... */
mii->mii_media_active |= IFM_NONE;
return;
}
anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR);
if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 &&
(phy->mii_extcapabilities &
(EXTSR_1000THDX | EXTSR_1000TFDX)) != 0) {
gtcr = PHY_READ(phy, MII_100T2CR);
gtsr = PHY_READ(phy, MII_100T2SR);
} else
gtcr = gtsr = 0;
if ((gtcr & GTCR_ADV_1000TFDX) && (gtsr & GTSR_LP_1000TFDX))
mii->mii_media_active |= IFM_1000_T|IFM_FDX;
else if ((gtcr & GTCR_ADV_1000THDX) &&
(gtsr & GTSR_LP_1000THDX))
mii->mii_media_active |= IFM_1000_T;
else if (anlpar & ANLPAR_T4)
mii->mii_media_active |= IFM_100_T4;
else if (anlpar & ANLPAR_TX_FD)
mii->mii_media_active |= IFM_100_TX|IFM_FDX;
else if (anlpar & ANLPAR_TX)
mii->mii_media_active |= IFM_100_TX;
else if (anlpar & ANLPAR_10_FD)
mii->mii_media_active |= IFM_10_T|IFM_FDX;
else if (anlpar & ANLPAR_10)
mii->mii_media_active |= IFM_10_T;
else
mii->mii_media_active |= IFM_NONE;
} else
mii->mii_media_active = ife->ifm_media;
}