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This should handle TLB flushing on m68k (it's called ATC though).

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22706 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
François Revol
2007-10-25 00:45:01 +00:00
parent 8848d5972f
commit ee75f8527b
2 changed files with 27 additions and 31 deletions
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headers/private/kernel/arch/m68k/arch_cpu.h
+16 -1
View File
@@ -142,7 +142,7 @@ enum machine_state {
MSR_DATA_ADDRESS_TRANSLATION = 1L << 4, // DR MSR_DATA_ADDRESS_TRANSLATION = 1L << 4, // DR
}; };
struct block_address_translation; //struct block_address_translation;
typedef struct arch_cpu_info { typedef struct arch_cpu_info {
int null; int null;
@@ -153,6 +153,8 @@ typedef struct arch_cpu_info {
extern "C" { extern "C" {
#endif #endif
#if 0
//PPC stuff
extern uint32 get_sdr1(void); extern uint32 get_sdr1(void);
extern void set_sdr1(uint32 value); extern void set_sdr1(uint32 value);
extern uint32 get_sr(void *virtualAddress); extern uint32 get_sr(void *virtualAddress);
@@ -181,6 +183,7 @@ extern void get_dbat3(struct block_address_translation *bat);
extern void reset_ibats(void); extern void reset_ibats(void);
extern void reset_dbats(void); extern void reset_dbats(void);
#endif
//extern void sethid0(unsigned int val); //extern void sethid0(unsigned int val);
//extern unsigned int getl2cr(void); //extern unsigned int getl2cr(void);
@@ -201,6 +204,12 @@ extern bool m68k_set_fault_handler(addr_t *handlerLocation, addr_t handler)
} }
#endif #endif
#define m68k_nop() asm volatile("nop") /* flushes insn pipeline */
#define pflush(addr) asm volatile("pflush (%0)" :: "a" (addr))
#define pflusha() asm volatile("pflusha")
//#define
#if 0
#define eieio() asm volatile("eieio") #define eieio() asm volatile("eieio")
#define isync() asm volatile("isync") #define isync() asm volatile("isync")
#define tlbsync() asm volatile("tlbsync") #define tlbsync() asm volatile("tlbsync")
@@ -243,11 +252,17 @@ enum m68k_processor_version {
MPC7410 = 0x800c, MPC7410 = 0x800c,
MPC8245 = 0x8081, MPC8245 = 0x8081,
}; };
#endif
/* /*
Use of (some) special purpose registers. Use of (some) special purpose registers.
SRP[63-32]: current struct thread*
SRP[31-0] :
CAAR : can we use it ??
PPC:
SPRG0: per CPU physical address pointer to an ppc_cpu_exception_context SPRG0: per CPU physical address pointer to an ppc_cpu_exception_context
structure structure
SPRG1: scratch SPRG1: scratch
src/system/kernel/arch/m68k/arch_cpu.cpp
+11 -30
View File
@@ -85,15 +85,13 @@ arch_cpu_sync_icache(void *address, size_t len)
void void
arch_cpu_invalidate_TLB_range(addr_t start, addr_t end) arch_cpu_invalidate_TLB_range(addr_t start, addr_t end)
{ {
asm volatile("sync"); m68k_nop();
while (start < end) { while (start < end) {
asm volatile("tlbie %0" :: "r" (start)); pflush(start);
asm volatile("eieio"); m68k_nop();
asm volatile("sync");
start += B_PAGE_SIZE; start += B_PAGE_SIZE;
} }
asm volatile("tlbsync"); m68k_nop();
asm volatile("sync");
} }
@@ -102,39 +100,22 @@ arch_cpu_invalidate_TLB_list(addr_t pages[], int num_pages)
{ {
int i; int i;
asm volatile("sync"); m68k_nop();
for (i = 0; i < num_pages; i++) { for (i = 0; i < num_pages; i++) {
asm volatile("tlbie %0" :: "r" (pages[i])); asm volatile("tlbie %0" :: "r" (pages[i]));
asm volatile("eieio"); pflush(pages[i]);
asm volatile("sync"); m68k_nop();
} }
asm volatile("tlbsync"); m68k_nop();
asm volatile("sync");
} }
void void
arch_cpu_global_TLB_invalidate(void) arch_cpu_global_TLB_invalidate(void)
{ {
if (sHasTlbia) { m68k_nop();
m68k_sync(); pflush();
tlbia(); m68k_nop();
m68k_sync();
} else {
addr_t address = 0;
unsigned long i;
m68k_sync();
for (i = 0; i < 0x100000; i++) {
tlbie(address);
eieio();
m68k_sync();
address += B_PAGE_SIZE;
}
tlbsync();
m68k_sync();
}
} }